The document discusses average current mode control (ACMC) in switching power supplies. It describes how ACMC improves upon peak current mode control by introducing a high-gain integrating current error amplifier into the current loop. This allows the average current to track the desired program level more accurately and provides better noise immunity, stability without slope compensation, and ability to control currents in any circuit branch. The document also discusses various ACMC circuit implementations and their advantages, including true average current control using a low-pass filter to isolate the average current value.

1. Current mode control as usually implemented in switching power supplies
actually senses and controls peak inductor current. This gives rise to many
serious problems, including poor noise immunity, a need for slope
compensation, and peak-to-average current errors which the inherently
low current loop gain cannot correct.
Average current mode control eliminates these problems and may be used
effectively to control currents other than inductor current.
The objective of this inner loop is to control the state-space averaged
inductor current, but in practice the instantaneous peak inductor current is
the basis for control. (Switch current --equal to inductor current during the
“on” time--is often sensed.) If the inductor ripple current is small, peak
inductor current control is nearly equivalent to average inductor current
control.
In a conventional switching power supply employing a buck derived
topology, the inductor is in the output. Current mode control then is
actually output current control, resulting in many performance
advantages.
Poor noise immunity. The peak method of inductor current control
functions by comparing the upslope of inductor current (or switch current)
to a current program level set by the outer loop-see Fig. 1. The comparator
turns the power switch off when the instantaneous current reaches the
desired level. The current ramp is usually quite small compared to the
programming level, especially when VIN is low. As a result, this method
is extremely susceptible to noise. A noise spike is generated each time the
switch turns on.

2. A fraction of a volt coupled into the control circuit can cause it to turn
off immediately, resulting in a subharmonic operating mode with much
greater ripple.
Slope compensation required. The peak current mode control method is
inherently unstable at duty ratios exceeding 0.5 resulting in sub-harmonic
oscillation. A compensating ramp (with slope equal to the inductor current
downslope) is usually applied to the comparator input to eliminate this
instability. In a buck regulator the inductor current downslope equals
Vo/L. With V. constant, as it usually is, the compensating ramp is fixed
and easy to calculate-but it does complicate the design. A fixed ramp
providing adequate compensation will overcompensate much of the time,
with resulting performance degradation and increased distortion. Peak
current mode control operates by directly comparing the actual inductor
current waveform to the current program level (set by the outer loop) at
the two inputs of the PWM comparator. This current loop has low gain
and so cannot correct for the deficiencies.
Referring to Fig. 2, the technique of average current mode control
overcomes these problems by introducing a high gain integrating current
error amplifier (CA) into the current loop. A voltage across R, (set by the
outer loop) represents the desired current program level. The voltage
across current sense resistor Rs, represents actual inductor current. The
difference, or current error, is amplified and compared to a large
amplitude sawtooth (oscillator ramp) at the PWM comparator inputs.

3. The gain-bandwidth characteristic of the current loop can be tailored for
optimum performance by the compensation network around the CA.
Compared with peak current mode control, the current loop gain crossover
frequency, fc, can be made approximately the same, but the gain will be
much greater at lower frequencies.
The result is:
1) Average current tracks the current program with a high degree of
accuracy. This is especially important in high power factor preregulators,
enabling less than 3% harmonic distortion to be achieved with a relatively
small inductor.
2) Slope compensation is not required, there is a limit to loop gain at the
switching frequency in order to achieve stability.
3) Noise immunity is excellent. When the clock pulse turns the power
switch on, the oscillator ramp immediately dives to its lowest level, volts
away from the corresponding current error level at the input of the PWM
comparator.
4) The average current mode method can be used to sense and control
the current in any circuit branch.
Designing the Optimum Control Loop Gain Limitation at fs:
Switching power supply control circuits all exhibit subharmonic
oscillation problems if the slopes of the waveforms applied to the two
inputs of the PWM comparator are inappropriately related. With peak

4. current mode control, slope compensation prevents this instability.
Average current mode control has a very similar problem, but a better
solution. The oscillator ramp effectively provides a great amount of slope
compensation. one criterion applies in a single pole system: The amplified
inductor current downslope at one input of the PWM comparator must not
exceed the oscillator ramp slope at the other comparator input. This
criterion puts an upper limit on the current amplifier gain at the
switching frequency, indirectly establishing the maximum current loop
gain crossover frequency, fc. It is the first thing that needs to be considered
in optimizing the average current mode control loop.
The inductor current is sensed through Rs. The inductor current waveform
with its sawtooth ripple component is amplified and inverted through the
CA and applied to the comparator. The inductor current downslope
(switch is off) becomes an upslope, as shown in Fig. 2. To avoid
subharmonic oscillation, this off-time CA output slope must not exceed
the oscillator ramp slope. In Fig. 2, the off-time CA output slope is much
less than the oscillator ramp slope, indicating that the CA gain is less than
optimum.
Calculating the slopes:
Inductor Current Downslope = Vo/L
Oscillator Ramp Slope = Vs/Ts = Vsfs.
Where Vs is the oscillator ramp p-p voltage, Ts and fs are the switching
period and frequency.
The inductor current downslope is translated into a voltage across current
sense resistor Rs and multiplied by the CA gain, GU This is set equal to
the oscillator ramp slope to determine the CA gain allowed at fs:
--------------------- (1)

5. Applying the values given in the example, and with Vs of 5Vpp, the maximum GCA at the switching
frequency is 25 (28dB). The current error amplifier gain at fs is set to this optimum value by
making the ratio Rf/R1, = 25.
The small-signal control-to-output gain of the buck regulator current
loop power section (from VCA at the CA output, to VRS, the voltage
across RS ) is:
--------------(2)
The overall open loop gain of the current loop is found by multiplying
(1) and (2). The result is set to for the loop gain crossover frequency, fc :
Setting the CA gain at the limit found in (1), the crossover frequency
will never be less than one sixth of the switching frequency.
In this example, fc is 20 kHz with VIN, at 15V (D= .8), and 40 kHz when
VIN at 30V (D= .4).
Fig. 3 shows the start-up waveforms of the voltages at the PWM
comparator inputs and the inductor current with VIN, at 30V and full
load.

6. Pole RF, CFP CFz/(CFP+ CFz) is set at switching frequency fs (100 kHz). This pole has one
purpose-to eliminate noise spikes riding on the current waveform.
Discontinuous Operation. When the load current I, becomes small, the inductor current
becomes discontinuous. The current level at the continuous/discontinuous mode boundary is:
In the discontinuous mode, below the mode boundary, changes in I, require large duty cycle
changes. But with average current mode control, the high gain of the current error amplifier
provides the large duty cycle changes necessary to accommodate changes in load current,
thereby maintaining good average current regulation. when the current loop is closed, the voltage
across current sense resistor VRS equals the current programming voltage VCA (from the voltage
error amplifier) at frequencies below fs. The transconductance of the closed current loop is a part
of the outer voltage control loop:
The closed loop transconductance rolls off and assumes a single pole characteristic at the open
loop crossover frequency, fs. [1]
True Average Circuit with Control Loops.

7. In the conventional average current-mode control, the time-varying average value of the
sensed inductor current is regulated.
Fig. 1.2 shows the circuit of a buck dc-dc converter with the conventional average current-mode
control scheme.
The reference to the current loop is set by the outer loop. The outer voltage loop is set to be
equal to the desired inductor current average. A high gain integrating amplifier in the current
loop attempts the track the average value of the inductor current and outputs the amplified
current error to a pulse-width modulator.

8. The amplified current error is compared to a large amplitude sawtooth waveform oscillating at
the switching frequency at the PWM comparator inputs.
Although, the conventional average current-mode control has unique advantages over peak
current-mode, a few challenges were encountered.
True AVG Current Method:
The compensation circuit and the low-pass filter are decoupled and they function independently.
The sensed voltage due to the inductor current is provided to a lowpass filter dedicated only to
cancel its switching frequency component.
The output voltage of the low-pass filter with a reduced switching frequency ripple component
is provided to the control circuit. Thus, the control voltage also exhibits a reduced ripple.

9. The sense resistor or current sensor is placed in the inductor branch to sense the inductor
current. The sensed voltage is vRS. The sensed voltage is provided to an LPF composed of a R
and C network.
The switching frequency component is eliminated by the LPF, therefore, the filter output
voltage is dc with negligible ripple.
The effective feedback voltage to the inner loop is Vf1.
The reference voltage to the inner current loop vR1 is governed by the outer voltage loop.
Based on the desired parameters such as high bandwidth and high dc gain of the inner current
loop, an appropriate control circuit with forward path impedance Zii and the feedback path
impedance Zfi will be derived. The control voltage Vci at the output of the controller is
compared with a sawtooth waveform vsaw, which generates the duty cycle dT. By virtue of
circuit operation, the true average value of the inductor current (or any branch current) is
sensed and controlled by the inner current loop.

10. The major advantages of using the modified technique are:
1. The compensation and filtering processes are performed independently. A good selection of
the filter cutoff frequency assists the dynamic response.
2. The feedback voltage to the control circuit contains primarily the average value of the sensed
current and the switching frequency component is negligible.
Therefore, a discontinuous switch or diode current with large amplitudes, a continuous or
discontinuous inductor current of any amplitude, or the load current can be sensed by placing
the current sensor in the corresponding branch.
3. The low-pass filter can be placed either in the feedback path or the forward path to reduce
the ripple in the control voltage.
4. Due to the presence of the low-pass filter, the current loop does not behave as a sampling
system. Thus, the effect of sampling gain is eliminated.
5. The problems due to switching instability are completely avoided as the control voltage
intersects the carrier voltage only once during each switching period.

11. Average Current mode control (ACM Circuit 3): as usually implemented in switching power
supplies actually senses and controls peak inductor current.
This gives rise to many serious problems, including poor noise immunity, a need for slope
compensation, and peak-to-average current mirror which the inherently low current loop gain
cannot collect.
ACM control eliminates these problems and may be used effectively to control currents other
than inductor current, allowing a much broader range of topological application. [TI_avg]
Fig. 2, the technique of ACM control overcomes these problems by introducing a high gain
integrating current error amplifier (CA) into the current loop.
A voltage across Rp (set by the outer loop) represents the desired current program level.
The voltage across current sense resistor Rs represents actual inductor current.
The current error, is amplified and compared to a large amplitude sawtooth (oscillator ramp) at
the PWM comparator inputs.
The gain-bandwidth characteristic of the current loop can be tailored for optimum performance
by the compensation network around the CA.
Compared with peak current mode control, the current loop gain crossover frequency, Ie, can be
made approximately the same, but the gain will be much greater at lower frequencies.
The result is: 1) Average current tracks the current program with a high degree of accuracy.
This is especially important in high power factor preregulators, enabling less than 3% harmonic
distortion to be achieved with a relatively small inductor.
In fact, average current mode control functions well even when the mode boundary is crossed
into the discontinuous mode at low current levels. The outer voltage control loop is oblivious to
this mode change.

12. 2) Slope compensation is not required, but Texas Instruments 3 SLUP091 there is a limit to loop
gain at the switching frequency in order to achieve stability.
3) Noise immunity is excellent. When the clock pulse turns the power switch on, the oscillator
ramp immediately dives to its lowest level, volts away from the corresponding current error level
at the input of the PWM comparator.
4) The average current mode method can be used to sense and control the current in any circuit
branch.
Thus it can control input current accurately with buck and flyback topologies, and can control
output current with boost and flyback topologies.
CFACC (Circuit 5):
Chirin_2007:

13. A buck converter with CFACMC is shown in Fig. 1. To implement CFACMC, a LPF circuit,
Pc,(s), is added to the conventional ACMC circuit to provide a feedforward path to the voltage
loop.
The inductor current is sensed by a resistor Rs and amplified by a current sensing amplifier
(CSA) to give the sensed current signal ViL. Besides being fed back to a current controller,
ViL is also fed forward through P,I(s) to sum with the output signal from a voltage controller,
Vcv, to form the control signal, Vc.
The difference between Vc, which represents the desired current, and ViL, which represents the
actual inductor current, is amplified by the current controller.
The resulting current error signal, VcI, is then compared with the sawtooth voltage, Vk,, to
generate the duty cycle signal, d, to drive the MOSFET.
The invention(US7196_good) described herein provides a method of accurately capturing the
average value of a piecewise linear switching current waveform of various types of pulse width
modulation (PWM) power converters.
The current wave form is typically a ramp-on-a-step waveform, where the average value is
provided on a pulse-by-pulse basis, where the average value is captured (sampled and held) and
presented at the end of each current pulse. The captured value remains valid until the end of the
next current pulse, at which time it is updated with the new value. This average current output
information can then be used to implement average current mode operation or average current
limiting on a pulse-by-pulse basis. Alternatively this output is filtered to provide a time averaged
current indication.
, the current averaging circuit 100 is implemented onto a power management chip which controls
one or more electronic switches according to PWM operation to convert an input voltage VIN to
a regulated output voltage VOUT. Alternatively, discrete embodiments are contemplated in which
the current averaging method is implemented off-chip. For the on-chip embodiments, a current
sense (CS) input pin is provided for sensing the current in the PWM electronic switches as known
to those skilled in the art. Other current sensing techniques are known, where the CS pin or other
techniques provide a current sense (CS) signal on a CS node that generates a Voltage indicative of
current.
FIG. 1, a CS node developing a CS signal is coupled to one terminal of a first single-pole, single-
throw (SPST) switch SW0. As used herein, a node and the signal it carries assume the same name
unless otherwise indicated. The other terminal of SWO is coupled to a node A, which is coupled
to one end of a first capacitor C0 and to the input ofa first buffer U0. The other end of the capacitor
C0 is coupled to a common node, such as ground (GND). The output of the buffer UO is coupled

14. to one end of a resistor R0, having its other end coupled to a node C. The CS node is also coupled
to one terminal of another SPST switch SW1, having its other terminal coupled to a node B. Node
B is coupled to one end of a second capacitor C1 and to the input of a second buffer U1. The other
end of the capacitor C1 is coupled to GND. The output of the buffer U1 is coupled to one end of a
resistor R1, having its other end coupled to node C. Node C is coupled to one terminal of another
SPST switch SW2 and to one end of a capacitor C2, having its other end coupled to GND. The
other terminal of SW2 is coupled to a node D, which is coupled to the input of another buffer U2
and to one end of a capacitor C3. The other end of the capacitor C3 is coupled to GND. The output
of the buffer U2 is a node E providing an output voltage signal VIA that represents the average
value of the ramp-on-a-step current on a pulse-by-pulse basis. Switch SWO has a control input
receiving a control signal SHORT provided by a timing control circuit 101. The control circuit 101
also generates a control signal LONG provided to a control input of the switch SW1, and a control
signal AVERAGE provided to the control input of the switch SW2. In each case, when the control
signal (SHORT, LONG, AVERAGE) is de-asserted low, the switch (SWO, SW1, SW2) is open
and when the control signal is asserted high, the Switch is closed. The SPST switches SWO-SW2
may each be implemented in any Suitable manner as known to those skilled in the art, Such as
transistor devices or the like including field-effect transistors (FETs), metal-oxide-semiconductor
FETs (MOSFETs), bipolar-junction transistors (BJTs), complementary MOS (CMOS) devices
(e.g., N-channel devices or P-channel devices or a CMOS combination), etc. As shown, the timing
control circuit 101 receives one or more timing control (TC) signals for purposes of timing the
SHORT, LONG and AVERAGE signals. In the embodiment illustrated, the buffers UO and U1
have Substantially the same gain relative to each other, such as unity gain buffers or the like. The
buffer U2 is also a unity gain buffer so that node E is a buffered version of node D. The resistors
R0 and R1 have substantially the same resistance, so that node C develops a voltage that is the
average value of the voltages of the nodes A and B reflected at the outputs of the buffers U0 and
U1, respectively. For example, if the Voltages of the nodes A and B are the same. Such as 1 Volt
(V), then the node C is the same (e.g., 1V); and if the voltages of the nodes A and B are different,
such as 1V and 5V, respectively, then the node C is between the A and B voltages (e.g., 3V), and
so on. The resistors R0 and R1 can be thought of as a resistive differencing junction coupled to the
capacitor C2. The average Voltage on node C is transferred to node D by pulsing switch SW2, so
that node E represents an average value on a pulse-by-pulse basis. In an alternative embodiment,
another unity gain buffer may be inserted between capacitor C2 and switch SW2 to buffer the
average value developed on the capacitor C2 provided to charge the capacitor C3 during each
cycle.

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