This document summarizes a research paper that proposes a new rail-to-rail class-AB CMOS buffer circuit designed to drive large capacitive loads at high speed with low power dissipation. The proposed circuit uses a new leakage current reduction technique called LECTOR that adds leakage control transistors to reduce sub-threshold leakage current. Simulation results show the circuit operates at 3V with a propagation delay of 292.1×10-12 seconds and leakage current of 118.4μA, representing improvements over prior designs. The settling time is also improved to 41.12×10-9 seconds. In conclusion, the proposed buffer circuit achieves both high speed and low power operation suitable for driving large capacitive loads.
Fpga implementation of race control algorithm for full bridge prcp convertereSAT Publishing House
IJRET : International Journal of Research in Engineering and Technology is an international peer reviewed, online journal published by eSAT Publishing House for the enhancement of research in various disciplines of Engineering and Technology. The aim and scope of the journal is to provide an academic medium and an important reference for the advancement and dissemination of research results that support high-level learning, teaching and research in the fields of Engineering and Technology. We bring together Scientists, Academician, Field Engineers, Scholars and Students of related fields of Engineering and Technology.
An operational amplifier with recycling folded cascode topology and adaptive ...VLSICS Design
This paper presents a highly adaptive operational amplifier with high gain, high bandwidth, high speed
and low power consumption. By adopting the recycling folded cascode topology along with an adaptivebiasing
circuit, this design achieves high performance in terms of gain-bandwidth product (GBW) and slew
rate (SR). This single stage op-amp has been designed in 0.18μm technology with a power supply of 1.8V
and a 5pF load. The simulation results show that the amplifier achieved a GBW of 335.5MHz, Unity Gain
Bandwidth of 247.1MHz and a slew rate of 92.8V/μs.
IJRET : International Journal of Research in Engineering and Technology is an international peer reviewed, online journal published by eSAT Publishing House for the enhancement of research in various disciplines of Engineering and Technology. The aim and scope of the journal is to provide an academic medium and an important reference for the advancement and dissemination of research results that support high-level learning, teaching and research in the fields of Engineering and Technology. We bring together Scientists, Academician, Field Engineers, Scholars and Students of related fields of Engineering and Technology.
Design of High-Speed Dynamic Double-Tail ComparatorIJERDJOURNAL
ABSTRACT:- The analog-to-digital converters which are of ultra low-power, area efficient, and high speed converters are made of dynamic regenerative comparators. These comparators can maximize speed and power efficiency. The delay and power dissipation of dynamic comparators are analyzed in this paper. The delays and tradeoff can be explored. The circuit of a conventional double tail comparator in this analysis is modified for fast operation even in different supply voltages. By using power gating technique and adding few transistors, the positive feedback during the regeneration is strengthened in the proposed comparator structure. The delay time can be reduced by providing positive feedback instead of adding few transistors. The analysis results are going to be confirmed on the basis of 0.25-µm CMOS technology. The power consumption and delay time can be significantly reduced based on this analysis. All the simulation are made using TANNER TOOLS, Generic 250nm. The schematic are drawn in the T-SPICE schematic editor.
International Journal of Engineering Research and Development (IJERD)IJERD Editor
International Journal of Engineering Research and Development is an international premier peer reviewed open access engineering and technology journal promoting the discovery, innovation, advancement and dissemination of basic and transitional knowledge in engineering, technology and related disciplines.
Analysis of multiport dc dc converter in renewable energy sourceseSAT Publishing House
IJRET : International Journal of Research in Engineering and Technology is an international peer reviewed, online journal published by eSAT Publishing House for the enhancement of research in various disciplines of Engineering and Technology. The aim and scope of the journal is to provide an academic medium and an important reference for the advancement and dissemination of research results that support high-level learning, teaching and research in the fields of Engineering and Technology. We bring together Scientists, Academician, Field Engineers, Scholars and Students of related fields of Engineering and Technology.
Fpga implementation of race control algorithm for full bridge prcp convertereSAT Publishing House
IJRET : International Journal of Research in Engineering and Technology is an international peer reviewed, online journal published by eSAT Publishing House for the enhancement of research in various disciplines of Engineering and Technology. The aim and scope of the journal is to provide an academic medium and an important reference for the advancement and dissemination of research results that support high-level learning, teaching and research in the fields of Engineering and Technology. We bring together Scientists, Academician, Field Engineers, Scholars and Students of related fields of Engineering and Technology.
An operational amplifier with recycling folded cascode topology and adaptive ...VLSICS Design
This paper presents a highly adaptive operational amplifier with high gain, high bandwidth, high speed
and low power consumption. By adopting the recycling folded cascode topology along with an adaptivebiasing
circuit, this design achieves high performance in terms of gain-bandwidth product (GBW) and slew
rate (SR). This single stage op-amp has been designed in 0.18μm technology with a power supply of 1.8V
and a 5pF load. The simulation results show that the amplifier achieved a GBW of 335.5MHz, Unity Gain
Bandwidth of 247.1MHz and a slew rate of 92.8V/μs.
IJRET : International Journal of Research in Engineering and Technology is an international peer reviewed, online journal published by eSAT Publishing House for the enhancement of research in various disciplines of Engineering and Technology. The aim and scope of the journal is to provide an academic medium and an important reference for the advancement and dissemination of research results that support high-level learning, teaching and research in the fields of Engineering and Technology. We bring together Scientists, Academician, Field Engineers, Scholars and Students of related fields of Engineering and Technology.
Design of High-Speed Dynamic Double-Tail ComparatorIJERDJOURNAL
ABSTRACT:- The analog-to-digital converters which are of ultra low-power, area efficient, and high speed converters are made of dynamic regenerative comparators. These comparators can maximize speed and power efficiency. The delay and power dissipation of dynamic comparators are analyzed in this paper. The delays and tradeoff can be explored. The circuit of a conventional double tail comparator in this analysis is modified for fast operation even in different supply voltages. By using power gating technique and adding few transistors, the positive feedback during the regeneration is strengthened in the proposed comparator structure. The delay time can be reduced by providing positive feedback instead of adding few transistors. The analysis results are going to be confirmed on the basis of 0.25-µm CMOS technology. The power consumption and delay time can be significantly reduced based on this analysis. All the simulation are made using TANNER TOOLS, Generic 250nm. The schematic are drawn in the T-SPICE schematic editor.
International Journal of Engineering Research and Development (IJERD)IJERD Editor
International Journal of Engineering Research and Development is an international premier peer reviewed open access engineering and technology journal promoting the discovery, innovation, advancement and dissemination of basic and transitional knowledge in engineering, technology and related disciplines.
Analysis of multiport dc dc converter in renewable energy sourceseSAT Publishing House
IJRET : International Journal of Research in Engineering and Technology is an international peer reviewed, online journal published by eSAT Publishing House for the enhancement of research in various disciplines of Engineering and Technology. The aim and scope of the journal is to provide an academic medium and an important reference for the advancement and dissemination of research results that support high-level learning, teaching and research in the fields of Engineering and Technology. We bring together Scientists, Academician, Field Engineers, Scholars and Students of related fields of Engineering and Technology.
Low Power and Fast Transient High Swing CMOS Telescopic Operational AmplifierIJERA Editor
CMOS telescopic operational amplifier with high-swing and high-performance is described in this paper. The
swing is attained by using the tail and current source-transistors in deep-linear region. The resultant deprivation
in parameters like differential gain, CMRR and added characteristics are recompensed by using regulatedcascode
differential gain enhancement and a replica-tail feedback technique. Operating at power supply of 3.3V,
the power consumption, slew rate and settling time are improved using transmission controlled pass circuitry
and level amplifier. It is shown through simulations that the Op-Amp preserves its high CMRR and unity gain
frequency.
DESIGN & ANALYSIS OF A CHARGE RE-CYCLE BASED NOVEL LPHS ADIABATIC LOGIC CIRCU...VLSICS Design
This paper focuses on principles of adiabatic logic, its classification and comparison of various adiabatic logic designs. An attempt has been made in this paper to modify 2PASCL (Two Phase Adiabatic Static CMOS Logic) adiabatic logic circuit to minimize delay of the different 2PASCL circuit designs. This modifications in the circuits leads to improvement of Power Delay Product (PDP) which is one of the figure of merit to optimize the circuit with factors like power dissipation and delay of the circuit. This paper investigates the design approaches of low power adiabatic gates in terms of energy dissipation and uses of Simple PN diode instead of MOS diode which reduces the effect of Capacitances at high transition and power clock frequency. A computer simulation using SPECTRE from Cadence is carried out on different adiabatic circuits, such as Inverter, NAND, NOR, XOR and 2:1 MUX.
ANALYSIS OF SMALL-SIGNAL PARAMETERS OF 2-D MODFET WITH POLARIZATION EFFECTS F...VLSICS Design
An improved analytical two dimensional (2-D) model for AlGaN/GaN modulation doped field effect
transistor (MODFET) has been developed. The model is based on the solution of 2-D Poisson’s equation.
The model includes the spontaneous and piezoelectric polarization effects. The effects of field dependent
mobility, velocity saturation and parasitic resistances are included in the current voltage characteristics of
the developed two dimensional electron gas (2-DEG) model. The small-signal microwave parameters have
been evaluated to determine the output characteristics, device transconductance and cut-off frequency for
50 nm gate length. The peak transconductance of 165mS/mm and a cut-off frequency of 120 GHz have been
obtained. The results so obtained are in close agreement with experimental data, thereby proving the
validity of the model.
SIMULTANEOUS OPTIMIZATION OF STANDBY AND ACTIVE ENERGY FOR SUB-THRESHOLD CIRC...VLSICS Design
Increased downscaling of CMOS circuits with respect to feature size and threshold voltage has a result of dramatically increasing in leakage current. So, leakage power reduction is an important design issue for active and standby modes as long as the technology scaling increased. In this paper, a simultaneous active and standby energy optimization methodology is proposed for 22 nm sub-threshold CMOS circuits. In the first phase, we investigate the dual threshold voltage design for active energy per cycle minimization. A
slack based genetic algorithm is proposed to find the optimal reverse body bias assignment to set of noncritical
paths gates to ensure low active energy per cycle with the maximum allowable frequency at the optimal supply voltage. The second phase, determine the optimal reverse body bias that can be applied to all gates for standby power optimization at the optimal supply voltage determined from the first phase.
Therefore, there exist two sets of gates and two reverse body bias values for each set. The reverse body bias is switched between these two values in response to the mode of operation. Experimental results are obtained for some ISCAS-85 benchmark circuits such as 74L85, 74283, ALU74181, and 16 bit RCA. The optimized circuits show significant energy saving ranged (from 14.5% to 42.28%) and standby power
saving ranged (from 62.8% to 67%)
A 10-bit, 200MS/s CMOS Pipeline ADC using new shared opamp architecture VLSICS Design
A 10 bit opamp-sharing pipeline analog-to-digital converter (ADC) using a novel mirror telescopic operational amplifiers (opamp) with dual nmos differential inputs is presented. Reduction of power and area is achieved by completely merging the front-end sample-and-hold amplifier (SHA) into the first multiplying digital-to-analog converter (MDAC) using the proposed opamp. Transistors in the opamp are always biased in saturation to avoid increase of settling time due to opamp turn-on delays. The design targets 0.18um CMOS process for operation, at 200MS/s from a 1.8V supply. The simulation results show the SNDR and SFDR of 59.45dB and 68.69dB, respectively, and the power consumption of 35.04mW is achieved.
The conventional three-level inverter has been proposed to act as a recuperating converter in Traction Supply Substation. This converter is mainly used to feed back the regenerative braking energy to the grid. However, passive filter is desired to mitigate the current and voltage harmonics. Therefore, this paper investigates the possibility to use a seven-level Cascaded H-Bridge (CHB) converter as the recuperating converter without additional filtering. The proposed converter is modeled with MATLAB/Simulink simulation software. It is then simulated with two potential modulation schemes, namely Phase-Shifted PWM (PS-PWM) and Phase-Disposition PWM (PD-PWM). The quality of AC waveforms produced by these two modulation methods is compared and studied. The results show that PS-PWM technique is preferable for this application as it offered a clean AC current waveform with less than 5% harmonic distortion. However, a twenty-one-level CHB was predicted to comply with the 8% voltage harmonic requirement.
IJERA (International journal of Engineering Research and Applications) is International online, ... peer reviewed journal. For more detail or submit your article, please visit www.ijera.com
Compact low power high slew-rate cmos buffer amplifier with power gating tech...VLSICS Design
A qualitative analysis of different parameters such as Phase noise, Slew rate and tranconductance by using
power gating reduction technique is presented. The circuit achieves the large driving capability by
employing simple comparators to sense the transients of the input to turn on the output stages, which are
statically off in the stable state. The effect of the different number of transistors and their topologies on the
phase noise and Slew rate is analyzed. Good agreement between qualitative and quantitative measurements
is observed. Scope of reducing of Noise and avoidance of Leakage due to various sources is discussed.
Optimal Body Biasing Technique for CMOS Tapered Buffer IJEEE
This paper represents Fixed Body Biased CMOS Tapered Buffer which is designed to minimize the average power dissipation across large capacitive load. The implementation of Reverse Body Bias (RBB) in the proposed Buffer chain is to vary Vth value of NMOS in the first stage. And with the increase in Vth /sub-threshold leakage current and power has been reduced. The technology constraints on the threshold voltage does not allow designer to set high threshold voltage for MOS devices. Hence, this was found that in proposed circuit that when optimal Reverse Body Bias value is set within (0.2 VDD to 0.4 VDD) range, the average power dissipation across capacitive load reduces to 82.2 % at very less penalty in delay. Thus CMOS buffer designers can use the proposed method to vary Vth while keeping VDD constant, which could improve the performance parameters of Tapered Buffer. The proposed analysis is verified by simulating the 3-stage tapered buffer schematics using standard 180nm CMOS technology in Cadence environment.
SIMULTANEOUS OPTIMIZATION OF STANDBY AND ACTIVE ENERGY FOR SUB-THRESHOLD CIRC...VLSICS Design
Increased downscaling of CMOS circuits with respect to feature size and threshold voltage has a result of
dramatically increasing in leakage current. So, leakage power reduction is an important design issue for
active and standby modes as long as the technology scaling increased. In this paper, a simultaneous active
and standby energy optimization methodology is proposed for 22 nm sub-threshold CMOS circuits. In the
first phase, we investigate the dual threshold voltage design for active energy per cycle minimization. A
slack based genetic algorithm is proposed to find the optimal reverse body bias assignment to set of noncritical
paths gates to ensure low active energy per cycle with the maximum allowable frequency at the
optimal supply voltage. The second phase, determine the optimal reverse body bias that can be applied to
all gates for standby power optimization at the optimal supply voltage determined from the first phase.
Therefore, there exist two sets of gates and two reverse body bias values for each set. The reverse body bias
is switched between these two values in response to the mode of operation. Experimental results are
obtained for some ISCAS-85 benchmark circuits such as 74L85, 74283, ALU74181, and 16 bit RCA. The
optimized circuits show significant energy saving ranged (from 14.5% to 42.28%) and standby power
saving ranged (from 62.8% to 67%).
SIMULTANEOUS OPTIMIZATION OF STANDBY AND ACTIVE ENERGY FOR SUB-THRESHOLD CIRC...VLSICS Design
Increased downscaling of CMOS circuits with respect to feature size and threshold voltage has a result of dramatically increasing in leakage current. So, leakage power eduction is an important design issue for active and standby modes as long as the technology scaling increased. In this paper, a simultaneous active and standbyrgy optimization methodology is proposed for 22 nm sub-threshold CMOS circuits. In thefirst phase, we investigate the dual threshold voltage design for active energy per cycle minimization. A slack based genetic algorithm is proposed to find the optimal reverse body bias assignment to set of noncritical paths gates to ensure low active energy per cycle with the maximum allowable frequency at the optimal supply voltage. The second phase, determine the optimal reverse body bias that can be applied to
all gates for standby power optimization at the optimal supply voltage determined from the first phase. Therefore, there exist two sets of gates and two reverse body bias values for each set. The reverse body bias is switched between these two values in response to the mode of operation. Experimental results are obtained for some ISCAS-85 benchmark circuits such as 74L85, 74283, ALU74181, and 16 bit RCA. The optimized circuits show significant energy saving ranged (from 14.5% to 42.28%) and standby power saving ranged (from 62.8% to 67%).
SIMULTANEOUS OPTIMIZATION OF STANDBY AND ACTIVE ENERGY FOR SUB-THRESHOLD CIRC...VLSICS Design
Increased downscaling of CMOS circuits with respect to feature size and threshold voltage has a result of
dramatically increasing in leakage current. So, leakage power reduction is an important design issue for
active and standby modes as long as the technology scaling increased. In this paper, a simultaneous active
and standby energy optimization methodology is proposed for 22 nm sub-threshold CMOS circuits. In the
first phase, we investigate the dual threshold voltage design for active energy per cycle minimization. A
slack based genetic algorithm is proposed to find the optimal reverse body bias assignment to set of noncritical paths gates to ensure low active energy per cycle with the maximum allowable frequency at the
optimal supply voltage. The second phase, determine the optimal reverse body bias that can be applied to
all gates for standby power optimization at the optimal supply voltage determined from the first phase.
Therefore, there exist two sets of gates and two reverse body bias values for each set. The reverse body bias
is switched between these two values in response to the mode of operation. Experimental results are
obtained for some ISCAS-85 benchmark circuits such as 74L85, 74283, ALU74181, and 16 bit RCA. The
optimized circuits show significant energy saving ranged (from 14.5% to 42.28%) and standby power
saving ranged (from 62.8% to 67%).
Adiabatic Logic Based Low Power Carry Select Adder for future TechnologiesIJMER
International Journal of Modern Engineering Research (IJMER) is Peer reviewed, online Journal. It serves as an international archival forum of scholarly research related to engineering and science education.
Design of a high frequency low voltage CMOS operational amplifierVLSICS Design
A method is presented in this paper for the design of a high frequency CMOS operational amplifier (OpAmp) which operates at 3V power supply using tsmc 0.18 micron CMOS technology. The OPAMP designed is a two-stage CMOS OPAMP followed by an output buffer. This Operational Transconductance Amplifier (OTA) employs a Miller capacitor and is compensated with a current buffer compensation technique. The unique behaviour of the MOS transistors in saturation region not only allows a designer to work at a low voltage, but also at a high frequency. Designing of two-stage op-amps is a multi-dimensional-optimization problem where optimization of one or more parameters may easily result into degradation of others. The OPAMP is designed to exhibit a unity gain frequency of 2.02GHz and exhibits a gain of 49.02dB with a 60.50 phase margin. As compared to the conventional approach, the proposed compensation method results in a higher unity gain frequency under the same load condition. Design has been carried out in Tanner tools. Simulation results are verified using S-edit and W-edit.
Low Power and Fast Transient High Swing CMOS Telescopic Operational AmplifierIJERA Editor
CMOS telescopic operational amplifier with high-swing and high-performance is described in this paper. The
swing is attained by using the tail and current source-transistors in deep-linear region. The resultant deprivation
in parameters like differential gain, CMRR and added characteristics are recompensed by using regulatedcascode
differential gain enhancement and a replica-tail feedback technique. Operating at power supply of 3.3V,
the power consumption, slew rate and settling time are improved using transmission controlled pass circuitry
and level amplifier. It is shown through simulations that the Op-Amp preserves its high CMRR and unity gain
frequency.
DESIGN & ANALYSIS OF A CHARGE RE-CYCLE BASED NOVEL LPHS ADIABATIC LOGIC CIRCU...VLSICS Design
This paper focuses on principles of adiabatic logic, its classification and comparison of various adiabatic logic designs. An attempt has been made in this paper to modify 2PASCL (Two Phase Adiabatic Static CMOS Logic) adiabatic logic circuit to minimize delay of the different 2PASCL circuit designs. This modifications in the circuits leads to improvement of Power Delay Product (PDP) which is one of the figure of merit to optimize the circuit with factors like power dissipation and delay of the circuit. This paper investigates the design approaches of low power adiabatic gates in terms of energy dissipation and uses of Simple PN diode instead of MOS diode which reduces the effect of Capacitances at high transition and power clock frequency. A computer simulation using SPECTRE from Cadence is carried out on different adiabatic circuits, such as Inverter, NAND, NOR, XOR and 2:1 MUX.
ANALYSIS OF SMALL-SIGNAL PARAMETERS OF 2-D MODFET WITH POLARIZATION EFFECTS F...VLSICS Design
An improved analytical two dimensional (2-D) model for AlGaN/GaN modulation doped field effect
transistor (MODFET) has been developed. The model is based on the solution of 2-D Poisson’s equation.
The model includes the spontaneous and piezoelectric polarization effects. The effects of field dependent
mobility, velocity saturation and parasitic resistances are included in the current voltage characteristics of
the developed two dimensional electron gas (2-DEG) model. The small-signal microwave parameters have
been evaluated to determine the output characteristics, device transconductance and cut-off frequency for
50 nm gate length. The peak transconductance of 165mS/mm and a cut-off frequency of 120 GHz have been
obtained. The results so obtained are in close agreement with experimental data, thereby proving the
validity of the model.
SIMULTANEOUS OPTIMIZATION OF STANDBY AND ACTIVE ENERGY FOR SUB-THRESHOLD CIRC...VLSICS Design
Increased downscaling of CMOS circuits with respect to feature size and threshold voltage has a result of dramatically increasing in leakage current. So, leakage power reduction is an important design issue for active and standby modes as long as the technology scaling increased. In this paper, a simultaneous active and standby energy optimization methodology is proposed for 22 nm sub-threshold CMOS circuits. In the first phase, we investigate the dual threshold voltage design for active energy per cycle minimization. A
slack based genetic algorithm is proposed to find the optimal reverse body bias assignment to set of noncritical
paths gates to ensure low active energy per cycle with the maximum allowable frequency at the optimal supply voltage. The second phase, determine the optimal reverse body bias that can be applied to all gates for standby power optimization at the optimal supply voltage determined from the first phase.
Therefore, there exist two sets of gates and two reverse body bias values for each set. The reverse body bias is switched between these two values in response to the mode of operation. Experimental results are obtained for some ISCAS-85 benchmark circuits such as 74L85, 74283, ALU74181, and 16 bit RCA. The optimized circuits show significant energy saving ranged (from 14.5% to 42.28%) and standby power
saving ranged (from 62.8% to 67%)
A 10-bit, 200MS/s CMOS Pipeline ADC using new shared opamp architecture VLSICS Design
A 10 bit opamp-sharing pipeline analog-to-digital converter (ADC) using a novel mirror telescopic operational amplifiers (opamp) with dual nmos differential inputs is presented. Reduction of power and area is achieved by completely merging the front-end sample-and-hold amplifier (SHA) into the first multiplying digital-to-analog converter (MDAC) using the proposed opamp. Transistors in the opamp are always biased in saturation to avoid increase of settling time due to opamp turn-on delays. The design targets 0.18um CMOS process for operation, at 200MS/s from a 1.8V supply. The simulation results show the SNDR and SFDR of 59.45dB and 68.69dB, respectively, and the power consumption of 35.04mW is achieved.
The conventional three-level inverter has been proposed to act as a recuperating converter in Traction Supply Substation. This converter is mainly used to feed back the regenerative braking energy to the grid. However, passive filter is desired to mitigate the current and voltage harmonics. Therefore, this paper investigates the possibility to use a seven-level Cascaded H-Bridge (CHB) converter as the recuperating converter without additional filtering. The proposed converter is modeled with MATLAB/Simulink simulation software. It is then simulated with two potential modulation schemes, namely Phase-Shifted PWM (PS-PWM) and Phase-Disposition PWM (PD-PWM). The quality of AC waveforms produced by these two modulation methods is compared and studied. The results show that PS-PWM technique is preferable for this application as it offered a clean AC current waveform with less than 5% harmonic distortion. However, a twenty-one-level CHB was predicted to comply with the 8% voltage harmonic requirement.
IJERA (International journal of Engineering Research and Applications) is International online, ... peer reviewed journal. For more detail or submit your article, please visit www.ijera.com
Compact low power high slew-rate cmos buffer amplifier with power gating tech...VLSICS Design
A qualitative analysis of different parameters such as Phase noise, Slew rate and tranconductance by using
power gating reduction technique is presented. The circuit achieves the large driving capability by
employing simple comparators to sense the transients of the input to turn on the output stages, which are
statically off in the stable state. The effect of the different number of transistors and their topologies on the
phase noise and Slew rate is analyzed. Good agreement between qualitative and quantitative measurements
is observed. Scope of reducing of Noise and avoidance of Leakage due to various sources is discussed.
Optimal Body Biasing Technique for CMOS Tapered Buffer IJEEE
This paper represents Fixed Body Biased CMOS Tapered Buffer which is designed to minimize the average power dissipation across large capacitive load. The implementation of Reverse Body Bias (RBB) in the proposed Buffer chain is to vary Vth value of NMOS in the first stage. And with the increase in Vth /sub-threshold leakage current and power has been reduced. The technology constraints on the threshold voltage does not allow designer to set high threshold voltage for MOS devices. Hence, this was found that in proposed circuit that when optimal Reverse Body Bias value is set within (0.2 VDD to 0.4 VDD) range, the average power dissipation across capacitive load reduces to 82.2 % at very less penalty in delay. Thus CMOS buffer designers can use the proposed method to vary Vth while keeping VDD constant, which could improve the performance parameters of Tapered Buffer. The proposed analysis is verified by simulating the 3-stage tapered buffer schematics using standard 180nm CMOS technology in Cadence environment.
SIMULTANEOUS OPTIMIZATION OF STANDBY AND ACTIVE ENERGY FOR SUB-THRESHOLD CIRC...VLSICS Design
Increased downscaling of CMOS circuits with respect to feature size and threshold voltage has a result of
dramatically increasing in leakage current. So, leakage power reduction is an important design issue for
active and standby modes as long as the technology scaling increased. In this paper, a simultaneous active
and standby energy optimization methodology is proposed for 22 nm sub-threshold CMOS circuits. In the
first phase, we investigate the dual threshold voltage design for active energy per cycle minimization. A
slack based genetic algorithm is proposed to find the optimal reverse body bias assignment to set of noncritical
paths gates to ensure low active energy per cycle with the maximum allowable frequency at the
optimal supply voltage. The second phase, determine the optimal reverse body bias that can be applied to
all gates for standby power optimization at the optimal supply voltage determined from the first phase.
Therefore, there exist two sets of gates and two reverse body bias values for each set. The reverse body bias
is switched between these two values in response to the mode of operation. Experimental results are
obtained for some ISCAS-85 benchmark circuits such as 74L85, 74283, ALU74181, and 16 bit RCA. The
optimized circuits show significant energy saving ranged (from 14.5% to 42.28%) and standby power
saving ranged (from 62.8% to 67%).
SIMULTANEOUS OPTIMIZATION OF STANDBY AND ACTIVE ENERGY FOR SUB-THRESHOLD CIRC...VLSICS Design
Increased downscaling of CMOS circuits with respect to feature size and threshold voltage has a result of dramatically increasing in leakage current. So, leakage power eduction is an important design issue for active and standby modes as long as the technology scaling increased. In this paper, a simultaneous active and standbyrgy optimization methodology is proposed for 22 nm sub-threshold CMOS circuits. In thefirst phase, we investigate the dual threshold voltage design for active energy per cycle minimization. A slack based genetic algorithm is proposed to find the optimal reverse body bias assignment to set of noncritical paths gates to ensure low active energy per cycle with the maximum allowable frequency at the optimal supply voltage. The second phase, determine the optimal reverse body bias that can be applied to
all gates for standby power optimization at the optimal supply voltage determined from the first phase. Therefore, there exist two sets of gates and two reverse body bias values for each set. The reverse body bias is switched between these two values in response to the mode of operation. Experimental results are obtained for some ISCAS-85 benchmark circuits such as 74L85, 74283, ALU74181, and 16 bit RCA. The optimized circuits show significant energy saving ranged (from 14.5% to 42.28%) and standby power saving ranged (from 62.8% to 67%).
SIMULTANEOUS OPTIMIZATION OF STANDBY AND ACTIVE ENERGY FOR SUB-THRESHOLD CIRC...VLSICS Design
Increased downscaling of CMOS circuits with respect to feature size and threshold voltage has a result of
dramatically increasing in leakage current. So, leakage power reduction is an important design issue for
active and standby modes as long as the technology scaling increased. In this paper, a simultaneous active
and standby energy optimization methodology is proposed for 22 nm sub-threshold CMOS circuits. In the
first phase, we investigate the dual threshold voltage design for active energy per cycle minimization. A
slack based genetic algorithm is proposed to find the optimal reverse body bias assignment to set of noncritical paths gates to ensure low active energy per cycle with the maximum allowable frequency at the
optimal supply voltage. The second phase, determine the optimal reverse body bias that can be applied to
all gates for standby power optimization at the optimal supply voltage determined from the first phase.
Therefore, there exist two sets of gates and two reverse body bias values for each set. The reverse body bias
is switched between these two values in response to the mode of operation. Experimental results are
obtained for some ISCAS-85 benchmark circuits such as 74L85, 74283, ALU74181, and 16 bit RCA. The
optimized circuits show significant energy saving ranged (from 14.5% to 42.28%) and standby power
saving ranged (from 62.8% to 67%).
Adiabatic Logic Based Low Power Carry Select Adder for future TechnologiesIJMER
International Journal of Modern Engineering Research (IJMER) is Peer reviewed, online Journal. It serves as an international archival forum of scholarly research related to engineering and science education.
Design of a high frequency low voltage CMOS operational amplifierVLSICS Design
A method is presented in this paper for the design of a high frequency CMOS operational amplifier (OpAmp) which operates at 3V power supply using tsmc 0.18 micron CMOS technology. The OPAMP designed is a two-stage CMOS OPAMP followed by an output buffer. This Operational Transconductance Amplifier (OTA) employs a Miller capacitor and is compensated with a current buffer compensation technique. The unique behaviour of the MOS transistors in saturation region not only allows a designer to work at a low voltage, but also at a high frequency. Designing of two-stage op-amps is a multi-dimensional-optimization problem where optimization of one or more parameters may easily result into degradation of others. The OPAMP is designed to exhibit a unity gain frequency of 2.02GHz and exhibits a gain of 49.02dB with a 60.50 phase margin. As compared to the conventional approach, the proposed compensation method results in a higher unity gain frequency under the same load condition. Design has been carried out in Tanner tools. Simulation results are verified using S-edit and W-edit.
A Simulation Based Analysis of Lowering Dynamic Power in a CMOS Inverteridescitation
With the increase in demand of high fidelity
portable devices, there is more and more emphasis laying
down on the development of low power and high performance
systems. In the next generation processors, the low power
design has to be incorporated into fundamental computation
units, such as adder. CMOS circuit design plays a crucial role
in designing of these computation units (like adder and
multiplier) so if there is any optimal way to reduce the power
dissipation in CMOS circuits then it will directly lower down
the power dissipation of other circuits and logic gates as well.
In this paper we have studied and analyzed different
techniques to reduce the dynamic power of CMOS circuit
with the help of performing simulation on some significant
factors (i.e device characteristics) of respective circuitry
designs by using Cadence-Virtuoso tool.
IJRET : International Journal of Research in Engineering and Technology is an international peer reviewed, online journal published by eSAT Publishing House for the enhancement of research in various disciplines of Engineering and Technology. The aim and scope of the journal is to provide an academic medium and an important reference for the advancement and dissemination of research results that support high-level learning, teaching and research in the fields of Engineering and Technology. We bring together Scientists, Academician, Field Engineers, Scholars and Students of related fields of Engineering and Technology.
FORCED STACK SLEEP TRANSISTOR (FORTRAN): A NEW LEAKAGE CURRENT REDUCTION APPR...VIT-AP University
Reduction in leakage current has become a significant concern in nanotechnology-based low-power, low-voltage, and high-performance VLSI applications. This research article discusses a new low-power circuit design the approach of FORTRAN (FORced stack sleep TRANsistor), which decreases the leakage power efficiency in the CMOS-based circuit outline in VLSI domain. FORTRAN approach reduces leakage current in both active as well as standby modes of operation. Furthermore, it is not time intensive when the circuit goes from active mode to standby mode and vice-versa. To validate the proposed design approach, experiments are conducted in the Tanner EDA tool of mentor graphics bundle on projected circuit designs for the full adder, a chain of 4-inverters, and 4-bit multiplier designs utilizing 180nm, 130nm, and 90nm TSMC technology node. The outcomes obtained show the result of a 95-98% vital reduction in leakage power as well as a 15-20% reduction in dynamic power with a minor increase in delay. The result outcomes are compared for accuracy with the notable design approaches that are accessible for both active and standby modes of operation.
Design of ultra low power 8 channel analog multiplexer using dynamic threshol...VLSICS Design
The design of an ultra low voltage, low power high
speed 8 channel Analog multiplexer in 180nm CMOS
technology is presented. A modified transmission ga
te using a dynamic threshold voltage MOSFET
(DTMOS
)
is employed in the design. The design is optimized
with respect to critical requirements like short
switching time, low power dissipation, good lineari
ty and high dynamic range with an operating voltage
of
0.4V. The ON and OFF resistances achieved are 32 oh
ms and 10Mohms respectively with a switching
speed of 10MHz. The power dissipation obtained is a
round 2.65uW for a dynamic range of 1uV to 0.4V.
A Sub Threshold Source Coupled Logic Based Design of Low Power CMOS Analog Mu...VLSICS Design
A novel approach for designing Ultra Low Power and wide dynamic range circuit for multiplexing analog
signals is presented. The design operates in weak inversion (Sub threshold) region and uses Source -
Coupled Logic ( SCL) circuit. The bias current of the SCL gates is varied to scale down linearly the power
consumption and the operating frequency. The multiplexer design employs CMOS transistors as
transmission gate with dynamic threshold voltage. The design exhibits low power dissipation, high
dynamic range and good linearity. The design was implemented in 180 nm technology and was operated at
a supply voltage of 400 mV with a bias current ranging in the order of few Pico-amperes. The ON and
OFF resistance of the transmission gate achieved were 27 ohms and 10 M ohms respectively. The power
dissipation achieved is around 0.79 μW for a dynamic range of 1μV to 0.4 V.
AN OPERATIONAL AMPLIFIER WITH RECYCLING FOLDED CASCODE TOPOLOGY AND ADAPTIVE ...VLSICS Design
This paper presents a highly adaptive operational amplifier with high gain, high bandwidth, high speed and low power consumption. By adopting the recycling folded cascode topology along with an adaptivebiasing circuit, this design achieves high performance in terms of gain-bandwidth product (GBW) and slew rate (SR). This single stage op-amp has been designed in 0.18µm technology with a power supply of 1.8V and a 5pF load. The simulation results show that the amplifier achieved a GBW of 335.5MHz, Unity Gain Bandwidth of 247.1MHz and a slew rate of 92.8V/µs.
Sub-Threshold Leakage Current Reduction Techniques In VLSI Circuits -A SurveyIJERA Editor
There is an increasing demand for portable devices powered up by battery, this led the manufacturers of
semiconductor technology to scale down the feature size which results in reduction in threshold voltage and
enables the complex functionality on a single chip. By scaling down the feature size the dynamic power
dissipation has no effect but the static power dissipation has become equal or more than that of Dynamic power
dissipation. So in recent CMOS technologies static power dissipation i.e. power dissipation due to leakage
current has become a challenging area for VLSI chip designers. In order to prolong the battery life and maintain
reliability of circuit, leakage current reduction is the primary goal. A basic overview of techniques used for
reduction of sub-threshold leakages is discussed in this paper. Based on the surveyed techniques, one would be
able to choose required and apt leakage reduction technique.
International Journal of Engineering Research and DevelopmentIJERD Editor
Electrical, Electronics and Computer Engineering,
Information Engineering and Technology,
Mechanical, Industrial and Manufacturing Engineering,
Automation and Mechatronics Engineering,
Material and Chemical Engineering,
Civil and Architecture Engineering,
Biotechnology and Bio Engineering,
Environmental Engineering,
Petroleum and Mining Engineering,
Marine and Agriculture engineering,
Aerospace Engineering.
International Journal of Engineering Research and Applications (IJERA) is an open access online peer reviewed international journal that publishes research and review articles in the fields of Computer Science, Neural Networks, Electrical Engineering, Software Engineering, Information Technology, Mechanical Engineering, Chemical Engineering, Plastic Engineering, Food Technology, Textile Engineering, Nano Technology & science, Power Electronics, Electronics & Communication Engineering, Computational mathematics, Image processing, Civil Engineering, Structural Engineering, Environmental Engineering, VLSI Testing & Low Power VLSI Design etc.
The DC-fault Blocking Capability by a New Hybrid Multilevel Converter in HVDC...Editor IJCATR
This paper explains the working principles, supported by simulation results, of a new converter topology in-tended for HVDC
application, called the Alternate Arm Con-verter (AAC). Modular Multilevel Converters deliver small footprints and efficiencies above
99% in their half-bridge format, but only deliver DC-fault blocking with full-bridge sub-modules, and with an unacceptable penalty in
efficiency. The Alternate Arm Converter (AAC) is a hybrid circuit topology using a mixture of full-bridge sub-modules and director
switches which is capable of current control through DC faults while maintaining good efficiency in normal operation. It is hybrid
between the modular multi-level converter, because of the presence of H-bridge cells, and the 2-level converter, in the form of director
switches in each arm. This converter is able to generate a multi-level AC voltage and, since its stacks of cells consist of H-bridge cells
instead of half-bridge cells, they are able to generate higher AC voltage than the DC terminal voltage. This allows the AAC to operate
at an optimal point, called the “sweet spot”, where the AC and DC energy flows equal. The director switches in the AAC are responsible
for alternating the conduction period of each arm, leading to a significant reduction in the number of cells in the stacks. Furthermore,
the AAC can keep control of the current in the phase reactor even in case of a DC-side fault and support the AC grid, through a
STATCOM mode. Simulation results and loss calculations are presented in this paper in order to support the claimed features of the
AAC
Design a Low Power High Speed Full Adder Using AVL Technique Based on CMOS Na...IOSR Journals
Abstract: Power and delay optimization is a very crucial issue in low voltage applications. In this paper, we present a design of Full Adder circuit using AVL techniques for low power operation. The approach for the design is based on XOR/XNOR & Transmission gate for single bit as hybrid design .By using this approach Full Adder is being designed using 12 transistors. We can reduce the value of total power dissipation by applying the AVLG (adaptive voltage level at ground) technology in which the ground potential is raised and AVLS (adaptive voltage level at supply) in which supply potential is increased. The main aim of the design is to investigate the power, Propagation Delay and Power delay Product for low voltage Full Adder for the proposed design style. The simulation results show that there is a significant reduction in power consumption for this proposed cell with the AVL technique. The circuit is designed using 65 nanometer CMOS technology and simulated using MicroWind and DSCH Ver. 3.1 Keywords: Full Adder, AVL Techniques, Low Power, VLSI, High Performance
Design of Memory Cell for Low Power ApplicationsIJERA Editor
Aggressive CMOS scaling results in lower threshold voltage and thin oxide thickness for transistors manufactured in nano regime. As a result, reducing the sub-threshold and tunneling gate leakage currents has become crucial in the design of ICs. This paper presents a new method to reduce the total leakage power dissipation of static random access memories (SRAMs) while maintaining their performance.
Elevating Tactical DDD Patterns Through Object CalisthenicsDorra BARTAGUIZ
After immersing yourself in the blue book and its red counterpart, attending DDD-focused conferences, and applying tactical patterns, you're left with a crucial question: How do I ensure my design is effective? Tactical patterns within Domain-Driven Design (DDD) serve as guiding principles for creating clear and manageable domain models. However, achieving success with these patterns requires additional guidance. Interestingly, we've observed that a set of constraints initially designed for training purposes remarkably aligns with effective pattern implementation, offering a more ‘mechanical’ approach. Let's explore together how Object Calisthenics can elevate the design of your tactical DDD patterns, offering concrete help for those venturing into DDD for the first time!
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See how to accelerate model training and optimize model performance with active learning
Learn about the latest enhancements to out-of-the-box document processing – with little to no training required
Get an exclusive demo of the new family of UiPath LLMs – GenAI models specialized for processing different types of documents and messages
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Length: 30 minutes
Session Overview
-------------------------------------------
During this webinar, we will cover the following topics while demonstrating the integrations of JMeter, InfluxDB and Grafana:
- What out-of-the-box solutions are available for real-time monitoring JMeter tests?
- What are the benefits of integrating InfluxDB and Grafana into the load testing stack?
- Which features are provided by Grafana?
- Demonstration of InfluxDB and Grafana using a practice web application
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https://www.rttsweb.com/jmeter-integration-webinar
JMeter webinar - integration with InfluxDB and Grafana
A RAIL-TO-RAIL HIGH SPEED CLASS-AB CMOS BUFFER WITH LOW POWER AND ENHANCED SLEW RATE
1. International Journal of VLSI design & Communication Systems (VLSICS) Vol.4, No.3, June 2013
DOI : 10.5121/vlsic.2013.4308 79
A RAIL-TO-RAIL HIGH SPEED CLASS-AB CMOS
BUFFER WITH LOW POWER AND ENHANCED
SLEW RATE
Sadhana Sharma1
, Abhay Vidyarthi2
and Shyam Akashe3
1
Research Scholar of ITM University, Gwalior, India
sadhanasharma2oct@gmail.com
2
Associate Professor, Dept. of ECE, ITM University, Gwalior, India
vidyarthi.abhay@gmail.com
3
Associate Professor, Dept. of ECE, ITM University, Gwalior, India
shyam.akashe@yahoo.com
ABSTRACT
A rail-to-rail class-AB CMOS buffer is proposed in this paper to drive large capacitive loads. A new
technique is used to reduce the leakage power of class-AB CMOS buffer circuits without affecting dynamic
power dissipation .The name of applied technique is LECTOR, which gives the high speed buffer with the
reduced low power dissipation (1.05%) and reduced area (2.8%). The proposed buffer is simulated at
45nm CMOS technology and the circuit is operated at 3V supply with cadence software. This analog circuit
is performed with extremely low leakage current as well as high current driving capability for the large
input voltages. The proposed paper is achieved very high speed with very low propagation delay range
i.e.(292×10-12). So the delay of the circuit is reduced to 10%. The settling time of this circuit is reduced by
24% (in ns) at 3V square wave input. The measured quiescent current is 41µA.
KEYWORDS
CMOS buffer, Class-AB, Rail-to-rail, Quiescent current, Lector technique.
1. INTRODUCTION
In the electronics industries CMOS based integrated circuits are used at very large scale .Today
CMOS technology has been scaled down to nanometer region. The demand of CMOS transistors
is increasing day by day for high speed, low cost and the low power consumption. In the CMOS
technology, large capacitive loads are used many times. Buffer circuits are mostly used to run the
large capacitive load at high speed. Here rail to rail class-AB CMOS buffer is presented to drive
the large capacitive loads. Presented paper has the enhanced slew rate with the low power
dissipation. This paper is based on the new leakage current technique i.e. LECTOR [1]. The
tapered buffer has been presented to get the high speed that contains the capacitive load with 5v
supply [2]. Here tapered buffer is fixed between the logic/registers and large capacitive loads.
A low dropout linear regulator (LDOs) is also designed which dissipates the low static power and
the transient response of this circuit is also good without transient overshoot when driving large
2. International Journal of VLSI design & Communication Systems (VLSICS) Vol.4, No.3, June 2013
80
capacitive loads [3].This paper was realized by a new current efficient analog driver for CMOS
LDO. To improve the transient response, the concept of the LDO with the current boosting buffer
was presented [4] , [5].In [6] A high driving capability CMOS buffer amplifier for TFT-LCD
source drivers is performed which contains a pair of auxiliary driving transistors. It contains the
comparators with the basic differential amplifiers to reduce the power dissipation.
A compact low-power rail-to-rail buffer is performed for large size LCD applications .It performs
the high slew rate by applying the push- pull output buffer with two complementary type input
amplifiers give a dual-path push-pull operation of the output buffer. An auxiliary biasing network
is used to control the output quiescent current without increase the power dissipation [7]-[9].The
new circuit technique is proposed to get a rail-to-rail CMOS analogue buffer with class-AB
function which gives an approach with low power dissipation and high driving capability. The
basic fundamental of this paper is based on the [10]. The operation of this circuit depends upon
the transconductance amplifier connected in negative feedback as shown in figure 1(a) and
(b).This scheme is used to driving capability.
The analog buffer is implemented by the transconductance amplifier gm with negative feedback.
In Fig.1 (a), consists the ro and CL represent the output resistance of the gm circuit and the load
capacitor, respectively. Fig.(b) contains the settling time which is exist between to and ts ,so the
gm circuit should be able to consist the high output current driving capability to quickly charge
(or discharge). When settling time to ≤ t ≥ ts, then output voltage Vo should follow the input
voltage Vin. Now to reduce the power consumption , to drive the large capacitive load, to reduce
the leakage current and to further reduce the settling time the Lector technique is performed.
This technique reduces the settling time by reducing the propagation delay. The paper consist an
adaptive circuit which has four simple current mirrors and the pair of leakage control transistors,
forming an attractive circuit for- low power applications. The basic idea of this paper begins from
the next section, Conditions for rail- to- rail input swing is given in the next section. Section 3
consists the low power dissipation scheme for the buffer circuit Section 4 explains the new high
speed buffer with low power. Section 5 is giving the simulation results of the circuit. And Section
6 is giving the conclusion of the proposed paper. .
Vin
V
to ts
Vin
Vout
t
( b)
Fig.1 (a) Transconductance amplifier-based voltage follower and (b) Output
settling time with slewing.
Vout
ro CL
(a)
gm
+
-
3. International Journal of VLSI design & Communication Systems (VLSICS) Vol.4, No.3, June 2013
81
2. CLASS-AB RAIL-TO-RAIL BUFFER
Class-AB rail-to-rail buffer contains some common features are explained in the following sub-
sections.
2.1 Rail-to-Rail input swing
To achieve the rail-to-rail swing, an NMOS pair and an PMOS pair added in parallel
configuration [11].The CMR voltage range of the n-channel pair is written as;
ܸ ≥ ܸ௦௦ + ܸ௦ + ܸௗ௦ (1)
Where ܸ௦ and ܸௗ௦ are the gate-source voltage and drain-source voltage respectively. Similarly,
the CMR of p-channel pair is written as;
ܸ ≤ ܸௗௗ + ܸ௦ + ܸௗ௦ (2)
To get rail-to-rail input range, one or both pair should be in “active mode”, which requires
ܸି௫ ≥ ܸି (3)
Put the equation (1) and (2) in equation (3)
ܸௗௗ − ܸ௦௦ ≥ ܸ௦ + ܸௗ௦ + ܸ௦ + ܸௗ௦ ≥ 2ܸ௧ (4)
Here equation (4) shows that ܸ௧ of NMOS and PMOS are same, and then the value of applied
voltage should be higher than twice of the threshold voltage ܸ௧ of the applied technology.
2.2 Class-AB Buffer
Class-AB buffer is mostly used to reduce the tradeoff between speed characteristics and power
dissipation. The function of class-AB buffer is also called the adaptive biasing [12]. Adaptive
biasing is useful to improve the slew rate performance. To achieve this phenomenon we need
high quiescent current so, that power -consumption will also increase. To remove this
contradiction Lector technique is applied.
In class-AB operation, each device operates the same way as in class-B over half the waveform,
but on the same side it also conducts a small amount on the other half. As per result the region
where both devices simultaneously are nearly off (the dead zone) is reduced. According to the
result when the waveform from the two devices are combined, the crossover greatly minimized or
eliminated altogether .The exact choice of quiescent current, the standing current across both
devices when there is no signal, then it make a large difference at the level of distortion (and to
the risk of thermal run away, that may damage the devices) often the bias voltage applied to set
this quiescent current has to be adjusted with the temperature of the output transistor.
4. International Journal of VLSI design & Communication Systems (VLSICS) Vol.4, No.3, June 2013
82
2.3 Power dissipation of circuit
The maximum power allowed to dissipate in a circuit is defined as,
Pୢ =
൫ౠౙౣ౮ି൯
ౠ
(5)
Where Pୢ is the power dissipation, T୨ୡ୫ୟ୶ is the maximum junction temperature [13]. Tୟ is
ambient temperature. Ɵja is the thermal resistance; depends on parameters such as die size,
package size and package material. The smaller will be the die size and package, the higher θ୨ୟ is
becomes then the power dissipation will be reduced .Total power dissipation in a device can be
calculated as
Pୢ = P୯ + P୭ (6)
Pୢ is the quiescent power dissipated in a circuit with no load connected at the output. P୭ is the
power dissipated in the circuit with a load connected at the output, this power cannot be
dissipated by the load.
Pୢ = supply current × total supply voltage with no load.
P୭ =output current × voltage difference between supply voltage and output voltage of
the same supply.
2. PROPOSED LOW POWER DISSIPATION SCHEME FOR CMOS BUFFER
We have seen that the buffer’s circuit affected by the power dissipation. The power dissipation is
an important consideration in the CMOS VLSI design circuits. High power consumption leads to
reduction in the battery life-, in the case of battery-powers applications and in reliability,
packaging and cooling costs. The main sources of power dissipation are: (a) capacitive power
dissipation. (b) Short circuit currents. (c) Leakage currents. In CMOS technology leakage power
occurs due to the sub-threshold; which is the reverse current flowing through the off transistor.
The feature size and the channel length of transistor are reducing day by day, because the
technology is also scaled down. Due to decrement in the channel length we get the increment of
the leakage power in the total dissipated power.
To minimize the increment of the leakage current we are applying the LECTOR technique, which
is based on the leakage control transistor. LECTOR technique is based on the stacking of
transistor, which is existing between supply voltage and ground. LECTOR provides two leakage
control transistors, a P-type and an N-type. In this technique PMOS is added with pull up network
and an NMOS is added with the pull down network. Here the gate terminal of each leakage
control transistor (LCT) is connected with the other, where one of the LCTs is always exist in the
cutoff region of operation, by help of this phenomenon an additional resistance is provided which
decreases the sub-threshold leakage current.
Fig. (2) Shows the leakage current of the buffer circuit which is achieved after the simulation of
the circuit at cadence software. By help of this technique we have achieved the reduced leakage
current i.e.118.4µa and the propagation delay is reduced to picorange i.e.292.1×10-12.The graph
between the supply voltage and achieved leakage power is shown in fig. (3).
5. International Journal of VLSI design & Communication Systems (VLSICS) Vol.4, No.3, June 2013
83
Fig. (2) Shows the simulated leakage current of the circuit.
Fig.(3) shows the achieved leakage power with supply voltage.
0
10
20
30
40
50
60
70
3v 2.5 2v 1.5v
LEAKAGE POWER(μw)
supply voltage
Leakagepower(μW)
6. International Journal of VLSI design & Communication Systems (VLSICS) Vol.4, No.3, June 2013
84
As shown in fig. (4), the charging capability of the paper is improved by this paper. Achieved
settling time is also improved in this paper. The settling time can be defined as the time required
for the output signal reaching within .2% of the output voltage. The simulated settling time is
41.12×10-9s. As shown in fig. (4), the R଼ሺୟ|ୠሻand Rሺୟ|ୠሻ are as the channel resistances of the
output transistor and the auxiliary driving transistor respectively. Then output response can be
written as,
ܸ௨௧ = ܸூ + ሺܸி − ܸூሻ 1 − ݁
ቀି௧
ఛൗ ቁ
൨ (7)
Where ܸூ and ܸி are the initial and final values of the output voltage respectively, and
߬ = ሺܴெ଼ǁܴெሻ × ܥ (8)
ௗೠ
ௗ௧
ቚ
௧ୀ௧భ
=
ሺಷିሻ
ఛ
݁
൬ି
௧
ఛ
൘ ൰
(9)
3. NEW HIGH SPEED BUFFER WITH LOW POWER
Fig.(4) shows the proposed class-AB rail-to-rail high speed buffer with low power dissipation.
This circuit is divided into two parts: The upper part of the circuit consist transistors Mc1a-c3a
with adaptive biasing and added with the transistors M1a-8a. The lower part of the circuit consist
the transistors Mc1b-c3b with adaptive biasing and added with M1b-8b. Total stages of the circuit
perform as a class-AB amplifier. The level shifters M4a-5a and M4b-5b are used to provide the
negative feedback, which extend the input common mode range [13].
The main aim of the negative feedback loop is the low impedances at the source terminals of
transistors M2a-2b. This function gives the result in the form of the gate-source voltages of M2a
(Vgs2a) and M2b (Vgs2b) are kept nearly constant. This functionality is used to show the class-
AB behavior. The inserted transistors M3a-3b are also used to increase the input range, so the
gate source voltages of M3a-3b are same as M2a-2b, which gives the same current behavior
controlled by V୧୬.Transistors M3a-3b performs the function as the constant controlled sources,
which stabilize the DC current of the transistors M7a-7b. The previous paper contains the
drawback of power dissipation. Transistors M8a-8b is inserted between M7a-7b, these transistors
remove the drawback of power dissipation. Function of these transistors is explained in the
previous section. The technique is applied on transistors M8a-8b, which is known as LECTOR
technique.
7. International Journal of VLSI design & Communication Systems (VLSICS) Vol.4, No.3, June 2013
85
4. SIMULATED RESULTS
Using 45nm CMOS technology we designed a new buffer as shown in fig. (4), which is simulated
at 3V supply voltage by help of the cadence tool. Fig.(4) contains the transistors that all have the
same sizing. Bias current IB is fixed at 10µA in buffer circuit. It contains the 1pF capacitor, fixed
at the output side. Table 1 shows the simulated results giving the overall performance. Fig.(5)
shows the frequency jitter waveform which is showing the rising function of buffer circuit.
Fig.(6) shows the overshoot of the output waveform. Fig.(7) shows the period jitter Fig.(8) Shows
the settling time of the circuit, which shows the high speed of the circuit. Fig.(9) shows the power
plot of the output waveform. and fig.(10)shows the input output waveform of the buffer circuit.
ܸ
ܸ௨௧
M1a
Fig.4. Proposed class-AB rail-to-rail high speed buffer with low power.
M2a
M3a
M4a
M5a
Mc3
Mc2 Mc1
M6a
M7a
IB
I
M8a
M8b
Md1bMd2
Md3b
M1
M2 M3b
M4
M5
M6b
M7b
IB
IB
1pF
8. International Journal of VLSI design & Communication Systems (VLSICS) Vol.4, No.3, June 2013
86
TABLE-1
SIMULATION RESULTS OF BUFFER
Parameter Simulated Results
Process technology 45nm
Power supply 3v
Transistor count 22
Settling time (ns) 91.07×10-9
Overshoot (m3
) 23.21×103
Rise time (ps) 139×10-12
Slew rate ( ݒ
ߤݏൗ ) 90
Period jitter 40×10-9
Phase noise 1.227
Total quiescent current(µA) 41.25×10-6
Propagation delay(ps) 292.1×10-12
Fig.(5) Shows the frequency jitter of the circuit
9. International Journal of VLSI design & Communication Systems (VLSICS) Vol.4, No.3, June 2013
Fig.(6)
Fig.(7) Shows the period jitter of the circuit.
Fig.(8) Shows the sittling time of the circuit.
International Journal of VLSI design & Communication Systems (VLSICS) Vol.4, No.3, June 2013
Fig.(6) Shows the oversshoot of the circuit.
Fig.(7) Shows the period jitter of the circuit.
Fig.(8) Shows the sittling time of the circuit.
International Journal of VLSI design & Communication Systems (VLSICS) Vol.4, No.3, June 2013
87
10. International Journal of VLSI design & Communication Systems (VLSICS) Vol.4, No.3, June 2013
88
Fig.(9) Shows the power plot of the circuit.
Fig.(10) Shows the input-output waveform
5. CONCLUSION
A new design scheme for CMOS class-AB buffer using the LECTOR technique is proposed. By
help of this technique reduced leakage current is achieved. Applying the LECTOR technique with
the adaptive biasing into the buffer helped us to get the propagation delay in the range of Pico-
seconds i.e.292.1×10-12, from here we can concluded that the speed of this buffer is very high.
The settling time of proposed circuit is also reduced to the range of nanoseconds. This technique
is also capable to enhance the slew rate, the achieved slew rate is 90(v
µsൗ ).The designed buffers
is applicable in systems requiring the efficient operation with very low quiescent power
consumption.
11. International Journal of VLSI design & Communication Systems (VLSICS) Vol.4, No.3, June 2013
89
REFERENCES
[1] U. Supriya, K. Ramana Rao, “Design of Low Power CMOS Circuits using Leakage Control
Transistor and Multi-Threshold CMOS Techniques.” International Journal. Computer Technology
and Applications, vol.3 (4), 1496-1500, 2012.
[2] Brain S. Cherkauer and Eby G. Friedman, “A Unified Design Methodology for CMOS Tapered
Buffers”, IEEE Transactions on very large scale integration systems, vol.3, no.1, March 1995.
[3] Hoi Lee, Philip K.T. Mok and Ka Nang Leung, “Design of Low Power Analog Drivers Based on
Slew rate Enhancement circuits for CMOS Low-Dropout Regulators.” IEEE Transactions on circuits
and systems-II: Express Briefs, vol.52, no.9, 2010.
[4] Ka Nang Leung and Yuen Sum Ng, “A CMOS Low Dropout Regulator with a momentarily current-
Boosting voltage Buffer”, IEEE Transactions on circuits and systems-I: Regular paper, vol.57, no.9,
2010.
[5] Massimo Aloito , Gaetano Palumbo, “Power Aware Design of Nanometer MCML Tapered Buffer.”
IEEE Transactions on circuits and systems-II: Express Briefs, vol.55 no.1, 2008.
[6] Zhi-Ming Lin and Hsin-Chi Lai, “A High Driving Capability CMOS Buffer Amplifier for TFF LCD
Source Driver.” Engineering Letters, 15:2, EL_15_2_22.Advance online publication:17, 2007.
[7] David Marino , Gaetano Palumbo, and Salvatore Pennnis, “Low-Power Dual active Class-AB Buffer
Amplifier with Self Biasing Network for LCD Column Drivers.” IEEE Transaction 978-1-4244-5309-
2/10/$26.00.2010
[8] D.J.R Cristaldi, S.Pennis, F.Pulvirenti, “Liquid Crystal Display Drivers: Techniques and
circuits.”Springer 2009
[9] J.-H.Wang, J.-C.Qui, H.-Y.Zheng, C.-H.Tsai, C.-Y.Wang, C.-C.Lee, C,-T Chang , “A High Compact
Low Power Slew rate Rail- to-Rail Class-AB Buffer Amplifier for LCD Driver ICs.” Proc, EDSSC
’07, app. 397-400, 2007.
[10] Merih Yeldiz and shahram Minaei and Emre Arslan, “High-slew rate low Quiscent current Rail-to-
Rail CMOS Buffer Amplifier for Flat Panel Displays.” Journal of circuits, systems and computers
vol.20, no.7 (2001)
[11] Chutham Sawigun, Andreas Demothenous, Xiao Liu, and wouter A. Serdijen, “A Compact Rail-to-
Rail Class-AB CMOS Buffer with Slew-rate Enhancement.”IEEE Transactions on circuits and
systems –II: Express briefs, vol.59, no.8, 2012.
[12] G.Ferri,G.-C.Cardarilli and M.Re , “Rail-to-Rail adaptive Biased low-power op-
Amp.”Microelectronics journal 32(2001) 265-272.
[13] amu Hu and Mohammad Sawan, “A Low Power 800mv Rail-to-Rail Class-AB Operational
amplifier.” IEEE CCECE 2003-CCGEI 2003 ,Monted, May/mai 2003.
[14] B.Dilip, P.Surya Prasad and R.S.G. Bhavani, “Leakage Power Reduction in CMOS Circuits Using
Leakage Control Transistor Technique in Nanoscale Technology.” International Journal of Electrnics
Signals and Systems (IJESS) ISSN: 2231-5969, vol.2 ISS-1, 2012.
12. International Journal of VLSI design & Communication Systems (VLSICS) Vol.4, No.3, June 2013
[15] Antonio Lopez Martin, Jose Maria Algueta Miiguel, Lucia Acosta, Jaime Ramirez
Ramon Gonzalez Carvajal, “Design of Two
Approach.” ETRI Journal, vol.33, no.3, 2011.
[16] Tzung-Je Lee, Tieh-Yen Chang Chua
µm 3.3-V CMOS technology” IEEE Tran
no.4, 2009.
[17] Shih-Lun Chen, Ming-Dou Ker, “An Output Buffer for 3.3
CMOS Process.” IEEE Transaction on circuit and systems
Authors
Sadhana Sharma was born in Gwalior (India) on 20 may 1987. She has completed
Bachelor of Engineering from Rajiv Gandhi Technical University, Bhopal.She is
pursuing M. Tech (VLSI Design) From ITM University, Gwalior.Her research
interests are in VLSI Design, Low power, VLSI Signal processing and FPGA Design.
Abhay Vidyarthi was born in Gwalior on 30 november 1979. He has completed Master
of Engineering in C.C.N . from Rajiv Gandhi technical University, Bhopal.His research
areas of interest are Signal Processing and Communication, Cognitive radio, Sensor
networks.He presented papers on Role of Communication And Technology In
Infrastructure Development on 24th
College, Gwalior.
And in National Conference on Wireless Communication on 5th
Engineering College, Gwalior.
S. Akashe was born on 22nd May 1976. This author received his M.Tech from ITM,
Gwalior, Madhya Pradesh, India in the year 2006. The author is
Thapar University, Patiala on the topic of Low Power Memory Cell Design. The
author’s major fields of study are low power VLSI Design, VLSI signal processing,
FPGA Design and Communication System.
He is working as Associate Professor in
department of ITM University, Gwalior, India. His important research publications are
“Implementation of Technology Scaling on Leakage Reduction Techniques using cadence tools with 45 nm
technology,” IEEE, 2011; “High Density and Low Leakage Current Based 5T SRAM Cell Using 45 nrn
Technology,” IEEE, 2011; “Multi Vt 7T SRAM Cell for high speed application At 45 Nm Technology,”
IEEE, 2011
International Journal of VLSI design & Communication Systems (VLSICS) Vol.4, No.3, June 2013
Antonio Lopez Martin, Jose Maria Algueta Miiguel, Lucia Acosta, Jaime Ramirez
n Gonzalez Carvajal, “Design of Two-Stage Class-AB CMOS Buffers: A Systematic
Approach.” ETRI Journal, vol.33, no.3, 2011.
Yen Chang Chua-Chin Wang, “Wide-Range 5.0/3.3/ 1.8V I/OBuffer using 0.35
V CMOS technology” IEEE Transaction on circuit and systems-i: regular papers, vol.56,
Dou Ker, “An Output Buffer for 3.3-V Application in a 0.13
CMOS Process.” IEEE Transaction on circuit and systems-II: Express Briefs, vol. 54, no.
Sadhana Sharma was born in Gwalior (India) on 20 may 1987. She has completed
Bachelor of Engineering from Rajiv Gandhi Technical University, Bhopal.She is
pursuing M. Tech (VLSI Design) From ITM University, Gwalior.Her research
rests are in VLSI Design, Low power, VLSI Signal processing and FPGA Design.
Abhay Vidyarthi was born in Gwalior on 30 november 1979. He has completed Master
of Engineering in C.C.N . from Rajiv Gandhi technical University, Bhopal.His research
areas of interest are Signal Processing and Communication, Cognitive radio, Sensor
networks.He presented papers on Role of Communication And Technology In
Infrastructure Development on 24th-25th Apr. 2007 at N.R.I.-I.T.M., Engineering
nd in National Conference on Wireless Communication on 5th-6th Apr 2008 at G.E.C.
S. Akashe was born on 22nd May 1976. This author received his M.Tech from ITM,
Gwalior, Madhya Pradesh, India in the year 2006. The author is pursuing Ph.D from
Thapar University, Patiala on the topic of Low Power Memory Cell Design. The
author’s major fields of study are low power VLSI Design, VLSI signal processing,
FPGA Design and Communication System.
He is working as Associate Professor in Electronics and Instrumentation Engineering
department of ITM University, Gwalior, India. His important research publications are
“Implementation of Technology Scaling on Leakage Reduction Techniques using cadence tools with 45 nm
“High Density and Low Leakage Current Based 5T SRAM Cell Using 45 nrn
Technology,” IEEE, 2011; “Multi Vt 7T SRAM Cell for high speed application At 45 Nm Technology,”
International Journal of VLSI design & Communication Systems (VLSICS) Vol.4, No.3, June 2013
90
Antonio Lopez Martin, Jose Maria Algueta Miiguel, Lucia Acosta, Jaime Ramirez-Angulo and
AB CMOS Buffers: A Systematic
Range 5.0/3.3/ 1.8V I/OBuffer using 0.35
i: regular papers, vol.56,
V Application in a 0.13-µm 1/ 2. 5-V
II: Express Briefs, vol. 54, no. 1, 2007.
“Implementation of Technology Scaling on Leakage Reduction Techniques using cadence tools with 45 nm
“High Density and Low Leakage Current Based 5T SRAM Cell Using 45 nrn
Technology,” IEEE, 2011; “Multi Vt 7T SRAM Cell for high speed application At 45 Nm Technology,”