This paper presents the design of Low Drop-Out (LDO) voltage regulator has fast transient response and which exploits a few current else low quiescent current in the operational amplifier PMOS type. We use band-gap reference for eliminate the temperature dependence. The proposed LDO voltage regulator implemented in 0.18-μm CMOS technology, we use Folded cascode CMOS amplifiers high performance in the stability , provide fast transient response which explains a fast settling, the LDO itself should provide in the output regulator voltages at t equal 2ps with transient variation of the voltage less than 170mV. High accuracy in the DC response terms, the simulation results show that the accuracy of the output regulator voltages is 1.54±0.009V, and power consumption of 1.51 mW.
Design of Low Voltage Low Power CMOS OP-AMPIJERA Editor
Operational amplifiers are an integral part of many analog and mixed signal systems. As the demand for mixed
mode integrated circuits increases, the design of analog circuits such as operational amplifiers in CMOS
technology becomes more critical. This paper presents a two stage CMOS operational amplifier, which operates
at ±1.8V power supply using TSMC 0.18um CMOS technology. The OP-AMP designed exhibit unity gain
frequency of 12.6 MHz, and gain of 55.5db with 300uw power dissipation. The gain margin and phase margin
of OP-AMP is 45˚ and 60˚ respectively. Design and simulation has been carried out in P Spice tool.
In this article, we proposed a Variable threshold MOSFET(VTMOS)approach which is realized from Dynamic Threshold MOSFET(DTMOS), suitable for sub-threshold digital circuit operation. Basically the principle of sub- threshold logics is operating MOSFET in sub-threshold region and using the leakage current in that region for switching action, there by drastically decreasing power .To reduce the power consumption of sub-threshold circuits further, a novel body biasing technique termed VTMOS is introduced .VTMOS approach is realized from DTMOS approach. Dynamic threshold MOS (DTMOS) circuits provide low leakage and high current drive, compared to CMOS circuits, operated at lower voltages.
The VTMOS is based on operating the MOS devices with an appropriate substrate bias which varies with gate voltage, by connecting a positive bias voltage between gate and substrate for NMOS and negative bias voltage between gate and substrate for PMOS. With VTMOS, there is a considerable reduction in operating current and power dissipation, while the remaining characteristics are almost the same as those of DTMOS. Results of our investigations show that VTMOS circuits improves the power up to 50% when compared to CMOS and DTMOS circuits, in sub- threshold region..
The performance analysis and comparison of VTMOS , DTMOS and CMOS is made and test results of Power dissipation, Propagation delay and Power delay product are presented to justify the superiority of VTMOS logic over conventional sub-threshold logics using Hspice Tool. . The dependency of these parameters on frequency of operation has also been investigated.
Analysis and Design of A Low-Voltage Low-Power Double-Tail Comparator. This is a final semester Mtech project on VLSI design implementation of dual tail comparator in a modifyied version. This design is implemented using VHDL Language with 100% Source code synthesizable available. Software for free to download and knowledge transfer for the same project is also being implemented..The design is implemented using FSM technology, low power is achieved in this project.area utilization is the major advantage in this project.Low power techniques such as Clock gating, power gating is implemented in this project.,ieee reference paper is used for the base.
An improved design of CMOS dynamic latch comparator with dual input dual output with a simple
design of three stages is represented. The basic disadvantages of latch type comparators are overcome by
producing an edge triggered comparison. The circuit is designed for a resolution of 300nV and the power
consumption is reduced to 450uW. It is designed for 1.8V DC supply voltage and 1 MHz clock frequency for
PVT variations. The simulation of the comparator is done in Cadence® Virtuoso Analog Design Environment
using 180nm technology. The error quotient is reduced less than 5% by adding a buffer stage. The delay is
brought down to 5nS. The active area appreciably is reduced. Layout of the proposed comparator has been
simulated in Cadence® Virtuoso Layout XL Design Environment. DRC and LVS have been verified.
Design of Low Voltage Low Power CMOS OP-AMPIJERA Editor
Operational amplifiers are an integral part of many analog and mixed signal systems. As the demand for mixed
mode integrated circuits increases, the design of analog circuits such as operational amplifiers in CMOS
technology becomes more critical. This paper presents a two stage CMOS operational amplifier, which operates
at ±1.8V power supply using TSMC 0.18um CMOS technology. The OP-AMP designed exhibit unity gain
frequency of 12.6 MHz, and gain of 55.5db with 300uw power dissipation. The gain margin and phase margin
of OP-AMP is 45˚ and 60˚ respectively. Design and simulation has been carried out in P Spice tool.
In this article, we proposed a Variable threshold MOSFET(VTMOS)approach which is realized from Dynamic Threshold MOSFET(DTMOS), suitable for sub-threshold digital circuit operation. Basically the principle of sub- threshold logics is operating MOSFET in sub-threshold region and using the leakage current in that region for switching action, there by drastically decreasing power .To reduce the power consumption of sub-threshold circuits further, a novel body biasing technique termed VTMOS is introduced .VTMOS approach is realized from DTMOS approach. Dynamic threshold MOS (DTMOS) circuits provide low leakage and high current drive, compared to CMOS circuits, operated at lower voltages.
The VTMOS is based on operating the MOS devices with an appropriate substrate bias which varies with gate voltage, by connecting a positive bias voltage between gate and substrate for NMOS and negative bias voltage between gate and substrate for PMOS. With VTMOS, there is a considerable reduction in operating current and power dissipation, while the remaining characteristics are almost the same as those of DTMOS. Results of our investigations show that VTMOS circuits improves the power up to 50% when compared to CMOS and DTMOS circuits, in sub- threshold region..
The performance analysis and comparison of VTMOS , DTMOS and CMOS is made and test results of Power dissipation, Propagation delay and Power delay product are presented to justify the superiority of VTMOS logic over conventional sub-threshold logics using Hspice Tool. . The dependency of these parameters on frequency of operation has also been investigated.
Analysis and Design of A Low-Voltage Low-Power Double-Tail Comparator. This is a final semester Mtech project on VLSI design implementation of dual tail comparator in a modifyied version. This design is implemented using VHDL Language with 100% Source code synthesizable available. Software for free to download and knowledge transfer for the same project is also being implemented..The design is implemented using FSM technology, low power is achieved in this project.area utilization is the major advantage in this project.Low power techniques such as Clock gating, power gating is implemented in this project.,ieee reference paper is used for the base.
An improved design of CMOS dynamic latch comparator with dual input dual output with a simple
design of three stages is represented. The basic disadvantages of latch type comparators are overcome by
producing an edge triggered comparison. The circuit is designed for a resolution of 300nV and the power
consumption is reduced to 450uW. It is designed for 1.8V DC supply voltage and 1 MHz clock frequency for
PVT variations. The simulation of the comparator is done in Cadence® Virtuoso Analog Design Environment
using 180nm technology. The error quotient is reduced less than 5% by adding a buffer stage. The delay is
brought down to 5nS. The active area appreciably is reduced. Layout of the proposed comparator has been
simulated in Cadence® Virtuoso Layout XL Design Environment. DRC and LVS have been verified.
Design of Low Power & High Speed Comparator with 0.18μm Technology for ADC Ap...IJERA Editor
In Analog to Digital Converter (ADC), high speed comparator influences the overall performance of ADC directly. This paper presents the high speed & low power design of a CMOS comparator. Schematic design of this comparator is fabricated in a 0.18μm UMC Technology with 1.8V power supply and simulated in cadence Virtuoso. Simulation results are presented and it shows that this design can work under high speed of 0.8108 GHz. The design has a low offset voltage, low power dissipation 108.0318μw. In addition we have verified present results with schematic view design and also compared these results with earlier reported work and got improvement in this reported work.
Design of a Low Noise Amplifier using 0.18μm CMOS technologytheijes
The International Journal of Engineering & Science is aimed at providing a platform for researchers, engineers, scientists, or educators to publish their original research results, to exchange new ideas, to disseminate information in innovative designs, engineering experiences and technological skills. It is also the Journal's objective to promote engineering and technology education. All papers submitted to the Journal will be blind peer-reviewed. Only original articles will be published.
Design of Two CMOS Differential Amplifiersbastrikov
High performance, 0.6u process CMOS differential amplifiers were designed in Cadence. Design specifications included differential gain, 3-db bandwidth, output swing, input common mode range, phase margin, total static power consumption, slew rate, and common mode rejection ratio.
This paper addresses a novel approach for designing and modeling of the isolated
flyback converter. Modeling is done without parasitic as well as with parasitic components.
A detailed analysis, simulation and different control strategy are conferred for flyback
converter in continuous conduction mode (CCM). To verify the design and modeling at
primary stage, study of the converter is practiced in CCM operation for input AC voltage
230V at 50Hz and output DC voltage of 5V and 50W output power rating using PSIM 6.0
software. Simulation result shows a little ripple in output of the converter in open loop. Finally
in order to evaluate the system as well as response of the controller, flyback converter is
simulated using MATLAB. This work, highlighting the modeling when the system have
transformer and facilitate designers to go for it when they need one or more than one output
for a given application upto 150W
This paper presents investigation and performance analysis of novel down sampling based clamping SV PWM technique for diode and cascaded Multi-level Invereter fed to Induction motor drive. A novel down sampling based clamping SVPWM has developed by adding triangular off set to sinusoidal fundamental waveform is modified by down sampling the reference wave by order of 10 so this technique is called clamping space vector pulse width modulation techniques such as PD, POD and APOD. so as to shift the lower order harmonics to higher order side. This novel carrier is compared with the offset injected space vector reference waveform to generate the required PWM pulses to the inverter. To analyze the performance of the proposed PWM technique it is implemented on seven level diode and cascaded Multi-level Inverter using Matlab/Simulink software tool for output line, phase voltage, currents, speed, torque and Total harmonic distortion analysis.
BASK Generator using analog switch
BFSK Generator using analog switch
BPSK Generator using analog switch
MATLAB EXPERIMENTS
4.Mean square estimation of signals
5. BASK
6. BFSK
7. BPSK
MICROWAVE EXPERIMENTS
8.Klystron characteristics
9.Frequency and wavelength measurement
10.VSWR measurement
PARASITIC-AWARE FULL PHYSICAL CHIP DESIGN OF LNA RFIC AT 2.45GHZ USING IBM 13...Ilango Jeyasubramanian
• Analyzed and designed a single stage cascoded LNA with Q-based calculation for desired input matching, output matching, power gain, IIP3 and Noise figure, including all the parasitics in the on-chip and off-chip components using SpectreRF simulations.
• Synthesized the LNA layout for on-chip components with spiral inductor, MOS capacitor, MIM capacitor and Bond-pads with ESD protections.
• Our LNA exhibited a noise figure of 1.23dB, linear gain of 18.54 dB, IIP3 of -4.60dbm, S11 of -31.11db, S22 of -24.91db with the operating range between 2.4-2.5GHZ along with 10% variation tolerance.
The Analysis of Dead Time on Switching Loss in High and Low Side MOSFETs of Z...IDES Editor
This work is about the analysis of dead time variation
on switching losses in a Zero Voltage Switching (ZVS)
synchronous buck converter (SBC) circuit. In high frequency
converter circuits, switching losses are commonly linked with
high and low side switches of SBC circuit. They are activated
externally by the gate driver circuit. The duty ratio, dead time
and resonant inductor are the parameters that affect the
efficiency of the circuit. These variables can be adjusted for
the optimization purposes. The study primarily focuses on
varying the settings of input pulses of the MOSFETs in the
resonant gate driver circuit which consequently affects the
performance of the ZVS synchronous buck converter circuit.
Using the predetermined inductor of 9 nH, the frequency is
maintained at 1 MHz for each cycle transition. The switching
loss graph is obtained and switching losses for both S1 and S2
are calculated and compared to the findings from previous
work. It has shown a decrease in losses by 13.8 % in S1. A dead
time of 15 ns has been determined to be optimized value in
the SBC design.
79.4dB/100MHz/23mW SNDR/BW/Power 7th order opampless multibit sigma delta modulator
Takashi Miki
Abstract:
A novel opampless multibit continuous-time (CT) sigma delta modulator is designed. Newly designed resonators without opamps are used for the modulator in order to suppress power consumption. Averaging multibit quantization technique is used for the internal quantizer of the modulator in order to compensate for the loss of the loop gain because of eliminating opamps from the loop filter. Averaging multibit quantization technique also enables to obtain a high signal-to-noise-distortion-ratio (SNDR) without dynamic element matching (ELD) in feedback DACs. The modulator is studied in transistor level simulations with 45nm process model files, and the result shows that it can achieve 79.4dB SNDR, 100MHz band width (BW), and 23mW power consumption.
Design of an ADC using High Precision Comparator with Time Domain Offset Canc...IJTET Journal
Abstract— The comparator is a combinational logic circuit that plays an important role in the design of analog to digital converter. One of its most important properties is its input referred offset. When mismatches are present in a dynamic comparator, due to internal positive feedback and transient response, it is always challenging to analytically predict the input-referred random offset voltages since the operating points of transistors are time varying. To overcome the offset effect a novel time-domain bulk-tuned offset cancellation method is applied to a low power dynamic comparator. Using this comparator in analog to digital converter it does not increase the power consumption, but at the same time the delay is reduced and the speed is increased. The comparator is designed using the 250-nm CMOS technology in mentor graphics tool. Operating at a supply voltage of 5v and clock frequency 100MHZ, the comparator together with the offset cancellation circuitry dissipates 335.49nW of power and dissipates 1.027uW of power for comparator without offset cancellation circuit. The simulation result indicates that the offset cancellation circuitry consumes negligible power and it does not draw any static current. Using this high precision offset cancelled comparator in the analog to digital converter circuit the static power consumption is less and it is able to work under very low supply voltage.
Flexibility a key factor to testability ijseajournal
Testability is an important software quality factor that is ineffective if it is not available at an early stage in
the development life-cycle. It becomes more essential in the case of object oriented design. Flexibility is an
important key factor to testability analysis and measurement for delivering high class testable and
maintainable software. Flexibility is a criterion of crucial significance to software developers, designers
and the quality controllers. It constantly guides and supports to avoid wastage of resources as well as
enable the designers for continuous improvement in the development process. Flexibility is concerned with
building high quality and reliable software within the constraints of cost and time. It greatly influences
cost, quality and reliability at software evolution process. Despite the fact flexibility is vital and highly
significant aspect for software development processes, it is poorly managed. This paper focuses the need
and importance of flexibility early at design phase. A model has been proposed for flexibility measurement
of object oriented design by establishing multiple linear regression. Finally the proposed model has been
validated using experimental tryout.
Management of time uncertainty in agileijseajournal
The rise of the use of mobile technologies in the world, such as smartphones and tablets, connected to
mobile networks is changing old habits and creating new ways for the society to access information and
interact with computer systems. Thus, traditional information systems are undergoing a process of
adaptation to this new computing context. However, it is important to note that the characteristics of this
new context are different. There are new features and, thereafter, new possibilities, as well as restrictions
that did not exist before. Finally, the systems developed for this environment have different requirements
and characteristics than the traditional information systems. For this reason, there is the need to reassess
the current knowledge about the processes of planning and building for the development of systems in this
new environment. One area in particular that demands such adaptation is software estimation. The
estimation processes, in general, are based on characteristics of the systems, trying to quantify the
complexity of implementing them. Hence, the main objective of this paper is to present a proposal for an
estimation model for mobile applications, as well as discuss the applicability of traditional estimation
models for the purpose of developing systems in the context of mobile computing. Hence, the main objective
of this paper is to present an effort estimation model for mobile applications.
A maintainability enhancement procedureijseajournal
In mobile communications age, environment changes rapidly, the requirements change is the software
project must face challenge. Able to overcome the impact of requirements change, software development
risk can be effectively decreased. In order to reduce software requirements change risk, the paper
investigates the major software development models and recommends the adaptable requirements change
software development. Agile development applied the Iterative and Incremental Development (IID)
approach, focuses on workable software and client communication. In software development, agile
development is a very suitable approach to handle the requirements change. However, agile development
maintenance existed many defects that include development documents control, user story inspection and
CM system. The maintenance defects of agile development should be improved. Analysing and collecting
the critical quality factors of agile development maintainability, in this paper proposes the Agile
Development Maintainability Measurement (ADMM) model. Based on ADMM model, the Agile
Development Maintainability Enhancement (ADME) procedure can be defined and deployed for reducing
the risk of requirements change.
Design of Low Power & High Speed Comparator with 0.18μm Technology for ADC Ap...IJERA Editor
In Analog to Digital Converter (ADC), high speed comparator influences the overall performance of ADC directly. This paper presents the high speed & low power design of a CMOS comparator. Schematic design of this comparator is fabricated in a 0.18μm UMC Technology with 1.8V power supply and simulated in cadence Virtuoso. Simulation results are presented and it shows that this design can work under high speed of 0.8108 GHz. The design has a low offset voltage, low power dissipation 108.0318μw. In addition we have verified present results with schematic view design and also compared these results with earlier reported work and got improvement in this reported work.
Design of a Low Noise Amplifier using 0.18μm CMOS technologytheijes
The International Journal of Engineering & Science is aimed at providing a platform for researchers, engineers, scientists, or educators to publish their original research results, to exchange new ideas, to disseminate information in innovative designs, engineering experiences and technological skills. It is also the Journal's objective to promote engineering and technology education. All papers submitted to the Journal will be blind peer-reviewed. Only original articles will be published.
Design of Two CMOS Differential Amplifiersbastrikov
High performance, 0.6u process CMOS differential amplifiers were designed in Cadence. Design specifications included differential gain, 3-db bandwidth, output swing, input common mode range, phase margin, total static power consumption, slew rate, and common mode rejection ratio.
This paper addresses a novel approach for designing and modeling of the isolated
flyback converter. Modeling is done without parasitic as well as with parasitic components.
A detailed analysis, simulation and different control strategy are conferred for flyback
converter in continuous conduction mode (CCM). To verify the design and modeling at
primary stage, study of the converter is practiced in CCM operation for input AC voltage
230V at 50Hz and output DC voltage of 5V and 50W output power rating using PSIM 6.0
software. Simulation result shows a little ripple in output of the converter in open loop. Finally
in order to evaluate the system as well as response of the controller, flyback converter is
simulated using MATLAB. This work, highlighting the modeling when the system have
transformer and facilitate designers to go for it when they need one or more than one output
for a given application upto 150W
This paper presents investigation and performance analysis of novel down sampling based clamping SV PWM technique for diode and cascaded Multi-level Invereter fed to Induction motor drive. A novel down sampling based clamping SVPWM has developed by adding triangular off set to sinusoidal fundamental waveform is modified by down sampling the reference wave by order of 10 so this technique is called clamping space vector pulse width modulation techniques such as PD, POD and APOD. so as to shift the lower order harmonics to higher order side. This novel carrier is compared with the offset injected space vector reference waveform to generate the required PWM pulses to the inverter. To analyze the performance of the proposed PWM technique it is implemented on seven level diode and cascaded Multi-level Inverter using Matlab/Simulink software tool for output line, phase voltage, currents, speed, torque and Total harmonic distortion analysis.
BASK Generator using analog switch
BFSK Generator using analog switch
BPSK Generator using analog switch
MATLAB EXPERIMENTS
4.Mean square estimation of signals
5. BASK
6. BFSK
7. BPSK
MICROWAVE EXPERIMENTS
8.Klystron characteristics
9.Frequency and wavelength measurement
10.VSWR measurement
PARASITIC-AWARE FULL PHYSICAL CHIP DESIGN OF LNA RFIC AT 2.45GHZ USING IBM 13...Ilango Jeyasubramanian
• Analyzed and designed a single stage cascoded LNA with Q-based calculation for desired input matching, output matching, power gain, IIP3 and Noise figure, including all the parasitics in the on-chip and off-chip components using SpectreRF simulations.
• Synthesized the LNA layout for on-chip components with spiral inductor, MOS capacitor, MIM capacitor and Bond-pads with ESD protections.
• Our LNA exhibited a noise figure of 1.23dB, linear gain of 18.54 dB, IIP3 of -4.60dbm, S11 of -31.11db, S22 of -24.91db with the operating range between 2.4-2.5GHZ along with 10% variation tolerance.
The Analysis of Dead Time on Switching Loss in High and Low Side MOSFETs of Z...IDES Editor
This work is about the analysis of dead time variation
on switching losses in a Zero Voltage Switching (ZVS)
synchronous buck converter (SBC) circuit. In high frequency
converter circuits, switching losses are commonly linked with
high and low side switches of SBC circuit. They are activated
externally by the gate driver circuit. The duty ratio, dead time
and resonant inductor are the parameters that affect the
efficiency of the circuit. These variables can be adjusted for
the optimization purposes. The study primarily focuses on
varying the settings of input pulses of the MOSFETs in the
resonant gate driver circuit which consequently affects the
performance of the ZVS synchronous buck converter circuit.
Using the predetermined inductor of 9 nH, the frequency is
maintained at 1 MHz for each cycle transition. The switching
loss graph is obtained and switching losses for both S1 and S2
are calculated and compared to the findings from previous
work. It has shown a decrease in losses by 13.8 % in S1. A dead
time of 15 ns has been determined to be optimized value in
the SBC design.
79.4dB/100MHz/23mW SNDR/BW/Power 7th order opampless multibit sigma delta modulator
Takashi Miki
Abstract:
A novel opampless multibit continuous-time (CT) sigma delta modulator is designed. Newly designed resonators without opamps are used for the modulator in order to suppress power consumption. Averaging multibit quantization technique is used for the internal quantizer of the modulator in order to compensate for the loss of the loop gain because of eliminating opamps from the loop filter. Averaging multibit quantization technique also enables to obtain a high signal-to-noise-distortion-ratio (SNDR) without dynamic element matching (ELD) in feedback DACs. The modulator is studied in transistor level simulations with 45nm process model files, and the result shows that it can achieve 79.4dB SNDR, 100MHz band width (BW), and 23mW power consumption.
Design of an ADC using High Precision Comparator with Time Domain Offset Canc...IJTET Journal
Abstract— The comparator is a combinational logic circuit that plays an important role in the design of analog to digital converter. One of its most important properties is its input referred offset. When mismatches are present in a dynamic comparator, due to internal positive feedback and transient response, it is always challenging to analytically predict the input-referred random offset voltages since the operating points of transistors are time varying. To overcome the offset effect a novel time-domain bulk-tuned offset cancellation method is applied to a low power dynamic comparator. Using this comparator in analog to digital converter it does not increase the power consumption, but at the same time the delay is reduced and the speed is increased. The comparator is designed using the 250-nm CMOS technology in mentor graphics tool. Operating at a supply voltage of 5v and clock frequency 100MHZ, the comparator together with the offset cancellation circuitry dissipates 335.49nW of power and dissipates 1.027uW of power for comparator without offset cancellation circuit. The simulation result indicates that the offset cancellation circuitry consumes negligible power and it does not draw any static current. Using this high precision offset cancelled comparator in the analog to digital converter circuit the static power consumption is less and it is able to work under very low supply voltage.
Flexibility a key factor to testability ijseajournal
Testability is an important software quality factor that is ineffective if it is not available at an early stage in
the development life-cycle. It becomes more essential in the case of object oriented design. Flexibility is an
important key factor to testability analysis and measurement for delivering high class testable and
maintainable software. Flexibility is a criterion of crucial significance to software developers, designers
and the quality controllers. It constantly guides and supports to avoid wastage of resources as well as
enable the designers for continuous improvement in the development process. Flexibility is concerned with
building high quality and reliable software within the constraints of cost and time. It greatly influences
cost, quality and reliability at software evolution process. Despite the fact flexibility is vital and highly
significant aspect for software development processes, it is poorly managed. This paper focuses the need
and importance of flexibility early at design phase. A model has been proposed for flexibility measurement
of object oriented design by establishing multiple linear regression. Finally the proposed model has been
validated using experimental tryout.
Management of time uncertainty in agileijseajournal
The rise of the use of mobile technologies in the world, such as smartphones and tablets, connected to
mobile networks is changing old habits and creating new ways for the society to access information and
interact with computer systems. Thus, traditional information systems are undergoing a process of
adaptation to this new computing context. However, it is important to note that the characteristics of this
new context are different. There are new features and, thereafter, new possibilities, as well as restrictions
that did not exist before. Finally, the systems developed for this environment have different requirements
and characteristics than the traditional information systems. For this reason, there is the need to reassess
the current knowledge about the processes of planning and building for the development of systems in this
new environment. One area in particular that demands such adaptation is software estimation. The
estimation processes, in general, are based on characteristics of the systems, trying to quantify the
complexity of implementing them. Hence, the main objective of this paper is to present a proposal for an
estimation model for mobile applications, as well as discuss the applicability of traditional estimation
models for the purpose of developing systems in the context of mobile computing. Hence, the main objective
of this paper is to present an effort estimation model for mobile applications.
A maintainability enhancement procedureijseajournal
In mobile communications age, environment changes rapidly, the requirements change is the software
project must face challenge. Able to overcome the impact of requirements change, software development
risk can be effectively decreased. In order to reduce software requirements change risk, the paper
investigates the major software development models and recommends the adaptable requirements change
software development. Agile development applied the Iterative and Incremental Development (IID)
approach, focuses on workable software and client communication. In software development, agile
development is a very suitable approach to handle the requirements change. However, agile development
maintenance existed many defects that include development documents control, user story inspection and
CM system. The maintenance defects of agile development should be improved. Analysing and collecting
the critical quality factors of agile development maintainability, in this paper proposes the Agile
Development Maintainability Measurement (ADMM) model. Based on ADMM model, the Agile
Development Maintainability Enhancement (ADME) procedure can be defined and deployed for reducing
the risk of requirements change.
A model for run time software architecture adaptationijseajournal
Since the global demand for software systems and constantly changing environments and systems is
increasing, the adaptability of software systems is of significant importance. Due to the architecture of
software system is a high-level view of the system and makes the modifiability possible at an overall level,
the adaptability of the software can be considered an effective approach to adapt software systems by
changing architecture configuration. In this study, the architecture configuration is modified through xADL
language which is a software architecture description language with a high flexibility. Software
architecture reconfiguration is done based on existing rules of rule-based system, which are written with
respect to three strategies of load balancing, fixed bandwidth and fixed latency. The proposed model of the
study is simulated based on samples of client-server system, video conferencing system and students’
grading system. The proposed model can be used in all types of architecture, include Client Server
Architecture, Service Oriented Architecture and etc.
Secured cloud support for global softwareijseajournal
This paper presents core problem solution to security of Global Software Development Requirement
Information. Currently the major issue deals with hacking of sensitive client information which may lead to
major financial as well as social loss. To avoid this system provides cloud security by encryption of data as
well as deployment of tool over the cloud will provide significant security to whole global content
management system. The core findings are presented in terms of how hacker hacks such systems and what
counter steps need to follow. Our algorithmic development provide random information storage at various
cloud nodes to secure our client requirement data files.
A novel approach for clone group mappingijseajournal
Clone group mapping has a very important significance in the evolution of code clone. The topic modeling
techniques were applied into code clone firstly and a new clone group mapping method was proposed. The
method is very effective for not only Type-1 and Type-2 clone but also Type-3 clone .By making full use of
the source text and structure information, topic modeling techniques transform the mapping problem of
high-dimensional code space into a low-dimensional topic space, the goal of clone group mapping was
indirectly reached by mapping clone group topics. Experiments on four open source software show that the
recall and precision are up to 0.99, thus the method can effectively and accurately reach the goal of clone
group mapping.
DETECTION AND REFACTORING OF BAD SMELL CAUSED BY LARGE SCALEijseajournal
Bad smells are signs of potential problems in code. Detecting bad smells, however, remains time
consuming for software engineers despite proposals on bad smell detection and refactoring tools. Large
Class is a kind of bad smells caused by large scale, and the detection is hard to achieve automatically. In
this paper, a Large Class bad smell detection approach based on class length distribution model and
cohesion metrics is proposed. In programs, the lengths of classes are confirmed according to the certain
distributions. The class length distribution model is generalized to detect programs after grouping.
Meanwhile, cohesion metrics are analyzed for bad smell detection. The bad smell detection experiments of
open source programs show that Large Class bad smell can be detected effectively and accurately with this
approach, and refactoring scheme can be proposed for design quality improvements of programs.
MULTIVIEW SOA : EXTENDING SOA USING A PRIVATE CLOUD COMPUTING AS SAAS AND DAASijseajournal
This work is based on two major areas, the Multiview Service Oriented Architecture and the combination between the computing cloud and MV-SOA. Thus, it is suggested to extend firstly the service oriented architecture (SOA) into an architecture called MV-SOA by adding two components, the Multiview service generator, whose role is to transform the classic service into Multiview service, and the data base, this component seeks to stock all of consumer service information. It is also suggested to combine the computing cloud and Multiview Service Oriented Architecture MVSOA. To reach such combination, the
MVSOA architecture was taken and we added to the client-side a private cloud in SaaS and DaaS.
Integrating profiling into mde compilersijseajournal
Scientific computation requires more and more performance in its algorithms. New massively parallel
architectures suit well to these algorithms. They are known for offering high performance and power
efficiency. Unfortunately, as parallel programming for these architectures requires a complex distribution
of tasks and data, developers find difficult to implement their applications effectively. Although approaches
based on source-to-source intends to provide a low learning curve for parallel programming and take
advantage of architecture features to create optimized applications, programming remains difficult for
neophytes. This work aims at improving performance by returning to the high-level models, specific
execution data from a profiling tool enhanced by smart advices computed by an analysis engine. In order to
keep the link between execution and model, the process is based on a traceability mechanism. Once the
model is automatically annotated, it can be re-factored aiming better performances on the re-generated
code. Hence, this work allows keeping coherence between model and code without forgetting to harness the
power of parallel architectures. To illustrate and clarify key points of this approach, we provide an
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FAST TRANSIENT RESPONSE LOW DROPOUT VOLTAGE REGULATOR
1. International Journal of Embedded Systems and Applications (IJESA) Vol.4, No.2/3, September 2014
FAST TRANSIENT RESPONSE LOW DROP-OUT
VOLTAGE REGULATOR
[
Hicham Akhamal1, Mostafa Chakir 2 and Hassan Qjidaa3
1Laboratoire d’Electronique Signaux – Systèmes et Informatique(LESSI), Sidi Mohamed Ben
Abdellah University, Dhar El Mehraz sciences Faculty, Fez, Morocco
ABSTRACT
This paper presents the design of Low Drop-Out (LDO) voltage regulator has fast transient response and
which exploits a few current else low quiescent current in the operational amplifier PMOS type. We use
band-gap reference for eliminate the temperature dependence. The proposed LDO voltage regulator
implemented in 0.18-μm CMOS technology, we use Folded cascode CMOS amplifiers high performance in
the stability , provide fast transient response which explains a fast settling, the LDO itself should provide in
the output regulator voltages at t equal 2ps with transient variation of the voltage less than 170mV. High
accuracy in the DC response terms, the simulation results show that the accuracy of the output regulator
voltages is 1.54±0.009V, and power consumption of 1.51 mW.
KEYWORDS
Low-dropout (LDO ) voltage regulator, Band-gap reference, Fast transient response, Current efficiency,
Figure of merit Layout.
1.INTRODUCTION
The power management systems is importance and increased much in the electronics industry
elsewhere the integrated circuits is exist in the last few years, The rationale is that LDO yields a
good line and load regulation while maintaining a stable, constant and accuracy output voltage.
Those battery-powered and handheld devices require advanced power management techniques to
extend the life cycle of the battery and consequently the operation cycle of the device. I have
chosen this architecture of a LDO linear regulator works for a frame made this set of
specifications and find my position in the study of other integrated circuit with very high
performance. All times power management in integrated circuits has been gaining a high-efficiency
power management module is necessary such as low-power power converter or low
dropout regulator to integrate circuit more attention because it allows for drastic reduction in the
consumption of battery-powered portable equipment, such as cellular phones, pagers, laptops,
camera recorders, and PDAs. The regulator is divided into two types, voltage mode LDO and
current mode LDO, the regulator which uses the voltage mode is named linear regulator,
therefore, the regulator which uses the current-mode is named shunt regulator. The power
transistor of the voltage-mode linear regulator is series with the load resistant, an error amplifier
and the power transistor are supplied by the same power supply (VIN), the series combination
forms a voltage divider to reduce the unregulated input source to a regulated output one.
DOI : 10.5121/ijesa.2014.4301 1
2. International Journal of Embedded Systems and Applications (IJESA) Vol.4, No.2/3, September 2014
This paper is organized as follows. In section II, description of circuit and the theoretical study of
the characteristics proposed LDO voltage regulator are discussed. In section III, the static-state
and dynamic-state characteristics are simulated and corresponding simulation results are
summarized. The conclusion is derived in section IV.
The top level structure of the proposed LDO shown in Fig. 1 It includes the following modules as
error amplifier, band-gap reference, Equivalent Series Resistance (ESR), Power Transistor (PM)
and Feedback Network (FNPD). This work presents a design of a LDO regulator in a 0.18-
μm CMOS technology.
2
Vin
Error
amplifier
Cc
Vout
Pass
Element
Rb1 Gnd
Rb2
RL
CL
Bias
Circuit
EA
2. LDO ARCHITECTURE
2.1. Description Of Circuit
VREF
Fig. 1. Structure of the Regulator LDO Circuit.
Voltage
Reference
The (Fig. 1) enclose a schematic of a regulators LDO voltage based on a PMOS, the structure of
LDO implemented in CMOS 0.18μm technology. This transistor PMOS with common source
connection as the pass element transistor between the input and output voltages. A part of the
output voltage is fed back through R1 and R2 to the input of the amplifier and is compared to the
voltage reference VREF. Capacitor CL stands for the capacitive load. The current Load (IL)
represents the load whose current is supplied by the power transistor [1], [2], [4], [5].
An EA signal is fed back to the gate of the pass transistor through the feedback loop to respond
to the load current while keeping the output voltage constant. The Voltage Control regulator
which is an electrical regulator is designed to maintain a constant voltage level, the Voltage
Control regulator regulates the Voltage supply to the load by adjusting the load current. It consists
of an error amplifier, a power transistor, and the load elements.
3. International Journal of Embedded Systems and Applications (IJESA) Vol.4, No.2/3, September 2014
3
2.2. Regulator Schematic And Parameters
The circuit of the proposed voltage -mode shunt regulator is shown in Fig. 2. Transistors M1 to
M11 form the first-stage amplifier, while M12 to M1 form the bias amplifier. R1 and R2 are the
resistive feedback network, the power transistor is labeled as MP. The error amplifier detects two
input signal regarding the reference voltage VREF and the feedback signal Voltage between R1
and R2 . M32,M33 and M34 are the Simple current mirror in the band gap. from M22 to M31
form the two-stage operational amplifier utilized in this design is shown in Fig. 2, the band-gap
circuit consists of two loops; one with negative feedback (through M23) and one with positive
feedback (through M22), and since it consists of a nMOS differential pair operating, this may lead
to stability especially if the positive feedback dominates over the negative feedback.
Fig. 2. Schematic of the proposed LDO voltage regulator.
From a equivalent small signal model of the proposed LDO. The small signal loop gain at low
frequency can be given as bellow
op _ amp MP G = A × A
Where
sg s g out op _ amp V =V −V =V −V
_ 7 9 7 9 7 7 3 1 5 3 1 5 3 3 [( (1 )) / / ] [( / / ) ( / / ) (1 )] outop amp ds ds ds ds m ds ds ds ds ds ds m R = r +r +r r g −h r + r r +r r r g +h
4. International Journal of Embedded Systems and Applications (IJESA) Vol.4, No.2/3, September 2014
4
And
_ m1 7 9 7 9 7 7 3 1 5 3 1 5 3 3 = g [( (1 )) / / ] [( / / ) ( / / ) (1 )] op amp ds ds ds ds m ds ds ds A r +r +r r g −h r + r r +rds rds rds gm +h
( ) 1
= +
1 2
+
1 2
1 / / MP MP
dsP
R
A g R R
g R R
The dominant and non-dominant poles of the feedback loop can be given as
( ) ( ) 1 gsMP gdp8 gdp10 gdn4 gdn6 C = C + C + C // C + C
2 gdMP _ _ C = C + Cc out op amp +C
3 Load C = C
1
1
2 C C + out op amp c out op amp
_ _ gdMP _ _
f
p R C
=
+
2
1 2
1
2 ( ( / /( )) mMP dsMP L
f
p g r R R C
=
+
0
1
2 ( ) ESR L
Z
p R C
=
2.2.1. Error Amplifier
The folded cascode operational amplifier (error amplifier) (EA) itself should provide very low
power dissipation (especially in stand-by mode), and its bias currents must be kept as low as
possible. It is apparent that a speed/dissipation trade-off arises, and the main limitation is
manifested in terms of slew-rate of the error amplifier.
As an example, if the EA can deliver to a 5-pF power-MOS gate no more than 2μA of current,
producing a 1.54 -V step will take 2ps of slewing interval. This allows improvement to the
transient response without increasing the DC consumption.
Considering that during this time the control loop of the LDO is interrupted and that the output
voltage is out of control, it is apparent that such a long slewing period may negatively impact on
the LDO performance, especially in terms of output voltage overshoots which may become
unacceptable for many applications.
2.2.2. Band-Gap
A CMOS band-gap reference circuit shown in Fig. 2 operates in a current-mode. A temperature
independent current is first generated by summing the proportional to absolute temperature
(PTAT) current IR7 and the complementary to absolute temperature (CTAT) current IR6.
Assuming M32, M33 and M34 have the same size [4],[5], the proposed band-gap reference uses
the Simple current mirror to decrease the surface layout of the Band-gap.
I = I1 +I2
5. International Journal of Embedded Systems and Applications (IJESA) Vol.4, No.2/3, September 2014
5
And yet
V+ = VA = R5 I1 + Vbe1
V- = VB = Vbe1= R6 I2
Then
V+ V- Else R5 I1 + Vbe1 = Vbe2
So he said to
− D
be be be V V V
2 1
1
= =
2 2
I
R R
DVbe =Vt ln(n)
1
ln( ) t V n
5
I
R
=
2
2
be V
6
I
R
=
ln( ) t be
Then 2
= +
4
5 6
REF
V n V
V R
R R
3. SIMULATED AND EXPERIMENTAL RESULTS
The LDO Circuit has been implemented in 0.18-μm CMOS technology. This work is improved
by the use of CMOs capacity (CT) so the advantage of reducing the area in the Layout is
shown in (Fig. 3) in which the effective die area is 10.853x10-3 mm2
Fig. 3. Layout of this work (LDO).
6. International Journal of Embedded Systems and Applications (IJESA) Vol.4, No.2/3, September 2014
For testing the LDO and external current mirror was used, and its output impedance is heavily
dependent of the amount of current. The LDO regulator is tested for R1 =0.5 k, R2 = 1.5 k
,VDD = 1.8 V, VREF = 1.2 V and multilayer ceramic output CMOS capacitor 500 pF with
several bypass CMOS capacitors in the f F range placed in parallel to reduce high-frequency
noise. The dc output voltage of the regulator is 1.54V. The ground current consumed by the LDO
regulator is 52 μA.
6
3.1. Gain , Phase And Stability Considerations
From the simulation results in Fig.4, the proposed LDO regulator is stable for load current values
ranging from 0 to 50 mA with a gain of the pass band is 85 dB. The phase margin is better than
60° for all cases then the LDO with the compensation is stable showing that the phase margin is
good enough.
Fig. 4 : Frequency response of the proposed LOO
3.2. Static-State Regulation Characteristics
The current mass is the sum of all currents polarization including in the regulator: the current
feedback, the current error amplifier and the drive current of the power transistor [2], [7].The
current mass is 52μA. The simulation results of different corners are as follows: The
characteristic of input voltage (Vin) and the output voltage (Vout) for our LDO voltage regulator
shown in Fig. 5. The drop-out voltage is 260 mV. The DC line regulation is 0.642%. The output
voltage of the proposed LDO voltage regulator with the load current swept from 100μA to 50mA
is given in Fig.6 the load regulation is 0.18x10-3 mV/mA. The current efficiency is 99.8% and
the power efficiency is 86%. The figure of merit (FOM) is 2.8ps.
7. International Journal of Embedded Systems and Applications (IJESA) Vol.4, No.2/3, September 2014
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Fig. 5. The DC sweep of the LDO
Fig. 6. DC Load regulation of the LDO.
t
Fig.7. Transient output voltage of the LDO regulator.
8. International Journal of Embedded Systems and Applications (IJESA) Vol.4, No.2/3, September 2014
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Fig.8. Simulated Temperature Variation of the proposed bandgap reference
circuit shown in Fig2.
The simulation results of the transient response shown in Fig.8. The transient response increases
further with different voltage input VIN from 2 V to 1.8 V and increasing the capacity CL, if t
= 2ps so he said to fast transient response [2],[3], [8]. Fig. 9 shows the simulated temperature
variation of the generated bias voltage 1.2 V that has a 30 mV variation in a temperature range of
-40°C to 80 °C .
4. CONCLUSIONS
LDO dropout is minimized to guarantee high power supply rejection at optimized efficiency. In
the meanwhile, current efficiency is enhanced up to 99.8 % because of low quiescent current
operation. The design procedure for obtaining the proper accuracy in the DC response low
quiescent current and fast transient output for to integrate with other circuit, involving a high
result of the figure of merit equal 2ps. Table I provides a performance comparison between this
work and recently published designs.
10. International Journal of Embedded Systems and Applications (IJESA) Vol.4, No.2/3, September 2014
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AUTHORS
Hicham Akhamal was born in Fez, Morocco in 1978. He received B.S. and
M.S. degrees in Faculty of Sciences from Sidi Mouhamed Ben Abdellah
University in2009 and 20011, respectively. Since 20011, he has been working
toward a Ph. Ddegree at the same university. His current research interests
include design of regulator LDO boost up gain and fast response ,
power-management integrated-circuit designs for telecommunication
applications, and G -C filter designs for biomedical applications.
Mostafa Chakir was born in Taounate, Morocco in 1986. He received
B.S. and M.S. degrees in Faculty of Sciences from Sidi Mouhamed Ben
Abdellah University in 2009 and 2011, respectively. Since 2011, he has been
working toward a Ph. D degree at the same university. His current interests are
in high speed mixed-signal integrated circuit designs, including active filters,
A/D andD/A converters.
Hassan Qjidaa received his M.S. and PhD in Applied Physics from Claude
Bernard University of Lyon France in 1983 and 1987 respectively. He got the
Pr.Degree in Faculty of Sciences from Sidi Mohammed Ben Abdellah
University, Fez, Morocco 1999. He is now an Professor in the Dept. of Physics
in Sidi Research interests include Very-large-scale integration (VLSI) solution,
Image Manuscripts Recognition,Cognitive Science, Image Processing,Computer
Graphics, Pattern Recognition, Neural Networks, Human machine Interface,
Artificial Intelligence and Robotics.