The scalability, modularity and massive parallelism exhibited by Network on chip(NoC) interconnects
make them highly suitable for the inter core communication framework of multiprocessor system-on-chip
(MPSoC) designs. Routers play the most vital role in transferring flits through the network, hence efficient
microarchitecture and cost effective routing algorithms are highly essential for modern NoC routers.
Elimination of buffers and deflection routing help to achieve energy and area efficiency of these routers.
The advantages of bufferless and buffered designs can be combined by using a minimum number of side
buffers to store a fraction of deflection flits in the router. In this paper, we propose a routing algorithm
based on weighted deflection of flits for minimally buffered deflection routers. Evaluations on 4x4 and 8x8
mesh NoC using synthetic workloads as well as benchmark applications demonstrate that deflection rate
and average network latency are significantly reduced in comparison with the state of the art NoC routers.
Performance analysis of the newly proposed algorithm shows that the network saturation point improves
by 26% compared to earlier designs in this domain
Network on Chip Architecture and Routing Techniques: A surveyIJRES Journal
The processor designing and development was designed to perform various complex logical information exchange and processing operations in a variety of resolutions. They mainly rely on concurrent and sync, both that of the software and hardware to enhance the productivity and performance. With the high speed growth approaching multi-billion transistor integration era, some of the main problems which are symbolized by all gate lengths in the range of 60-90 nm, will be from non-scalable delays generated by wire. All similar problems may be solved by using Network on Chip (NOC) systems. In the presented paper, we have summarized research papers and contributions in NOC area. With advancement in the technology in the on chip communication, faster interaction between devices is becoming vital. Network on Chip (NOC) can be one of the solutions for faster on chip communication. For efficient link between devices of NOC, routers are needed. This paper also reviews implementation of routing techniques. The use of routing gives higher throughput as required for dealing with complexity of modern systems. It is mainly focused on the routing design parameters on both system level including traffic pattern, network topology and routing algorithm, and architecture level including arbitration algorithm.
PERFORMANCE STUDIES ON THE VARIOUS ROUTING PROTOCOLS IN AD-HOC NETWORKSJYoTHiSH o.s
Every protocol has its advantages and disadvantages in different scenarios. The choice of a routing protocol should be made carefully after considering every aspect we provided in this section (and possibly more).
Network on Chip Architecture and Routing Techniques: A surveyIJRES Journal
The processor designing and development was designed to perform various complex logical information exchange and processing operations in a variety of resolutions. They mainly rely on concurrent and sync, both that of the software and hardware to enhance the productivity and performance. With the high speed growth approaching multi-billion transistor integration era, some of the main problems which are symbolized by all gate lengths in the range of 60-90 nm, will be from non-scalable delays generated by wire. All similar problems may be solved by using Network on Chip (NOC) systems. In the presented paper, we have summarized research papers and contributions in NOC area. With advancement in the technology in the on chip communication, faster interaction between devices is becoming vital. Network on Chip (NOC) can be one of the solutions for faster on chip communication. For efficient link between devices of NOC, routers are needed. This paper also reviews implementation of routing techniques. The use of routing gives higher throughput as required for dealing with complexity of modern systems. It is mainly focused on the routing design parameters on both system level including traffic pattern, network topology and routing algorithm, and architecture level including arbitration algorithm.
PERFORMANCE STUDIES ON THE VARIOUS ROUTING PROTOCOLS IN AD-HOC NETWORKSJYoTHiSH o.s
Every protocol has its advantages and disadvantages in different scenarios. The choice of a routing protocol should be made carefully after considering every aspect we provided in this section (and possibly more).
This compare and evaluate two routing protocols DSR and CBRP in ad hoc networks. DSR is based on flat topology and CBRP is of cluster based. Both are compared in different number of scenarios and their performances are compared in terms of pdf, channel utilization, nrl, average end to end delay and control overheads.
International Journal of Computational Engineering Research(IJCER)ijceronline
International Journal of Computational Engineering Research(IJCER) is an intentional online Journal in English monthly publishing journal. This Journal publish original research work that contributes significantly to further the scientific knowledge in engineering and Technology.
RRSTP: A Spanning Tree Protocol for Obviating Count-to-Infinity from Switched...CSCJournals
This paper will presents a highly reliable and rapidly converging spanning tree protocol named as Reliable Rapid Spanning Tree Protocol. The need of this spanning tree protocol is felt because reliability of switched Ethernet networks is heavily dependent upon that of spanning tree protocol. But current standard spanning tree protocol – Rapid Spanning Tree Protocol – is well known for its susceptibility to classical count-to-infinity problem. Because of this problem the protocol has extremely variable and unexpectedly high convergence time even in small networks. As a result network wide congestion, frame loss and frame delay may occur. Even forwarding loops may be induced into the network under certain circumstances. It is expected that the new protocol – RRSTP – will significantly increase the dependability of switched Ethernet networks by providing guaranteed protection against the count-to-infinity problem.
PERFORMANCE ANALYSIS OF OLSR PROTOCOL IN MANET CONSIDERING DIFFERENT MOBILITY...ijwmn
A Mobile Ad Hoc Network (MANET) is created when an independent mobile node network is connected
dynamically via wireless links. MANET is a self-organizing network that does not rely on pre-existing
infrastructure such as wired or wireless network routers. Mobile nodes in this network move randomly,
thus, the topology is always changing. Routing protocols in MANET are critical in ensuring dependable
and consistent connectivity between the mobile nodes. They conclude logically based on the interaction
between mobile nodes in MANET routing and encourage them to choose the optimum path between source
and destination. Routing protocols are classified as proactive, reactive, or hybrid. The focus of this project
will be on Optimized Link State Routing (OLSR) protocol, a proactive routing technique. OLSR is known as
the optimized variant of link state routing in which packets are sent throughout the network using the
multipoint relay (MPR) mechanism. This article evaluates the performance of the OLSR routing protocol
under condition of changing mobility speed and network density. The study's performance indicators are
average packet throughput, packet delivery ratio (PDR), and average packet latency. Network Simulator 2
(NS-2) and an external patch UM-OLSR are used to simulate and evaluate the performance of such
protocol. As a result of research, the approach of implementing the MPR mechanism are able to minimise
redundant data transmission during the normal message broadcast. The MPRs enhance the link state
protocols’ traditional diffusion mechanism by selecting the right MPRs. Hence, the number of undesired
broadcasts can be reduced and limited. Further research will focus on different scenario and environment
using different mobility model
Arteris network on chip: The growing cost of wiresArteris
Arteris NoC SoC Interconnect presentation given by Jonah Probell at ARM Technology Conference 9-11 Nov 2010. Explains how traditional AXI fabrics require huge numbers of wires and leads to routing congestion, and how network on chip interconnects address routing congestion by allowing fewer wires. Explains the basics of NoC packetization and serialization.
For further details contact:
N.RAJASEKARAN B.E M.S 9841091117,9840103301.
IMPULSE TECHNOLOGIES,
Old No 251, New No 304,
2nd Floor,
Arcot road ,
Vadapalani ,
Chennai-26.
BETTER SCALABLE ROUTING PROTOCOL FOR HYBRID WIRELESS MESH NETWORKcscpconf
There are many routing approaches have been borrowed from mobile ad hoc network to achieve routing solutions in wireless mesh network. WMN was developed for reliable data communication and load balancing. AODV provides loop-free routes even while repairing broken links. This paper have been proposed an improved hierarchical AODV routing protocol
(IH-AODV), which exhibits better scalability and performance in the network. This IH-AODV protocol has been proposed for improvement in the scaling potential of AODV. MAODV allows
each node in the network to send out multicast data packets, used for multicast traffic. The wireless mesh network architecture provides reduction in installation cost, large scale
deployment, reliability and self management. It is mainly focused on implementing military or specialized civilian applications. Two protocols MAODV and IH-AODV were simulated using NS2 package. Simulation results will demonstrate that, IH-AODV scales well for large network
and other metrics are also better than or comparable to MAODV in hybrid WMNs.
Impact of parameter variations and optimization on dg pnin tunnel fetVLSICS Design
The downscaling of conventional MOSFETs has come to its fundamental limits. TFETs are very attractive
devices for low power applications because of their low off-current and potential for smaller sub threshold
slope. In this paper, the impact of various parameter variations on the performance of a DG-PNIN Tunnel
field effect transistor is investigated. In this work, variations in gate oxide material, source doping, channel
doping, drain doping, pocket doping and body thickness are studied and all these parameters are optimized
as performance boosters to give better current characteristics parameters. After optimization with all these
performance boosters, the device has shown improved performance with increased on-current and reduced
threshold voltage and the Ion/Ioff ratio is > 106.
Vlsics040303LOW POWER DUAL EDGE - TRIGGERED STATIC D FLIP-FLOPVLSICS Design
This paper enumerates new architecture of low power dual-edge triggered Flip-Flop (DETFF) designed at
180nm CMOS technology. In DETFF same data throughput can be achieved with half of the clock
frequency as compared to single edge triggered Flip-Flop (SETFF). In this paper conventional and
proposed DETFF are presented and compared at same simulation conditions. The post layout experimental
results comparison shows that the average power dissipation is improved by 48.17%, 41.29% and 36.84%
when compared with SCDFF, DEPFF and SEDNIFF respectively and improvement in PDP is 42.44%,
33.88% and 24.69% as compared to SCDFF, DEPFF and SEDNIFF respectively. Therefore the proposed
DETFF design is suitable for low power and small area applications
This compare and evaluate two routing protocols DSR and CBRP in ad hoc networks. DSR is based on flat topology and CBRP is of cluster based. Both are compared in different number of scenarios and their performances are compared in terms of pdf, channel utilization, nrl, average end to end delay and control overheads.
International Journal of Computational Engineering Research(IJCER)ijceronline
International Journal of Computational Engineering Research(IJCER) is an intentional online Journal in English monthly publishing journal. This Journal publish original research work that contributes significantly to further the scientific knowledge in engineering and Technology.
RRSTP: A Spanning Tree Protocol for Obviating Count-to-Infinity from Switched...CSCJournals
This paper will presents a highly reliable and rapidly converging spanning tree protocol named as Reliable Rapid Spanning Tree Protocol. The need of this spanning tree protocol is felt because reliability of switched Ethernet networks is heavily dependent upon that of spanning tree protocol. But current standard spanning tree protocol – Rapid Spanning Tree Protocol – is well known for its susceptibility to classical count-to-infinity problem. Because of this problem the protocol has extremely variable and unexpectedly high convergence time even in small networks. As a result network wide congestion, frame loss and frame delay may occur. Even forwarding loops may be induced into the network under certain circumstances. It is expected that the new protocol – RRSTP – will significantly increase the dependability of switched Ethernet networks by providing guaranteed protection against the count-to-infinity problem.
PERFORMANCE ANALYSIS OF OLSR PROTOCOL IN MANET CONSIDERING DIFFERENT MOBILITY...ijwmn
A Mobile Ad Hoc Network (MANET) is created when an independent mobile node network is connected
dynamically via wireless links. MANET is a self-organizing network that does not rely on pre-existing
infrastructure such as wired or wireless network routers. Mobile nodes in this network move randomly,
thus, the topology is always changing. Routing protocols in MANET are critical in ensuring dependable
and consistent connectivity between the mobile nodes. They conclude logically based on the interaction
between mobile nodes in MANET routing and encourage them to choose the optimum path between source
and destination. Routing protocols are classified as proactive, reactive, or hybrid. The focus of this project
will be on Optimized Link State Routing (OLSR) protocol, a proactive routing technique. OLSR is known as
the optimized variant of link state routing in which packets are sent throughout the network using the
multipoint relay (MPR) mechanism. This article evaluates the performance of the OLSR routing protocol
under condition of changing mobility speed and network density. The study's performance indicators are
average packet throughput, packet delivery ratio (PDR), and average packet latency. Network Simulator 2
(NS-2) and an external patch UM-OLSR are used to simulate and evaluate the performance of such
protocol. As a result of research, the approach of implementing the MPR mechanism are able to minimise
redundant data transmission during the normal message broadcast. The MPRs enhance the link state
protocols’ traditional diffusion mechanism by selecting the right MPRs. Hence, the number of undesired
broadcasts can be reduced and limited. Further research will focus on different scenario and environment
using different mobility model
Arteris network on chip: The growing cost of wiresArteris
Arteris NoC SoC Interconnect presentation given by Jonah Probell at ARM Technology Conference 9-11 Nov 2010. Explains how traditional AXI fabrics require huge numbers of wires and leads to routing congestion, and how network on chip interconnects address routing congestion by allowing fewer wires. Explains the basics of NoC packetization and serialization.
For further details contact:
N.RAJASEKARAN B.E M.S 9841091117,9840103301.
IMPULSE TECHNOLOGIES,
Old No 251, New No 304,
2nd Floor,
Arcot road ,
Vadapalani ,
Chennai-26.
BETTER SCALABLE ROUTING PROTOCOL FOR HYBRID WIRELESS MESH NETWORKcscpconf
There are many routing approaches have been borrowed from mobile ad hoc network to achieve routing solutions in wireless mesh network. WMN was developed for reliable data communication and load balancing. AODV provides loop-free routes even while repairing broken links. This paper have been proposed an improved hierarchical AODV routing protocol
(IH-AODV), which exhibits better scalability and performance in the network. This IH-AODV protocol has been proposed for improvement in the scaling potential of AODV. MAODV allows
each node in the network to send out multicast data packets, used for multicast traffic. The wireless mesh network architecture provides reduction in installation cost, large scale
deployment, reliability and self management. It is mainly focused on implementing military or specialized civilian applications. Two protocols MAODV and IH-AODV were simulated using NS2 package. Simulation results will demonstrate that, IH-AODV scales well for large network
and other metrics are also better than or comparable to MAODV in hybrid WMNs.
Impact of parameter variations and optimization on dg pnin tunnel fetVLSICS Design
The downscaling of conventional MOSFETs has come to its fundamental limits. TFETs are very attractive
devices for low power applications because of their low off-current and potential for smaller sub threshold
slope. In this paper, the impact of various parameter variations on the performance of a DG-PNIN Tunnel
field effect transistor is investigated. In this work, variations in gate oxide material, source doping, channel
doping, drain doping, pocket doping and body thickness are studied and all these parameters are optimized
as performance boosters to give better current characteristics parameters. After optimization with all these
performance boosters, the device has shown improved performance with increased on-current and reduced
threshold voltage and the Ion/Ioff ratio is > 106.
Vlsics040303LOW POWER DUAL EDGE - TRIGGERED STATIC D FLIP-FLOPVLSICS Design
This paper enumerates new architecture of low power dual-edge triggered Flip-Flop (DETFF) designed at
180nm CMOS technology. In DETFF same data throughput can be achieved with half of the clock
frequency as compared to single edge triggered Flip-Flop (SETFF). In this paper conventional and
proposed DETFF are presented and compared at same simulation conditions. The post layout experimental
results comparison shows that the average power dissipation is improved by 48.17%, 41.29% and 36.84%
when compared with SCDFF, DEPFF and SEDNIFF respectively and improvement in PDP is 42.44%,
33.88% and 24.69% as compared to SCDFF, DEPFF and SEDNIFF respectively. Therefore the proposed
DETFF design is suitable for low power and small area applications
Multisim design and simulation of 2.2 g hz lna for wireless communicationVLSICS Design
This paper presents the work done on the design and simulation of a high frequency low noise amplifier for
wireless communication. The purpose of the amplifier is to amplify the received RF path of a wireless
network. With high gain, high sensitivity and low noise using Bipolar Junction transistor (BJT). The design
methodology requires analysis of the transistor for stability, proper matching, network selection and
fabrication. The BJT transistor was chosen for the design of the LNA due to its low noise and good gain at
high frequency. These properties were confirmed using some measurement techniques including Network
Analyzer, frequency analyzer Probe and Oscilloscope for the simulation and practical testing of the
amplifier to verify the performance of the designed High frequency Low noise amplifier. The design goals
of noise figure of 0.52dB-0.7dB and bias conditions are Vcc = 3.5 V and Icc= 55 mA to produce 16.8 dB
gain across the 0.4–2.2GHz band.
Evolution of Structure of Some Binary Group-Based N-Bit Compartor, N-To-2N De...VLSICS Design
Reversible logic has attracted substantial interest due to its low power consumption which is the main
concern of low power VLSI systems. In this paper, a novel 4x4 reversible gate called inventive gate has
been introduced and using this gate 1-bit, 2-bit, 8-bit, 32-bit and n-bit group-based reversible comparator
have been constructed with low value of reversible parameters. The MOS transistor realizations of 1-bit, 2-
bit, and 8-bit of reversible comparator are also presented and finding power, delay and power delay
product (PDP) with appropriate aspect ratio W/L. Novel inventive gate has the ability to use as an n-to-2n
decoder. Different novel reversible circuit design style is compared with the existing ones. The relative
results shows that the novel reversible gate wide utility, group-based reversible comparator outperforms
the present style in terms of number of gates, garbage outputs and constant input.
A RAIL-TO-RAIL HIGH SPEED CLASS-AB CMOS BUFFER WITH LOW POWER AND ENHANCED SL...VLSICS Design
A rail-to-rail class-AB CMOS buffer is proposed in this paper to drive large capacitive loads. A new
technique is used to reduce the leakage power of class-AB CMOS buffer circuits without affecting dynamic
power dissipation .The name of applied technique is LECTOR, which gives the high speed buffer with the
reduced low power dissipation (1.05%) and reduced area (2.8%). The proposed buffer is simulated at
45nm CMOS technology and the circuit is operated at 3V supply with cadence software. This analog circuit
is performed with extremely low leakage current as well as high current driving capability for the large
input voltages. The proposed paper is achieved very high speed with very low propagation delay range
i.e.(292×10-12). So the delay of the circuit is reduced to 10%. The settling time of this circuit is reduced by
24% (in ns) at 3V square wave input. The measured quiescent current is 41μA
FGMOS BASED LOW-VOLTAGE LOW-POWER HIGH OUTPUT IMPEDANCE REGULATED CASCODE CUR...VLSICS Design
Floating Gate MOS (FGMOS) transistors can be very well implemented in lieu of conventional MOSFET
for design of a low-voltage, low-power current mirror. Incredible features of flexibility, controllability and
tunability of FGMOS yields better results with respect to power, supply voltage and output swing. This
paper presents a new current mirror designed with FGMOS which exhibit high output impedance, higher
current range, very low power dissipation and higher matching accuracy. It achieves current range of up to
1500 µA, high output impedance of 1.125 TΩ, bandwidth of 4.1 MHz and dissipates power as low as 10.56
µW. The proposed design has been simulated using Cadence Design Environment in 180 nm CMOS
process technology with +1.0 Volt single power supply
DESIGN OF IMPROVED RESISTOR LESS 45NM SWITCHED INVERTER SCHEME (SIS) ANALOG T...VLSICS Design
This work presents three different approaches which eliminates the resistor ladder completely and hence
reduce the power demand drastically of a Analog to Digital Converter. The first approach is Switched
Inverter Scheme (SIS) ADC; The test result obtained for it on 45nm technology indicates an offset error of
0.014 LSB. The full scale error is of -0.112LSB. The gain error is of 0.07 LSB, actual full scale range of
0.49V, worst case DNL & INL each of -0.3V. The power dissipation for the SIS ADC is 207.987 μwatts;
Power delay product (PDP) is 415.9 fWs, and the area is 1.89μm2. The second and third approaches are
clocked SIS ADC and Sleep transistor SIS ADC. Both of them show significant improvement in power
dissipation as 57.5% & 71% respectively. Whereas PDP is 229.7 fWs and area is 0.05 μm2 for Clocked SIS
ADC and 107.3 fWs & 1.94 μm2 for Sleep transistor SIS ADC.
SINGLE-PORT FIVE-TRANSISTOR SRAM CELL WITH REDUCED LEAKAGE CURRENT IN STANDBYVLSICS Design
In this paper, a new single-port five-transistor (5T) Static Random Access Memory (SRAM) cell with
integrated read/write assist is proposed. Amongst the assist circuitry, a voltage control circuit is coupled to
the sources corresponding to driver transistors of each row memory cells. This configuration is aimed to
control the source voltages of driver transistors under different operating modes. Specifically, during a
write operation, by means of sizing the driver transistor close to bitline to resolve the write ‘1’ issue. In
addition, associated with a two-stage reading mechanism to increase the reading speed and to avoid
unnecessary power consumption. Finally, with the standby start-up cir
Designing High-Speed, Low-Power Full Adder Cells Based on Carbon Nanotube Tec...VLSICS Design
This article presents novel high speed and low power full adder cells based on carbon nanotube field effect
transistor (CNFET). Four full adder cells are proposed in this article. First one (named CN9P4G) and
second one (CN9P8GBUFF) utilizes 13 and 17 CNFETs respectively. Third design that we named
CN10PFS uses only 10 transistors and is full swing. Finally, CN8P10G uses 18 transistors and divided into
two modules, causing Sum and Cout signals are produced in a parallel manner. All inputs have been used
straight, without inverting. These designs also used the special feature of CNFET that is controlling the
threshold voltage by adjusting the diameters of CNFETs to achieve the best performance and right voltage
levels. All simulation performed using Synopsys HSPICE software and the proposed designs are compared
to other classical and modern CMOS and CNFET-based full adder cells in terms of delay, power
consumption and power delay product.
A Sub Threshold Source Coupled Logic Based Design of Low Power CMOS Analog Mu...VLSICS Design
A novel approach for designing Ultra Low Power and wide dynamic range circuit for multiplexing analog
signals is presented. The design operates in weak inversion (Sub threshold) region and uses Source -
Coupled Logic ( SCL) circuit. The bias current of the SCL gates is varied to scale down linearly the power
consumption and the operating frequency. The multiplexer design employs CMOS transistors as
transmission gate with dynamic threshold voltage. The design exhibits low power dissipation, high
dynamic range and good linearity. The design was implemented in 180 nm technology and was operated at
a supply voltage of 400 mV with a bias current ranging in the order of few Pico-amperes. The ON and
OFF resistance of the transmission gate achieved were 27 ohms and 10 M ohms respectively. The power
dissipation achieved is around 0.79 μW for a dynamic range of 1μV to 0.4 V.
Optimal Unate Decomposition Method for Synthesis of Mixed CMOS VLSI CircuitsVLSICS Design
Static CMOS logic style is often the choice of designers for synthesizing low power circuits. This style is
robust in terms of noise integrity however, it offers less speed. Domino logic style, as an alternative is often
found in critical paths of various large scale high performance circuits. Yet, due to high switching activity
they are not suitable for synthesis of low power circuits. To achieve both power and speed benefits, we
propose a method of designing circuit using mixed CMOS logic style, taking advantages of both static and
Domino logic styles. For a given circuit, we extract the unate and binate components using a unate
decomposition algorithm. These are optimized such that the resulting circuit is optimum in terms of power,
area and delay. To do this, a multi-objective genetic algorithm is employed. The optimized unate and binate
blocks are mapped using Domino and static cell libraries, respectively. Testing the efficacy of our
approach with ISCAS85 and MCNC89 benchmark circuits showed an improvement of 25% in delay and
22% in transistor count with 12% more power dissipation compared to circuits with only static CMOS
logic. Thus, mixed CMOS circuits are promising in high speed and area constraint applications.
Design of low power cmos logic circuits using gate diffusion input (gdi) tech...VLSICS Design
The Gate diffusion input (GDI) is a novel technique
for low power digital circuit design. This techniq
ue
reduces the power dissipation, propagation delay, a
rea of digital circuits and it maintains low comple
xity
of logic design. In this paper, the 4×1 Multiplexer
, 8×3 Encoder, BCD Counter and Mealy State Machine
were implemented by using Pass Transistors (PT), Tr
ansmission Gate (TG) and Gate Diffusion Input (GDI)
technique and then they were compared with each oth
er for power dissipation. The Multiplexers and
Encoders are combinational circuits and Counters an
d mealy machines are sequential circuits both of th
em
are very important digital systems so power optimiz
ation should be done to those digital circuits. The
whole processes for development of digital circuits
and simulation was done by using the mentor graphi
cs
backend tool. This method can also be extended to t
he processors and other high level designs for
optimization of power dissipation, area and delay i
n order to increase the circuit efficiency.
LEAKAGE REDUCTION TECHNIQUE AND ANALYSIS OF CMOS D FLIP FLOPVLSICS Design
The expansion of battery operated portable device is continuously increasing the demand for low
power, minimum delay and high speed integrated circuits. In many of the portable devices the
standby periods are longer than the active periods and thus consume more power in the standby
state [2]. It is extremely important to reduce the power consumption in the standby mode. In
today’s high performance integrated circuits the leakage power contributes major power
consumption than overall total power consumption. In deep submicron circuits the leakage
power increases than the dynamic power and also in the circuits when there are no transitions at
the input and the transistors are in steady state [1]. Leakage power is mainly due to leakage
current that flows in the circuit when the circuit is operated in sleep or standby mode. The
leakage current is composed of sub-threshold leakage current, gate current, gate leakage current
and reverses biased leakage. Among all leakages, sub-threshold leakage contributes major part of
the leakage. The sub-threshold leakage current of a metal oxide semiconductor device is
expressed as
Where µo is the mobility of electrons/holes, Cox denotes oxide
capacitance of gate per unit area, W and L are width and channel length of MOS device
respectively, Vgs is the gate to source voltage Vt is the thermal voltage and η is the swing
coefficient. The contents of this paper are organized as follows: Section 2 descr
DESIGN OF A PROGRAMMABLE LOW POWER LOW DROP-OUT REGULATORVLSICS Design
A low power programmable low drop-out regulator capable of providing 1V output has been proposed. The
regulator requires a supply voltage of 1.2V and works in the temperature range of -40 to 125 °C in nominal
corner (i.e, normal doping for PMOS and NMOS Field Effect Transistors), yielding a load regulation of
3%. The output voltage level is controlled externally by means of 2 1-bit control signals. The circuit
provides a DC gain of 30 dB and a maximum DC Power Supply Rejection Ratio of -35 dB and a worst case
PSRR of -20 dB. Power dissipation in the load is nearly 100 μW
SMART MULTICROSSBAR ROUTER DESIGN IN NOCVLSICS Design
This paper gives the innovative idea of designing a router using multicrossbar switch in Network on
Chip(NoC) . In Network-on-Chip architectures the input buffer can consume a large portion of the total
power. Eliminating all input buffer would result in increased power consumption at high load, while
reducing the size of input buffer degrades the performance. In this paper we have proposed a muticrossbar
router design using elastic buffer by combining the advantage of both buffered and buffer less network. In
the proposed design Power Delay Product is reduced by around 37 .91% as compared to baseline router
Performance Improved Network on Chip Router for Low Power ApplicationsIJTET Journal
Abstract— On chip routers typically have buffers dedicated to their input or output ports for temporarily storing packets in case contention occurs. Buffers consume significant portions of router area. While running a traffic trace, however not all input ports of routers have incoming packets needed to be transferred simultaneously. So large numbers of buffer queues in the network are empty and other queues are mostly busy. This observation motivates us to design Router architecture with Shared Queues (RoShaQ), router architecture that maximizes buffer utilization by allowing the sharing multiple buffer queues among input ports. In the network design of the NoC the most essential things are a network topology and a routing algorithm. Routers route the packets based on the algorithm that they use. Every system has its own requirements for the routing algorithm. A new adaptive weighted XY routing algorithm for eight port router Architecture is proposed in order to decrease the latency of the network on chip router.
Mobile ad hoc network is a reconfigurable network of mobile nodes connected by multi-hop wireless links and capable of operating without any fixed infrastructure support. In order to facilitate communication within such self-creating, self-organizing and self administrating network, a dynamic routing protocol is needed. The primary goal of such an ad hoc network routing protocol is to discover and establish a correct and efficient route between a pair of nodes so that messages may be delivered in a timely manner. Route construction should be done with a minimum of overhead and bandwidth consumption. This paper examines two routing protocols, both on-demand source routing, for mobile ad hoc networks– the Dynamic Source Routing (DSR), an flat architecture based and the Cluster Based Routing Protocol (CBRP), a cluster architecture based and evaluates both routing protocols in terms of packet delivery fraction, normalized routing load, average end to end delay, throughput by varying number of nodes per sq. km, traffic sources and mobility. Simulation results show that in high
mobility (pause time 0s) scenarios, CBRP outperforms DSR. CBRP scales well with increasing number of nodes.
IRJET-A_AODV: A Modern Routing Algorithm for Mobile Ad-Hoc NetworkIRJET Journal
Ritu Parasher, Yogesh Rathi "A_AODV: A Modern Routing Algorithm for Mobile Ad-Hoc Network", International Research Journal of Engineering and Technology (IRJET), Volume2,issue-01 April 2015.e-ISSN:2395-0056, p-ISSN:2395-0072. www.irjet.net .published by Fast Track Publications
Abstract
Mobile ad-hoc network (MANET) is an autonomous wireless network, deploy without any fixed infrastructure and assistance of base stations. Each node in network shares wireless link for interconnections and not only operates as an end system, but also as a router to forward packets. Since the network nodes are mobile, can be move in any direction with varying paces that generate high dynamicity of network so the protocols that are developed for general ad hoc networks are unsuitable for such an environment. In addition, on-hand routing protocols performance decreases as size of network increased. In this context, to enhance the recitation of routing in MANETs, we propose a new approach in this paper, named Advanced Ad hoc On-Demand Distance Vector (A_AODV). It is a modified version of traditional AODV routing protocol, shrink the active path whenever optimal pathway is available and switches the traffic on it. Simulation studies are conducted using NS2 to prove that proposed approach enhance network performance when network size, load or the mobility increases
A Network-on-chip (NOC) is a new paradigm in complex system-on-chip (SOC) designs that provide efficient on chip communication networks. The data is routed through the networks in terms of packets. The routing of data is mainly done by routers. So the architecture of router must be an efficient one with a lower latency and higher throughput. In this project we designed, implemented and analyzed crossbar router architectures for a network on chip communication in a FPGA. The routers have five ports, four ports connected to other ports in four different directions and the fifth port connected to the processing element through a network interface. Our Proposed architecture contains 4x4 crossbar switch, switch allocator, path and channel request, data ram and 4 i/o ports. The datas ere sent through the routers in order to prevent congestion. The swich allocator and VC allocator are used to allocate the datas in priority order. The switch allocator will allocate the datas according to the path and channel request. The XY algorithm with a scheduler is used in this project for proper destination of the datas.
A ULTRA-LOW POWER ROUTER DESIGN FOR NETWORK ON CHIPijaceeejournal
The design of more complex systems becomes an increasingly difficult task because of different issues
related to latency, design reuse, throughput and cost that has to be considered while designing. In
Real-time applications there are different communication needs among the cores. When NoCs (Networks
on chip) are the means to interconnect the cores, use of some techniques to optimize the
communication are indispensable. From the performance point of view, large buffer sizes ensure
performance during different applications execution. But unfortunately, these same buffers are the main
responsible for the router total power dissipation. Another aspect is that by sizing buffers for the worst case
latency incurs in extra dissipation for the mean case, which is much more frequent. Reconfigurable router
architecture for NOC is designed for processing elements communicate over a second
communication level using direct-links between another node elements. Several possibilities to use the
router as additional resources to enhance complexity of modules are presented. The reconfigurable router
is evaluated in terms of area, speed and latencies. The proposed router was described in VHDL and used
the ModelSim tool to simulate the code. Analyses the average power consumption, area, and frequency
results to a standard cell library using the Design Compiler tool. With the reconfigurable router it was
possible to reduce the congestion in the network, while at the same time reducing power dissipation and
improving energy.
Energy efficiency cross layer protocol for wireless mesh networkIJCNCJournal
Wireless mesh network (WMN) is a novel emerging tec
hnology that will change the world more effectively
and efficiently. It is regarded as a highly promisi
ng technology being increasingly important in mobil
e
wireless networks of the future generation. In this
paper, we consider energy management for wireless
mesh networks from a point of view that started rec
ently to attract the attention means the conservati
on of
energy for operational and the environment reasons
which is known as the Green Networking. This paper
discusses different routing protocols to establish
a protocol which considers energy efficiency. The e
xisting
protocols are compared using the basic functions of
routing and the suggest protocol is designed to
overcome some of their shortcomings. We are focusin
g on the conception of the cross-layer routing
protocol that is implemented in TDMA (Time Division
Multiple Access) wireless mesh networks based
MAC protocol.
Influence of Clustering on the Performance of MobileAd Hoc Networks (MANETs)Narendra Singh Yadav
Clustering is an important research area for mobile ad hoc networks (MANETs) as it increases the capacity of network, reduces the routing overhead and makes the network more scalable in the presence of both high mobility and a large number of mobile nodes. Routing protocols based on flat topology are not scalable because of their built-in characteristics. However, clustering cause overhead which consumes considerable bandwidth, drain mobile nodes energy quickly, likely cause congestion, collision and data delay in larger networks. This paper uses an implementation of the Dynamic Source Routing (DSR), an flat architecture based and the Cluster Based Routing Protocol (CBRP), a cluster architecture based routing protocol to examine the influence of clustering on the performance of mobile ad hoc networks. This paper evaluates channel utilization and control overhead as a function of number of nodes per sq. km to show the effect of clustering. Simulation results show that in high mobility scenarios, CBRP outperforms DSR. CBRP scales well with increasing number of nodes.
Optimized Design of 2D Mesh NOC Router using Custom SRAM & Common Buffer Util...VLSICS Design
With the shrinking technology, reduced scale and power-hungry chip IO leads to System on Chip. The design of SOC using traditional standard bus scheme encounters with issues like non-uniform delay and routing problems. Crossbars could scale better when compared to buses but tend to become huge with increasing number of nodes. NOC has become the design paradigm for SOC design for its highly regularized interconnect structure, good scalability and linear design effort. The main components of an NoC topology are the network adapters, routing nodes, and network interconnect links. This paper mainly deals with the implementation of full custom SRAM based arrays over D FF based register arrays in the design of input module of routing node in 2D mesh NOC topology. The custom SRAM blocks replace DFF(D flip flop) memory implementations to optimize area and power of the input block. Full custom design of SRAMs has been carried out by MILKYWAY, while physical implementation of the input module with SRAMs has been carried out by IC Compiler of SYNOPSYS.The improved design occupies approximately 30% of the area of the original design. This is in conformity to the ratio of the area of an SRAM cell to the area of a D flip flop, which is approximately 6:28.The power consumption is almost halved to 1.5 mW. Maximum operating frequency is improved from 50 MHz to 200 MHz. It is intended to study and quantify the behavior of the single packet array design in relation to the multiple packet array design. Intuitively, a
common packet buffer would result in better utilization of available buffer space. This in turn would translate into lower delays in transmission. A MATLAB model is used to show quantitatively how performance is improved in a common packet array design.
Optimized Design of 2D Mesh NOC Router using Custom SRAM & Common Buffer Util...VLSICS Design
With the shrinking technology, reduced scale and power-hungry chip IO leads to System on Chip. The design of SOC using traditional standard bus scheme encounters with issues like non-uniform delay and routing problems. Crossbars could scale better when compared to buses but tend to become huge with increasing number of nodes. NOC has become the design paradigm for SOC design for its highly regularized interconnect structure, good scalability and linear design effort. The main components of an NoC topology are the network adapters, routing nodes, and network interconnect links. This paper mainly deals with the implementation of full custom SRAM based arrays over D FF based register arrays in the design of input module of routing node in 2D mesh NOC topology. The custom SRAM blocks replace D FF(D flip flop) memory implementations to optimize area and power of the input block. Full custom design of SRAMs has been carried out by MILKYWAY, while physical implementation of the input module with SRAMs has been carried out by IC Compiler of SYNOPSYS.The improved design occupies approximately 30% of the area of the original design. This is in conformity to the ratio of the area of an SRAM cell to the area of a D flip flop, which is approximately 6:28.The power consumption is almost halved to 1.5 mW. Maximum operating frequency is improved from 50 MHz to 200 MHz. It is intended to study and quantify the behavior of the single packet array design in relation to the multiple packet array design. Intuitively, a
common packet buffer would result in better utilization of available buffer space. This in turn would translate into lower delays in transmission. A MATLAB model is used to show quantitatively how performance is improved in a common packet array design.
Congestion Control in Manets Using Hybrid Routing ProtocolIOSR Journals
Abstract : As the network size increases the probability of congestion occurrence at nodes increases. This is because of the event driven nature of ad hoc networks that leads to unpredictable network load. As a result congestion may occur at the nodes which receive more data than that can be forwarded and cause packet losses. In this paper we propose a hybrid scheme that attempts to avoid packet loss due to congestion as well as reduce end to end delay in delivering data packets by combining two protocols- Destination sequenced distance vector routing (DSDV), which is a table driven or proactive protocol and Improved Ad-hoc on demand vector routing (IAODV) which is an on-demand or reactive protocol that reduces packet loss due to congestion. The strategy adopted is use DSDV for path selection and if congestion occurs than switch over to IAODV. The routing performance of this model is then compared with IAODV and DSDV in terms of end to end delay, throughput and packet delivery fraction. Keywords- DSDV, Hybrid protocol, AODV, IAODV, MANET
Congestion Control in Manets Using Hybrid Routing ProtocolIOSR Journals
As the network size increases the probability of congestion occurrence at nodes increases. This is
because of the event driven nature of ad hoc networks that leads to unpredictable network load. As a result
congestion may occur at the nodes which receive more data than that can be forwarded and cause packet losses.
In this paper we propose a hybrid scheme that attempts to avoid packet loss due to congestion as well as reduce
end to end delay in delivering data packets by combining two protocols- Destination sequenced distance vector
routing (DSDV), which is a table driven or proactive protocol and Improved Ad-hoc on demand vector routing
(IAODV) which is an on-demand or reactive protocol that reduces packet loss due to congestion. The strategy
adopted is use DSDV for path selection and if congestion occurs than switch over to IAODV. The routing
performance of this model is then compared with IAODV and DSDV in terms of end to end delay, throughput
and packet delivery fraction
Student information management system project report ii.pdfKamal Acharya
Our project explains about the student management. This project mainly explains the various actions related to student details. This project shows some ease in adding, editing and deleting the student details. It also provides a less time consuming process for viewing, adding, editing and deleting the marks of the students.
Hybrid optimization of pumped hydro system and solar- Engr. Abdul-Azeez.pdffxintegritypublishin
Advancements in technology unveil a myriad of electrical and electronic breakthroughs geared towards efficiently harnessing limited resources to meet human energy demands. The optimization of hybrid solar PV panels and pumped hydro energy supply systems plays a pivotal role in utilizing natural resources effectively. This initiative not only benefits humanity but also fosters environmental sustainability. The study investigated the design optimization of these hybrid systems, focusing on understanding solar radiation patterns, identifying geographical influences on solar radiation, formulating a mathematical model for system optimization, and determining the optimal configuration of PV panels and pumped hydro storage. Through a comparative analysis approach and eight weeks of data collection, the study addressed key research questions related to solar radiation patterns and optimal system design. The findings highlighted regions with heightened solar radiation levels, showcasing substantial potential for power generation and emphasizing the system's efficiency. Optimizing system design significantly boosted power generation, promoted renewable energy utilization, and enhanced energy storage capacity. The study underscored the benefits of optimizing hybrid solar PV panels and pumped hydro energy supply systems for sustainable energy usage. Optimizing the design of solar PV panels and pumped hydro energy supply systems as examined across diverse climatic conditions in a developing country, not only enhances power generation but also improves the integration of renewable energy sources and boosts energy storage capacities, particularly beneficial for less economically prosperous regions. Additionally, the study provides valuable insights for advancing energy research in economically viable areas. Recommendations included conducting site-specific assessments, utilizing advanced modeling tools, implementing regular maintenance protocols, and enhancing communication among system components.
Hierarchical Digital Twin of a Naval Power SystemKerry Sado
A hierarchical digital twin of a Naval DC power system has been developed and experimentally verified. Similar to other state-of-the-art digital twins, this technology creates a digital replica of the physical system executed in real-time or faster, which can modify hardware controls. However, its advantage stems from distributing computational efforts by utilizing a hierarchical structure composed of lower-level digital twin blocks and a higher-level system digital twin. Each digital twin block is associated with a physical subsystem of the hardware and communicates with a singular system digital twin, which creates a system-level response. By extracting information from each level of the hierarchy, power system controls of the hardware were reconfigured autonomously. This hierarchical digital twin development offers several advantages over other digital twins, particularly in the field of naval power systems. The hierarchical structure allows for greater computational efficiency and scalability while the ability to autonomously reconfigure hardware controls offers increased flexibility and responsiveness. The hierarchical decomposition and models utilized were well aligned with the physical twin, as indicated by the maximum deviations between the developed digital twin hierarchy and the hardware.
NO1 Uk best vashikaran specialist in delhi vashikaran baba near me online vas...Amil Baba Dawood bangali
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CW RADAR, FMCW RADAR, FMCW ALTIMETER, AND THEIR PARAMETERSveerababupersonal22
It consists of cw radar and fmcw radar ,range measurement,if amplifier and fmcw altimeterThe CW radar operates using continuous wave transmission, while the FMCW radar employs frequency-modulated continuous wave technology. Range measurement is a crucial aspect of radar systems, providing information about the distance to a target. The IF amplifier plays a key role in signal processing, amplifying intermediate frequency signals for further analysis. The FMCW altimeter utilizes frequency-modulated continuous wave technology to accurately measure altitude above a reference point.
We have compiled the most important slides from each speaker's presentation. This year’s compilation, available for free, captures the key insights and contributions shared during the DfMAy 2024 conference.
Final project report on grocery store management system..pdfKamal Acharya
In today’s fast-changing business environment, it’s extremely important to be able to respond to client needs in the most effective and timely manner. If your customers wish to see your business online and have instant access to your products or services.
Online Grocery Store is an e-commerce website, which retails various grocery products. This project allows viewing various products available enables registered users to purchase desired products instantly using Paytm, UPI payment processor (Instant Pay) and also can place order by using Cash on Delivery (Pay Later) option. This project provides an easy access to Administrators and Managers to view orders placed using Pay Later and Instant Pay options.
In order to develop an e-commerce website, a number of Technologies must be studied and understood. These include multi-tiered architecture, server and client-side scripting techniques, implementation technologies, programming language (such as PHP, HTML, CSS, JavaScript) and MySQL relational databases. This is a project with the objective to develop a basic website where a consumer is provided with a shopping cart website and also to know about the technologies used to develop such a website.
This document will discuss each of the underlying technologies to create and implement an e- commerce website.
Welcome to WIPAC Monthly the magazine brought to you by the LinkedIn Group Water Industry Process Automation & Control.
In this month's edition, along with this month's industry news to celebrate the 13 years since the group was created we have articles including
A case study of the used of Advanced Process Control at the Wastewater Treatment works at Lleida in Spain
A look back on an article on smart wastewater networks in order to see how the industry has measured up in the interim around the adoption of Digital Transformation in the Water Industry.
HEAP SORT ILLUSTRATED WITH HEAPIFY, BUILD HEAP FOR DYNAMIC ARRAYS.
Heap sort is a comparison-based sorting technique based on Binary Heap data structure. It is similar to the selection sort where we first find the minimum element and place the minimum element at the beginning. Repeat the same process for the remaining elements.
Sachpazis:Terzaghi Bearing Capacity Estimation in simple terms with Calculati...Dr.Costas Sachpazis
Terzaghi's soil bearing capacity theory, developed by Karl Terzaghi, is a fundamental principle in geotechnical engineering used to determine the bearing capacity of shallow foundations. This theory provides a method to calculate the ultimate bearing capacity of soil, which is the maximum load per unit area that the soil can support without undergoing shear failure. The Calculation HTML Code included.
Cosmetic shop management system project report.pdfKamal Acharya
Buying new cosmetic products is difficult. It can even be scary for those who have sensitive skin and are prone to skin trouble. The information needed to alleviate this problem is on the back of each product, but it's thought to interpret those ingredient lists unless you have a background in chemistry.
Instead of buying and hoping for the best, we can use data science to help us predict which products may be good fits for us. It includes various function programs to do the above mentioned tasks.
Data file handling has been effectively used in the program.
The automated cosmetic shop management system should deal with the automation of general workflow and administration process of the shop. The main processes of the system focus on customer's request where the system is able to search the most appropriate products and deliver it to the customers. It should help the employees to quickly identify the list of cosmetic product that have reached the minimum quantity and also keep a track of expired date for each cosmetic product. It should help the employees to find the rack number in which the product is placed.It is also Faster and more efficient way.
Cosmetic shop management system project report.pdf
MINIMALLY BUFFERED ROUTER USING WEIGHTED DEFLECTION ROUTING FOR MESH NETWORK ON CH
1. International Journal of VLSI design & Communication Systems (VLSICS) Vol.6, No.3, June 2015
DOI : 10.5121/vlsic.2015.6306 59
MINIMALLY BUFFERED ROUTER USING
WEIGHTED DEFLECTION ROUTING FOR
MESH NETWORK ON CHIP
Simi Zerine Sleeba and Mini M.G.
Department of Electronics Engineering, Government Model Engineering College,
Cochin University of Science and Technology
Kochi, India
ABSTRACT
The scalability, modularity and massive parallelism exhibited by Network on chip(NoC) interconnects
make them highly suitable for the inter core communication framework of multiprocessor system-on-chip
(MPSoC) designs. Routers play the most vital role in transferring flits through the network, hence efficient
microarchitecture and cost effective routing algorithms are highly essential for modern NoC routers.
Elimination of buffers and deflection routing help to achieve energy and area efficiency of these routers.
The advantages of bufferless and buffered designs can be combined by using a minimum number of side
buffers to store a fraction of deflection flits in the router. In this paper, we propose a routing algorithm
based on weighted deflection of flits for minimally buffered deflection routers. Evaluations on 4x4 and 8x8
mesh NoC using synthetic workloads as well as benchmark applications demonstrate that deflection rate
and average network latency are significantly reduced in comparison with the state of the art NoC routers.
Performance analysis of the newly proposed algorithm shows that the network saturation point improves
by 26% compared to earlier designs in this domain.
KEYWORDS
Network on Chip, Deflection routing, Minimal buffering, Average Latency
1. INTRODUCTION
As technology scaling reduces the feature size to nanolevels, a large number of intellectual
property cores are being integrated on to a single chip[1]. Such chips can execute applications
that demand extensive amounts of parallel processing. Hence there is an ever increasing demand
for on chip interconnects capable of handling huge amount of data. Traditional bus based
interconnects are no longer suitable for MPSoCs with hundreds and thousands of cores. NoCs
emerge as a promising design choice for realising efficient on chip interconnections as they
largely alleviate the limitations of bus based interconnects.
Generally, MPSoCs employ a regular mesh topology as in Figure 1. Each Processing Element
(PE) is connected to a local switching element called router(R) by means of a network interface.
Each PE is either a processor core (with built-in L1 cache) or a slice of shared L2 cache. Requests
2. International Journal of VLSI design & Communication Systems (VLSICS) Vol.6, No.3, June 2015
60
for data transfer between processor and shared cache inject packets into the network. These
packets start from source node and traverse multiple routers and links before reaching the
destination node. Each router has five input ports and five output ports, four of them are
connected to neighbouring routers in the east, west, north and south directions. The fifth input
port accepts packets injected from the PE to the network and output port ejects packets destined
to the PE from the network. The packets arriving at the input ports of a router move through
various functional units and get access to output ports depending on their routing choice and
prioritisation.
Figure 1. Mesh Interconnection Topology Figure 2. MinBD router microarchitecture[8]
In the traditional virtual channel router (VCR), large number of buffers are employed at the input
ports so that flits belonging to different packet transmissions can proceed simultaneously through
the same physical channel[2][3]. Packets that cannot find a productive output port from the
router are temporarily buffered. Thus buffers prevent unnecessary wastage of link bandwidth and
increase saturation throughput of the network. But these buffers consume significant amount of
dynamic power when active and static power when idle[4][5]. Recent research findings indicate
that static power could constitute 80% to 90% of interconnect power in future systems[6][7].
Hence buffer size is an important parameter that affects area, power and performance of NoCs.
The buffered routers provide an overprovisioned buffer size to accomodate the worst case
network traffic. Real applications are found to have a low injection rate[8][9] compared to
synthetic traffic and in such situations, buffer utilisation is very less. Hence the concept of
bufferless and minimally buffered router in NoC are gaining acceptability as they can deliver
similar performance with a lesser power consumption. In these routers, packets are broken down
into smaller flow control units or flits which are independently routed. In bufferless deflection
routers, when more than one incoming flit competes for the same output port, one wins and
traverses through the desired output port, the others are assigned non productive ports ie. such
flits are deflected. So eventhough power and area due to buffers is minimum in bufferless
designs, the flit deflection rate is high and network saturates earlier compared to buffered routers.
Minimally buffered routers combine the advantages of buffered and bufferless designs by
buffering a small fraction of the deflection flits, achieving performance close to that of NoCs
with buffered routers. The area and power consumed by the side buffers are not significantly
higher than that of bufferless designs.
3. International Journal of VLSI design & Communication Systems (VLSICS) Vol.6, No.3, June 2015
61
In this work, we propose a novel weighted deflection algorithm for output port selection in
minimally buffered routers for mesh NoCs. From evaluations, we observe that the proposed
algorithm outperforms the native routing method of MinBD in terms of reduced deflection rate
and average flit latency. Reduction in deflection rate leads to reduced dynamic power
consumption due to unproductive flit movement through the network.
The rest of the paper is organised as follows. Sections 2 and 3 give an overview of the existing
deflection routers employing minimal buffering and the motivation behind this work. Section 4
and 5 explain the Weighted Deflection routing algorithm and router pipeline in detail. Section 6
describes the evaluation method. We consolidate our experimental results in Section 7 and then
we conclude the paper.
2. RELATED WORK
First among the network on chip routers is the buffered virtual channel router that attains the
required network performance by providing large number of virtual channels and buffers [2] [3].
Bufferless routers are first proposed in [10][11]. Bufferless routing mechanism is either based on
dropping and retransmission of packets or on deflection of packets. SCARAB [12] uses the
policy of packet dropping which incurs a high retransmission overhead. BLESS [13] proposes a
bufferless router microarchitecture using deflection routing. In a deflection router, all flits
arriving at the input ports pass through one of the output ports from the router pipeline [14].
BLESS routers use sequential allocation of output ports to flits which are sorted on the basis of
age; this increases the critical path length inside the router and makes the router slow. A much
superior router microarchitecture is that of CHIPPER [15] which employs parallel port allocation
of flits. CHIPPER is faster compared to BLESS but exhibits higher flit deflection rate. In our
earlier work, WeDBless [16],we use a routing policy which reduces deflection rate significantly
by prioritising output ports for a flit based on Deflection Weights(DW) and ranking flits inside
the router based on Weighted Deflection Count (WDC).
MinBD [8] which is the first minimally buffered router design employs a small side buffer to
store a few number of deflection flits in the router. DEBAR [9] and SLIDER [17] also use
minimal buffering at the routers along with innovative methods for flit ejection, injection and
buffering. Another work using minimal buffering inside router is mentioned in [18]. The study of
various NoCs using deflection routing comes out with the opinion that a priority based deflection
policy which uses global or history related criteria is most suited for boosting the performance of
networks [19].
3. MOTIVATION
The MinBD router is efficient in terms of lower deflection rate compared to CHIPPER and
consumes lesser power and area compared to virtual channel router. In deflection routers, each
incoming flit is transferred to an output port or a side buffer in two cycles of operation ( we use
two cycle routers). Deadlock problem does not arise in deflection routers since cyclic dependency
of resources will not occur [13]. In bufferless routers, it is equally important to ensure livelock
freedom. Both CHIPPER and MinBD use the golden flit priority scheme to resolve livelock
problem. In this scheme, flits belonging to one packet are marked as the highest priority flits
(golden flits) in the entire network and it is guaranteed to win a productive output port at each
router until the packet finally reaches the destination and golden status is passed on to another
4. International Journal of VLSI design & Communication Systems (VLSICS) Vol.6, No.3, June 2015
62
packet. This scheme is not very efficient because more that 90% of the flits are delivered without
becoming golden. The conflict for port allocation of non golden flits is resolved randomly.
MinBD uses an additional silver flit priority for prioritising a flit within a router. We analyse
certain drawbacks of MinBD which motivate us to propose a new router using weighted
deflection algorithm.
3.1. Problem of complex flit prioritisation scheme
The golden priority scheme requires that all routers in the network incorporate a functional unit
for golden flit identification while most of them donot recieve golden flits. Silver flit scheme is
also inefficient since it cannot ensure that high priority flits in one router get similar priority in
the succeeding routers. This leads to increased number of deflections per flit resulting in early
saturation of the network. The silver flit prioritisation unit also increases the critical path delay
inside router as can be seen from Figure 2.
3.2. Inefficiency of dimension order routing
MinBD uses the Permutation Deflection Network(PDN) proposed in CHIPPER [15] for
allocating output port to flits. Computation of desired output port is done by XY routing method
which computes only one productive output for a flit. In a mesh network, majority of the flits
have two productive output ports in a router. If one of the output ports chosen by the flit is in
demand by a higher priority flit, the lower priority flit can occupy the next productive output port.
But this capability of PDN is not utilised by the existing routing algorithm in MinBD. Hence we
need a routing algorithm which adaptively chooses output ports for flits based on local
congestion in the neighbouring routers and global congestion in the network.
3.3. Additional power and area consumption due to duplicate ejection units
As shown in Figure 2, MinBD router uses two ejection units placed one after another for ejecting
two locally destined flits in a cycle. This costs additional power and area and also increases the
critical path length inside the router.
In this work, we propose a Weighted Deflection routing algorithm for a minimally buffered
router which eliminates flit ranking based on complex global timing and provides local priority
for a flit inside the router based on the value of Weighted Deflection Level. Flits with higher
WDL win the arbitration for output port in a router. Choice of output port for a flit is based on
Weighted Distance to Destination which provides more than one productive routes for a flit in
majority of the cases. Dual ejection is facilitated through a single ejection port by providing an
Eject Buffer which buffers one ejection ready flit. The path delay inside the router caused by
duplicate ejection units and the additional wiring overhead is reduced in this design. We also
propose a simple logic that precomputes the productive routes of outgoing flits in the succeeding
router by adjusting the WDDs of the flit.
4. WEIGHTED DEFLECTION ROUTING ALGORITHM
In this routing method, flits in a router are ranked based on the value of Weighted Deflection
Level(WDL)and output ports for a flit are prioritised based on Weighted Distance to
Destination(WDD). WDL and WDD values are incorporated in the enhanced header of a flit.
5. International Journal of VLSI design & Communication Systems (VLSICS) Vol.6, No.3, June 2015
63
4.1. Weighted Deflection Level
The WDL is 6 bits long and has an initial value of 0 when injected into the network. When a flit
makes a hop from one router to another, its WDL value changes. When the flit moves through a
productive output port, its WDL is decremented and when it is deflected through non productive
port, its WDL is incremented. So frequently deflected flits have higher WDL value compared to
less deflected ones. During arbitration for port allocation, if two flits compete for the same output
port, the one with higher WDL wins and moves through the desired port whereas the other flit is
deflected through the remaining output port. As the flit moves out of a router, its WDL is updated
with the new value . Since the WDL of deflected flits are incremented, these flits get higher
priority to win productive output ports in subsequent routers. The WDL field maintains an
account of the flit’s deflection and this priority scheme effectively replaces other methods based
on global timing information.
4.2. Weighted Distance to Destination
For a flit, the productive output ports of a router are those which move the flit towards its
destination router. Each flit has four WDDs, each of which are 2 bit values. They represent the
Figure 3. Example 4x4 Mesh Network Figure 4. Enhanced Flit Header
Figure 5: Maximum value of WDL for various flit injection rates for 8x8 mesh
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relative distance of the flit’s destination from the current router in the North, South, East, West
directions. Each WDD can have a value of -1(least distance and highly preferred output port), +1
(second preference output port), +2 (non productive or least preferred output port). WDD of -1,+1
and +2 are coded as 00, 01 and 10 respectively. We use 8 bits in total to accomodate the four
WDDs in the enhanced flit header. When a flit is injected into the network the WDDs are
calculated based on the position of its destination and stored in its header. During the arbitration
for output port selection, each flit gets its routing preference from the WDD values in its header.
A flit tries to occupy an output port with the least WDD value. Consider the 4 x 4 mesh NoC
shown in Figure 3. For a flit at south input port of router(1,1) whose destination is at router(2,2),
north and east directions are equally productive, hence WDD values in these directions will be -1.
south and west output ports carry the flit away from the destination and hence WDD values in
those directions will be +2 . The 8 bit WDD values of this flit at router(1,1) will be North(00),
South(10), East(00), West(10). As a second example, if the flit destination is at router(1,2), only
the East output port has a WDD of -1, North and South WDDs are +1 and west WDD is +2.
Figure 6. Pipeline diagram of proposed router
When the flit leaves the current router, the flit header is updated with a new set of WDDs
corresponding to the next router. This is done in the route precomputation stage at the end of the
router pipeline. The WDL of a flit is updated by adding the WDD corresponding to the allocated
output port to it. In the first example mentioned above, if north or east output port is alloted to the
flit (WDD value is -1), its new WDL value is obtained by adding -1 to the current WDL value. If
south or west output port (WDD value is +2 ) is alloted, new WDL is obtained by adding +2 to
the current WDL value. As a flit gets deflected away from the destination, the WDL value
increases due to addition of larger WDDs. We maintain the value of WDL between 0 and 26 by
decrementing the value as the flit approaches destination and incrementing it as it goes away.
This priority scheme based on Weighted Deflection largely increases the probability of the older
flits reaching the destination earlier. Thus, the algorithm guarantees livelock freedom of flits
since increase in WDL raises the priority of deflected flits and prevents them from being
deflected continuously.
4.3. Enhanced Flit Header
In order to incorporate the WDL and WDDs, we use an enhanced header of 14 bits for each flit .
The header format is shown in Figure 4. Among the 14 bits; 8 bits represent the four WDDs and
6 bits represent WDL. In Figure 5, we plot the maximum values of WDL obtained for various flit
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injection rates in an 8x8 mesh network. The WDL value increases from 0 to 38 as the injection
rate is increased. Hence a 6 bit field is sufficient to represent WDL in the flit header.
5. ROUTER PIPELINE
In the router pipeline shown in Figure 6, the incoming flits experience two cycle latency. At the
beginning and end of a cycle, flits are stored in pipeline registers which are shown by solid
vertical lines in Figure 6. One cycle latency is constituted by ejection unit, flit injection from side
buffers and injection from the local PE. The next cycle includes output port allocation using
Permutation Deflection Network(PDN), side buffering of deflection flits and route
precomputation. Function of each of these units is explained in detail.
5.1. Ejection Unit
The function of the Ejection Unit is to remove flits destined for the local core from the network.
The ejection unit consists of a flit identification circuit, an Eject Buffer (EB) and Eject
Multiplexer. We refer to the flits destined for the local core as Ejection Ready Flits (ERF). The
flit identification circuit identifies the ERF from among the flits arriving at the input ports of the
router. We simulate the network using real application traffic and observe that for 10% of the
operation cycles, more than one ERF occur. For very few cases, more than one ERF is present in
two consecutive cycles. In the newly proposed router, we use the dual ejection mechanism
mentioned in [9] and [16] where dual ejection is made possible using a single ejection port. If
more than one ERF is present, the one with the highest WDL qualifies for ejection through the
local port and one is buffered in the EB. The ERF in the Eject Buffer is ejected from the router in
the next cycle. In the next cycle, newly arrived ERF are considered for ejection only if EB is
empty. If more than two ERF are present, one is ejected, one is buffered and the others are
deflected. But such cases occur rarely as we see in evaluations. Buffering of one ERF in a cycle
substantially reduces deflections due to them.
5.2. Injection
There are two injection blocks placed one after another. One is for buffer injection and the other
is for injection from local core. In this router, some of the deflection flits are forced into a side
buffer after port allocation. The Buffer Injection unit re-injects these flits back into the router
pipeline in a subsequent clock cycle, when any of the flits in the four input channels are not
present. In a cycle, atmost one flit can be re-injected into the router pieline. A FIFO side buffer is
used in the routers ie. the flit that entered the side buffer first will be re-injected into the pipeline
first. The local PE can inject flits into the network only when at least one input channel is free
even after re injection from side buffer. In a cycle, atmost one flit can be injected from the local
core.
5.3. Permutation Deflection Network
We use the PDN structure mentioned in CHIPPER and MinBD for parallel output port allocation.
This PDN efficiently maps every input port to every output port of the router. The PDN consists
of four 2x2 Permutation Deflection Units (PDU1, PDU2, PDU3, PDU4) arranged in two stages,
two units per stage. In the first stage, the North and East input channels are connected to PDU1
and South and West input channels are connected to PDU2. In each permuter block, the flit with
higher WDL value has the priority to choose the desired output port and the flit with lower WDL
gets the other port. The winning flit chooses the output port with lesser WDD; the WDD values
are obtained from the flit header.
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At the output of Permutation units PDU3 and PDU4, an output port is alloted to each flit. Most of
the flits have two output ports with the same WDD values. So even if a flit does not win an
arbitration in the first permutation stage, it can still acquire an equally desirable output port in the
second stage. For example, if a flit from the north input port is destined for a router in the south
east direction, both south and east output ports are equally productive for it. If the flit fails to get
to south output port at PDU1 due to lesser WDL value, it will be deflected to PU4 which is
connected to east and west output ports. In this block the flit has a chance of getting the east
output port which is also equally desirable for it. If the flit again loses in this arbitration and is
deflected through the west output port, its WDL value is incremented by + 2 (WDD of west
output port is +2 for this flit). Then the flit has an increased probability of winning the desired
output port in the next router.
5.4. Side Buffering of Deflection Flits
In minimally buffered router, after port allocation by the PDN, some of the flits donot win
productive output ports to their destinations. Deflection of these flits through the links is reduced
by moving some of them into a side buffer. We choose the side buffer size as 4. Atmost one flit
can be side buffered in a cycle. If the side buffer is full, flits in the subsequent cycles are
deflected.
Table 1. Precomputed WDD values for a flit at router (1,1)
Assigned Output Destination at (2,2) Destination at (3,3)
N S E W N S E W
North 1 1 -1 2 -1 2 -1 2
South -1 2 -1 2 -1 2 -1 2
East -1 2 1 1 -1 2 -1 2
West -1 2 -1 2 -1 2 -1 2
5.5. Route Precomputation Unit
The WDL and WDD values in the header of the outgoing flits are recomputed and updated in this
unit which is placed after the port allocation stage. The new WDD values correspond to preferred
output routes in the next router. Pre-computation of routes using this method is less complex
compared to that of MinBD where XY route computation is done for incoming flits. This can be
explained with the help of the example in Figure 3. If south or west output port ( WDD is +2) is
alloted to the sample flit at router (1,1), the flit is being moved further away from destination. So
in the south or west neighbouring router of (1,1), the WDD values have no change ie. they need
not be re-computed. Table 1 shows the precomputed WDD values for a flit at router(1,1) when
destination is at router(2,2) (in columns 2 to 5) and destination is at router(3,3) (in columns 6 to
9). Since the current WDD values of the flit in north, south, east and west directions are 0, +2, 0
and +2 respectively, WDDs need to be re-computed only when a flit having two productive
output ports is alloted one of them and destination is at two hops distance from the current router.
In all other cases, the new values of WDDs are equal to the previous values.
6. EXPERIMENTAL METHODOLOGY
We use the traditional cycle accurate NoC simulator, Booksim [20] which models the VC router
mentioned in [2]. We make suitable modifications on Booksim to model the newly proposed
minimally buffered router using weighted deflection (abbreviated as MinBWD in the evaluation
section) as mentioned in Section 4. We enhance the flit header with 14 bits for representing WDD
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(8 bits) and WDL values ( 6 bits). We also model the CHIPPER and MinBD architectures as
mentioned in the literature and use MinBD as a baseline in our evaluations. The router delay is
two cycles in all the three architectures. We conduct all evaluations using single flit packets.
6.1. Synthetic Workloads
We use synthetic traffic patterns to analyse the robustness of our algorithm. Real applications
exhibit self throttling, hence synthetic traffic is best suited to test the network saturation point of
an algorithm. Uniform random traffic is used to assess the adaptability and load balancing
capability of the routing algorithm where as patterns like transpose, bit-complement and tornado
are network intensive. Using these synthetic workloads, we conduct simulations on 4x4 and 8x8
mesh network. After sufficient warm up time, we collect the average flit latency, deflection rate
and throughput values by varying the flit injection rates from 0 to network saturation point.
Table 2. Percentage of different network injection intensity applications in various benchmark mixes.
Benchmark Mix M1 M2 M3 M4 M5 M6
% of Low 100 0 0 50 0 31
% of Medium 0 100 0 0 50 31
% of High 0 0 100 50 50 38
Figure 7. Average flit latency comparison under various synthetic traffic patterns in 8 × 8 mesh network.
Figure 8: Average flit deflection comparison under various synthetic traffic patterns
in 8 × 8 mesh network
6.2. Real Applications
We simulate a 64 (8x8) core multiprocessor system using Multi2sim [21]. Each core has an out-
of-order x86 processor with 64KB 4-way set associative L1 cache and 512KB 16-way set
associative shared L2 cache. Each core runs one of the applications from SPEC CPU 2006
benchmark application suite [22]. Based on the misses per kilo instructions(MPKI) from L1
cache, these applications are classified as low, medium or high MPKI . We run low MPKI
applications like calculix, gombk and h264ref; medium MPKI applications like bwaves,
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bzip2,gcc and high MPKI applications such as hmmer, leslie3d and matlab in our simulations.
We generate 6 workload mixes by combining applications from the suite as given in Table 2. The
network packets generated by these workloads are used in our NoC simulator and average
deflection rate and average latency of MinBWD and MinBD are compared.
7. EXPERIMENTAL ANALYSIS
We compare the average deflection rate of MinBWD with that of MinBD for synthetic and real
workloads to analyse the role of weighted deflection algorithm in reducing deflections. We also
compare the average flit latencies of MinBWD with MinBD as well as a bufferless router,
CHIPPER. We analyse average latencies for 4x4 and 8x8 mesh inorder to study the variation in
performance with network scaling. Various performance parameters like average deflection rate,
average latency and average throughput are analysed in detail.
Figure 9. Average flit latency comparison under various synthetic traffic patterns
in 4 × 4 mesh network.
Figure 10: Average deflection rate and latency for real applications.
7.1. Effect on Average Deflection Rate
Deflection of flits through the network causes unnecessary dissipation of dynamic power. The
aim of our algorithm is to minimise these deflections and achieve energy efficiency for the NoC.
Average deflection rate is computed as the average number of deflections encountered per flit.
The average deflection plot for three typical synthetic traffic patterns ie., uniform-random,
transpose and bit complement are shown in Figure 8. MinBWD reduces the average deflection
rate by 56% compared to MinBD for uniform-random traffic. For non-uniform traffic distribution
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like transpose and bit complement, MinBWD reduces deflection rate by 33% and 65%
respectively. Unique features of the proposed algorithm which lead to reduction in deflection rate
are: (1) providing more than one productive paths for a flit (2) incrementing WDL value for
deflected flits giving them high priority to win arbitration in successive routers (3)providing Eject
Buffer to store ERF for dual flit ejection. From evaluations using real applications as shown in
10, MinBWD shows a maximum of 36% reduction in deflection rate which is obtained for work-
loads with a larger share of high MPKI applications. This explains that the effectiveness of the
MinBWD algorithm is more evident under higher network load.
7.2. Average Flit Latency
It is obvious that the reduction in deflection rate obtained for MinBWD reflects in the average flit
latency also. Flit latency is measured as the average number of cycles taken by the flit from the
time it is generated at the PE upto its ejection at the destination core. A lower value of latency
means that the data flits traverse the network in lesser number of cycles and this results in
application speed up. We plot the average latencies for synthetic traffic patterns for 8x8 and 4x4
mesh in Figure 7 and Figure 9 respectively. For uniform traffic, the adaptivity and reduced
deflections of MinBWD improves the network saturation point by 26% compared to MinBD.
Figure 11: Average throughput comparison under various synthetic traffic patterns
in 8 × 8 mesh network.
7.3. Average Throughput
The throughput is computed as the number of flits ejected from the network per router per cycle.
Average throughput variations for various synthetic traffic patterns is shown in Figure 11. At
lower injection rates, the throughput delivered by MinBWD and MinBD are similar. MinBD
reaches saturation earlier and a dip in throughput is observed for injection rates higher than
saturation point.The average throughput of MinBWD is higher for all synthetic workloads and a
steady value is maintained further beyond saturation.
8. ROUTER TIMING, POWER AND AREA
We implement each of the functional units of the minimally buffered router using Verilog HDL
and synthesise using an EDA tool. We also model additional control logic required for weighted
deflection algorithm and compare the overall timing latency of MinBWD and MinBD router
architectures. Since MinBWD uses dual ejection with Eject Buffer, the first pipeline stage has
37% gain in timing latency compared to MinBD which uses two ejection Units. Silver flit
prioritisation stage of MinBD is not used in our design and the timing delay of PDN in both
MinBD and MinBWD is the same. The delay of the Route precomputation unit at the end of the
second pipeline stage in MinBWD is lesser than that of silver flit priority block of MinBD, hence
we conclude that the timing latency of the second pipeline stage is same for MinBWD and
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MinBD. Among the two pipeline stages, second stage dominates the timing latency and hence it
decides the router’s operating frequency.
We use Orion 2.0 tool[23] for modelling the power and area consumed by MinBWD as well as
MinBD. We choose the operating frequency as 1GHz, technology parameter as 65nm and link
delay as one cycle. The enhanced flit header in MinBWD uses additional 14 bits for transmitting
WDL and WDD values. Hence static power and wiring area at each of the links increases by 10%
compared to MinBD. The scheme for dual ejection using single ejection port reduces channel
wiring overhead in MinBWD by 26%.
9. CONCLUSION
In this paper we propose a novel routing algorithm for minimally buffered deflection routers
which reduces the flit deflection rate and average latency of flits using a unique mechanism of
Weighted Deflection. Flits are prioritized using Weighted Deflection Level which is directly
proportional to the amount of deflections encountered by the flit. Route computation for a flit
based on Weighted Distance to Destination and predetermination of these values for a router
contribute significantly to adaptive routing and reducing critical path lengths. From this work, we
conclude that the new algorithm combined with minimal buffering for deflection routers promise
better performance for NoCs in terms of higher network saturation points and lower latencies.
ACKNOWLEDGEMENTS
This work is supported in part by grant from UGC under MOMA-MANF scheme.
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AUTHORS
Simi Zerine Sleeba recieved her B.Tech degree in Electronics & Communication
Engineering from Mahatma Gandhi University, India in 1997 and M.Tech degree in
VLSI & Embedded Systems from Cochin University of Science and Technology,
India in 2010. Currently, she is pursuing her PhD research at Cochin University of
Science and Technology. Her research interests include On chip interconnection
network architectures and algorithms and low power MPSoC design.
Mini M.G. recieved her B.Tech degree in Electronics & Communication Engineering
from Kerala University, M.Tech degree in Digital Electronics and PhD in Image
Processing from Cochin University of Science and Technology, India. She is presently
working as the Academic Dean at Govt. Model Engineering College, Kochi, India.
Her research interests include low power MPSoC design, network on chip
architectures and digital image processing.