This article presents novel high speed and low power full adder cells based on carbon nanotube field effect
transistor (CNFET). Four full adder cells are proposed in this article. First one (named CN9P4G) and
second one (CN9P8GBUFF) utilizes 13 and 17 CNFETs respectively. Third design that we named
CN10PFS uses only 10 transistors and is full swing. Finally, CN8P10G uses 18 transistors and divided into
two modules, causing Sum and Cout signals are produced in a parallel manner. All inputs have been used
straight, without inverting. These designs also used the special feature of CNFET that is controlling the
threshold voltage by adjusting the diameters of CNFETs to achieve the best performance and right voltage
levels. All simulation performed using Synopsys HSPICE software and the proposed designs are compared
to other classical and modern CMOS and CNFET-based full adder cells in terms of delay, power
consumption and power delay product.
CNFET BASED BASIC GATES AND A NOVEL FULLADDER CELLVLSICS Design
In this paper two novel high performance designs for AND and OR basic gates and a novel Full-Adder Cell are presented. These designs are based on carbon nanotube technology. In order to compare the proposed designs with previous ones both MOSFET based and CNFET based circuits are selected. By the way the proposed designs have better performance in comparison with previous designs in terms of speed, power consumption and power-delay product (PDP).
A Low Power High Bandwidth Four Quadrant Analog Multiplier in 32 NM CNFET Tec...VLSICS Design
Carbon Nanotube Field Effect Transistor (CNFET) is a promising new technology that overcomes several limitations of traditional silicon integrated circuit technology. In recent years, the potential of CNFET for analog circuit applications has been explored. This paper proposes a novel four quadrant analog multiplier design using CNFETs. The simulation based on 32nm CNFET technology shows that the proposed multiplier has very low harmonic distortion (<0.45%), large input range (±400mV), large bandwidth (~50GHz) and low power consumption (~247µW), while operating at a supply voltage of ±0.9V.
Design of a CMOS-based microwave active channelized bandpass filterTELKOMNIKA JOURNAL
A two-branch microwave active bandpass filter is designed through the channelized filtering technique as well as the transversal concept. Both the main and the auxiliary branches, connected without power dividers/combiners, rely on C-coupled active third order Chebyshev bandpass filters. A lumped element signal delay circuit is also introduced in the main channel. Active inductors based on the gyrator-C topology, are involved in the Chebyshev filters’ structure. CMOS-based Operational Transconductor Amplifier (OTA) circuits are the building blocks of these inductors. The proposed active transversal channelized filter produces an elliptic narrow band response, centered at 1.13 GHz. Simulation results, obtained by means of the PSPICE code according to the 0.18 μm TSMC MOS technology, indicate excellent performances illustrating good impedance matching, low insertion losses and high selectivity. Finally, the noise analysis shows that the filter has a low noise figure in the bandwidth.
Performance Comparison of CMOS and Finfet Based Circuits At 45nm Technology U...IJERA Editor
According to the Moore’s Law, the number of transistors in a unit chip area double every two years. But the existing technology of integrated circuit formation is posing limitations to this law. CMOS technology shows certain limitations as the device is reduced more and more in the nanometer regime out of which power dissipation is an important issue. FinFET is evolving to be a promising technology in this regard. This paper aims to analyze and compare the characteristics of CMOS and FinFET circuits at 45nm technology. Inverter circuit is implemented in order to study the basic characteristics such as voltage transfer characteristics, leakage current and power dissipation. Further the efficiency of FinFET to reduce power as compared to CMOS is proved using SRAM circuit. The results show that the average power is reduced by 92.93% in read operation and by 97.8% in write operation.
Performance Analysis of Interconnect Drivers for Ultralow Power ApplicationsIDES Editor
ultralow power consumption requirement of low
throughput applications needs to operate circuits in
subthreshold region where subthreshold leakage current is used
as active current for necessary computations. This paper
investigates the impact of interconnect drivers on digital circuit
performance in subthreshold region. In particular, we have
investigates the performance of Si-MOSFET and CNFETs at
32nm deep submicron technology node. Performance Analysis
is carried out for different interconnect drivers driving global
interconnect. We have proposed an optimized CNFET driver
which gives the significant improvement in delay and PDP over
conventional CNFET in subthreshold for global and semi-global
interconnect length. HSPICE device model files generated from
“Nano CMOS” tool are use for Si-MOSFET to analyze the
impact of Process and Temperature (P, T) variations on
robustness of circuit for fair comparison with CNFET.
Variability of design metric parameters is evaluated by applying
Gaussian distribution using Monte Carlo simulation run.
CNFET BASED BASIC GATES AND A NOVEL FULLADDER CELLVLSICS Design
In this paper two novel high performance designs for AND and OR basic gates and a novel Full-Adder Cell are presented. These designs are based on carbon nanotube technology. In order to compare the proposed designs with previous ones both MOSFET based and CNFET based circuits are selected. By the way the proposed designs have better performance in comparison with previous designs in terms of speed, power consumption and power-delay product (PDP).
A Low Power High Bandwidth Four Quadrant Analog Multiplier in 32 NM CNFET Tec...VLSICS Design
Carbon Nanotube Field Effect Transistor (CNFET) is a promising new technology that overcomes several limitations of traditional silicon integrated circuit technology. In recent years, the potential of CNFET for analog circuit applications has been explored. This paper proposes a novel four quadrant analog multiplier design using CNFETs. The simulation based on 32nm CNFET technology shows that the proposed multiplier has very low harmonic distortion (<0.45%), large input range (±400mV), large bandwidth (~50GHz) and low power consumption (~247µW), while operating at a supply voltage of ±0.9V.
Design of a CMOS-based microwave active channelized bandpass filterTELKOMNIKA JOURNAL
A two-branch microwave active bandpass filter is designed through the channelized filtering technique as well as the transversal concept. Both the main and the auxiliary branches, connected without power dividers/combiners, rely on C-coupled active third order Chebyshev bandpass filters. A lumped element signal delay circuit is also introduced in the main channel. Active inductors based on the gyrator-C topology, are involved in the Chebyshev filters’ structure. CMOS-based Operational Transconductor Amplifier (OTA) circuits are the building blocks of these inductors. The proposed active transversal channelized filter produces an elliptic narrow band response, centered at 1.13 GHz. Simulation results, obtained by means of the PSPICE code according to the 0.18 μm TSMC MOS technology, indicate excellent performances illustrating good impedance matching, low insertion losses and high selectivity. Finally, the noise analysis shows that the filter has a low noise figure in the bandwidth.
Performance Comparison of CMOS and Finfet Based Circuits At 45nm Technology U...IJERA Editor
According to the Moore’s Law, the number of transistors in a unit chip area double every two years. But the existing technology of integrated circuit formation is posing limitations to this law. CMOS technology shows certain limitations as the device is reduced more and more in the nanometer regime out of which power dissipation is an important issue. FinFET is evolving to be a promising technology in this regard. This paper aims to analyze and compare the characteristics of CMOS and FinFET circuits at 45nm technology. Inverter circuit is implemented in order to study the basic characteristics such as voltage transfer characteristics, leakage current and power dissipation. Further the efficiency of FinFET to reduce power as compared to CMOS is proved using SRAM circuit. The results show that the average power is reduced by 92.93% in read operation and by 97.8% in write operation.
Performance Analysis of Interconnect Drivers for Ultralow Power ApplicationsIDES Editor
ultralow power consumption requirement of low
throughput applications needs to operate circuits in
subthreshold region where subthreshold leakage current is used
as active current for necessary computations. This paper
investigates the impact of interconnect drivers on digital circuit
performance in subthreshold region. In particular, we have
investigates the performance of Si-MOSFET and CNFETs at
32nm deep submicron technology node. Performance Analysis
is carried out for different interconnect drivers driving global
interconnect. We have proposed an optimized CNFET driver
which gives the significant improvement in delay and PDP over
conventional CNFET in subthreshold for global and semi-global
interconnect length. HSPICE device model files generated from
“Nano CMOS” tool are use for Si-MOSFET to analyze the
impact of Process and Temperature (P, T) variations on
robustness of circuit for fair comparison with CNFET.
Variability of design metric parameters is evaluated by applying
Gaussian distribution using Monte Carlo simulation run.
Theoretical Analysis of a two-stage Sagnac loop filter Using Jones Matrices IJECEIAES
In this work, a theoretical analysis of a Sagnac loop filter (SLF) with twostage polarization maintaining fibers (PMFs) and polarization controllers (PCs) is presented. The transmission function of this two-stage SLF is calculated in detail by using Jones matrix. The calculation is performed in order to investigate the filtering characteristics. The theoretical results show that the wavelength interval is depending on the dynamic settings of the length of the PMFs and the polarization angle of the PCs. By changing the polarization angle of the PCs, a multiple of single, dual or triple wavelength in each channel can be achieved. Based on this study, a flat multiwavelength spectrum can be obtained by adjusting the PMFs and the PCs in the twostage SLF. This finding significantly contributes to the generation of multiwavelength fiber laser (MWFL) that can be used for many optical applications.
BER ANALYSIS FOR DOWNLINK MIMO-NOMA SYSTEMS OVER RAYLEIGH FADING CHANNELSIJCNCJournal
The Multiple-input multiple-output (MIMO) technique combined with non-orthogonal multiple access (NOMA) has been considered to enhance total system performance. This paper studies the bit error rate of two-user power-domain NOMA systems using successive interference cancellation receivers, with zeroforcing equalization over quasi-static Rayleigh fading channels. Successive interference cancellation technique at NOMA receivers has been the popular research topic due to its simple implementation, despite its vulnerability to error propagation. Closed-form expressions are derived for downlink NOMA in single-input single-output and uncorrelated quasi-static MIMO Rayleigh fading channel. Analytical results are consolidated with Monte Carlo simulation.
OPTIMIZATION TECHNIQUES FOR SOURCE FOLLOWER BASED TRACK-AND-HOLD CIRCUIT FOR ...VLSICS Design
Since the current demand for high-resolution and fast analog to digital converters (ADC) is driving the need for track and hold amplifiers (T&H) operating at RF frequencies. A very fast and linear T&H circuit is the key element in any modern wideband data acquisition system. Applications like a cable TV or a broad variety of different radio standards require high processing speeds with high resolution. The track-and-hold (T&H) circuit is a fundamental block for analog-to digital (A/D) converters. Its use allows most dynamic errors of A/D converters to be reduced, especially those showing up when using high frequency input signals. Having a wideband and precise acquisition system is a prerequisite for today’s trend towards multi-standard flexible radios, with as much signal processing as possible in digital domain. This work investigates effect of various design schemes and circuit topology for track
and-hold circuit to achieve acceptable linearly, high slew rate, low power consumption and low noise
Interconnected Serialized Architecture for Transmission SystemsIJERD Editor
Transmission system with proposed multiplexer-flip-flops (MUX-FFs) has a high throughput and low-cost solution for serial link transmitters. MUX-FFs is designed with proposed multiplexer-latches that possess a logic function of various combinational circuits and storing capacity of sequential circuits. Pipeline arrangement with MUX-FFs composed of cascaded latches and MUX-latches with this many latch gates for sequential can be removed. Simulation results show that a 8-to-1 serializer with MUX-FFs reduces 63% gate-count compared to traditional pipeline transmission architecture. The measured results shows that the MUX-FFs and the proposed transmission architecture are almost bit error free and high speed in transmission.
DESIGN AND MODELLING OF DIFFERENT SRAM’S BASED ON CNTFET 32NM TECHNOLOGYVLSICS Design
Carbon nanotube field-effect transistor (CNTFET) refers to a field-effect transistor that utilizes a single carbon nanotube or an array of carbon nanotubes as the channel material instead of bulk silicon in the traditional MOSFET structure. Since it was first demonstrated in 1998, there have been tremendous developments in CNTFETs, which promise for an alternative material to replace silicon in future electronics. Carbon nanotubes are promising materials for the nano-scale electron devices such as nanotube FETs for ultra-high density integrated circuits and quantum-effect devices for novel intelligent circuits, which are expected to bring a breakthrough in the present silicon technology. A Static Random Access Memory (SRAM) is designed to plug two needs: i) The SRAM provides as cache memory, communicating between central processing unit and Dynamic Random Access Memory (DRAM). ii) The SRAM technology act as driving force for low power application since SRAM is portable compared to DRAM, and SRAM doesn’t require any refresh current. On the basis of acquired knowledge, we present
different SRAM's designed for the conventional CNTFET. HSPICE simulations of this circuit using Stanford CNTFET model shows a great improvement in power saving.
DESIGN OF LOW WRITE-POWER CONSUMPTION SRAM CELL BASED ON CNTFET AT 32nm TECHN...VLSICS Design
The SRAM which functions as the cache for system-on-chip is vital in the electronic industry. Carbon Nanotube Field Effect Transistor (CNFET) is used for high performance, high stability and low-power circuit designs as an alternative material to silicon in recent years. Therefore Design of SRAM Cell based on CNTFET is important for Low-power cache memory. In cells, the bit-lines are the most power consuming components because of larger power dissipation in driving long bit-line with large capacitance. The cache write consumes considerable large power due to full voltage swing on the bit-line. This Paper proposes a novel 7T SRAM cell based on CNTFET that only depends on one of bit lines for Write operation and reduce the write-power consumption. The read cycle also improved because of careful transistor
sizing. HSPICE simulations of this circuit using Stanford CNFET model shows that 37.2% write power saving, read cycle improvement of 38.6%.
International Journal of Engineering Research and Applications (IJERA) is an open access online peer reviewed international journal that publishes research and review articles in the fields of Computer Science, Neural Networks, Electrical Engineering, Software Engineering, Information Technology, Mechanical Engineering, Chemical Engineering, Plastic Engineering, Food Technology, Textile Engineering, Nano Technology & science, Power Electronics, Electronics & Communication Engineering, Computational mathematics, Image processing, Civil Engineering, Structural Engineering, Environmental Engineering, VLSI Testing & Low Power VLSI Design etc.
Design and Analysis of Power and Variability Aware Digital Summing CircuitIDES Editor
Due to aggressive scaling and process imperfection
in sub-45 nm technology node Vt (threshold voltage) shift is
more pronounced causing large variations in circuit response.
Therefore, this paper presents the analyses of various popular
1-bit digital summing circuits in light of PVT (process, voltage
and temperature) variations to verify their functionality and
robustness. The investigation is carried with ±3ó process
parameters and ±10% VDD (supply voltage) variation by applying
Gaussian distribution and Monte Carlo analysis at 22 nm
technology node on HSPICE environment. Design guidelines
are derived to select the most suitable topology for the design
features required. Transmission Gate (TG)-based digital
summing circuit is found to be the most robust against PVT
variations. Hence, a TG-based digital summing circuit is
implemented using carbon nanotube field effect transistor
(CNFET). This implementation offers tighter spread in
propagation delay (3×), power dissipation (1.14×) and EDP
(energy delay product) (1.1×) at nominal voltage of VDD = 0.95V
compared to MOSFET-based (TG – topology) digital summing
circuit implying its robustness against PVT variations.
Design and Analysis of New Modified Feedthrough Logic (MFTL) Circuits Using C...IJERA Editor
It is a challenging task for a VLSI design engineer to develop low power VLSI circuits, without sacrificing its performance. Feedthrough Logic (FTL) is a new technology which could be considered better than the existing technologies for improving circuit efficiency. Modified Feedthrough Logic (MFTL), offers a better power factor than the FTL logic structures, and also shows an improvement in the speed factor. But the scenario again changes when the design extends to nano scales of device dimension, where many factors which were neglected otherwise need to be given more importance. To avoid or minimize problems like hot carrier effects, electro migration, drain induced barrier lowering and other issues that becomes prominent in nano scale MOSFET‟s, Carbon Nanotube Field Effect Transistor (CNTFET) is considered to be a promising candidate in future integrated circuits. Hence this work extends the advantages of MFTL logic into nano level by incorporating CNTFETs in place of MOSFETs. The modifications have been implemented using CNTFETs of 16nm technology from HSPICE library on a 10 chain inverter stage, an 8 bit RCA and a Vedic multiplier and performance factors like PDP and ADP are compared to that of the conventional MOSFET circuits.
Combining SFBC_OFDM Systems with SVD Assisted Multiuser Transmitter and Multi...IOSR Journals
Abstract: In this work, we exploit the SVD assisted multiuser transmitter (MUT) and multiuser detector (MUD) technique, using downlink (DL) preprocessing transmitter and DL postprocessing receiver matrice .In combination with space frequency block coding (SFBC). And also propose the precoded DL transmission scheme, were the both proposed schemes take advantage of the channel state information (CSI) of all users at the base station (BS), but only of the mobile station (MS)’s own CSI, to decompose the MU MIMO channels into parallel single input single output (SISO), these two proposed schemes are compared to the vertical layered space time (V_BLAST) combined with SFBC (SFBC_VBLAST). Our Simulation results show that the performance of the proposed scheme with DL Zero Forcing (ZF) transmitter for interference canceller outperforms the SFBC_VBLAST and the precoded DL schemes with ZF receiver in frequency selective fading channels. Keywords – Post processing, Preprocessing,, SFBC, SVD, ZF.
DESIGN OF A HIGH PRECISION, WIDE RANGED ANALOG CLOCK GENERATOR WITH FIELD PRO...VLSICS Design
This paper presents a circuit of a high-precision, wide ranged, analog clock generator with on-chip programmability feature using Floating-gate transistors. The programmable oscillator can attain a continuous range of time-periods lying in the programming precision range of Floating Gates. The circuit consists of two sub circuits: Current Generator circuit and Wave Generator circuit. The current of current generator circuit is programmable and mirrored to the wave generator to generate the desired square wave. The topology is well suited to applications like clocking high performance ADCs and DACs as well as used as the internal clock in structured analog CMOS designs. A simulation model of the circuit was built in T-Spice, 0.35µm CMOS process. The circuit results in finely tuned clock with programmability precision of about 13bit [1]. Simulation results show high amount of temperature insensitivity (0.507ns/°C) for a large range of thermal conditions. The proposed circuit can compensate any change in temperature. The circuit design can be operated at low supply voltage i.e., 1v.
IJERA (International journal of Engineering Research and Applications) is International online, ... peer reviewed journal. For more detail or submit your article, please visit www.ijera.com
A REVIEW OF THE 0.09 µm STANDARD FULL ADDERSVLSICS Design
This paper presents power analysis of the seven full adder cells [6] reported as having a low PDP (Power Delay Product), by means of speed, power consumption and area. These full adders were designed upon various logic styles to derive the sum and carry outputs. The existed standard full adders and the proposed full adders [6] are designed and showed the better result comparison. This paper describes how the proposed full adders [6] are better in contrast to the standard full adders. And mentioned how the standard full adders are not giving faithful results . All these full adders designed using TDK 90 nm Technology and simulated using mentor graphics EDA tool with BSIMv3 (model 49). And the layouts of all these full adders designed in Icstation of Mentor Graphics and presented their areas. The total results of prelayout and postlayout simulation are tabulated.
DESIGN OF A PROGRAMMABLE LOW POWER LOW DROP-OUT REGULATORVLSICS Design
A low power programmable low drop-out regulator capable of providing 1V output has been proposed. The
regulator requires a supply voltage of 1.2V and works in the temperature range of -40 to 125 °C in nominal
corner (i.e, normal doping for PMOS and NMOS Field Effect Transistors), yielding a load regulation of
3%. The output voltage level is controlled externally by means of 2 1-bit control signals. The circuit
provides a DC gain of 30 dB and a maximum DC Power Supply Rejection Ratio of -35 dB and a worst case
PSRR of -20 dB. Power dissipation in the load is nearly 100 μW
LEAKAGE REDUCTION TECHNIQUE AND ANALYSIS OF CMOS D FLIP FLOPVLSICS Design
The expansion of battery operated portable device is continuously increasing the demand for low
power, minimum delay and high speed integrated circuits. In many of the portable devices the
standby periods are longer than the active periods and thus consume more power in the standby
state [2]. It is extremely important to reduce the power consumption in the standby mode. In
today’s high performance integrated circuits the leakage power contributes major power
consumption than overall total power consumption. In deep submicron circuits the leakage
power increases than the dynamic power and also in the circuits when there are no transitions at
the input and the transistors are in steady state [1]. Leakage power is mainly due to leakage
current that flows in the circuit when the circuit is operated in sleep or standby mode. The
leakage current is composed of sub-threshold leakage current, gate current, gate leakage current
and reverses biased leakage. Among all leakages, sub-threshold leakage contributes major part of
the leakage. The sub-threshold leakage current of a metal oxide semiconductor device is
expressed as
Where µo is the mobility of electrons/holes, Cox denotes oxide
capacitance of gate per unit area, W and L are width and channel length of MOS device
respectively, Vgs is the gate to source voltage Vt is the thermal voltage and η is the swing
coefficient. The contents of this paper are organized as follows: Section 2 descr
MINIMALLY BUFFERED ROUTER USING WEIGHTED DEFLECTION ROUTING FOR MESH NETWORK ...VLSICS Design
The scalability, modularity and massive parallelism exhibited by Network on chip(NoC) interconnects
make them highly suitable for the inter core communication framework of multiprocessor system-on-chip
(MPSoC) designs. Routers play the most vital role in transferring flits through the network, hence efficient
microarchitecture and cost effective routing algorithms are highly essential for modern NoC routers.
Elimination of buffers and deflection routing help to achieve energy and area efficiency of these routers.
The advantages of bufferless and buffered designs can be combined by using a minimum number of side
buffers to store a fraction of deflection flits in the router. In this paper, we propose a routing algorithm
based on weighted deflection of flits for minimally buffered deflection routers. Evaluations on 4x4 and 8x8
mesh NoC using synthetic workloads as well as benchmark applications demonstrate that deflection rate
and average network latency are significantly reduced in comparison with the state of the art NoC routers.
Performance analysis of the newly proposed algorithm shows that the network saturation point improves
by 26% compared to earlier designs in this domain
Impact of parameter variations and optimization on dg pnin tunnel fetVLSICS Design
The downscaling of conventional MOSFETs has come to its fundamental limits. TFETs are very attractive
devices for low power applications because of their low off-current and potential for smaller sub threshold
slope. In this paper, the impact of various parameter variations on the performance of a DG-PNIN Tunnel
field effect transistor is investigated. In this work, variations in gate oxide material, source doping, channel
doping, drain doping, pocket doping and body thickness are studied and all these parameters are optimized
as performance boosters to give better current characteristics parameters. After optimization with all these
performance boosters, the device has shown improved performance with increased on-current and reduced
threshold voltage and the Ion/Ioff ratio is > 106.
Theoretical Analysis of a two-stage Sagnac loop filter Using Jones Matrices IJECEIAES
In this work, a theoretical analysis of a Sagnac loop filter (SLF) with twostage polarization maintaining fibers (PMFs) and polarization controllers (PCs) is presented. The transmission function of this two-stage SLF is calculated in detail by using Jones matrix. The calculation is performed in order to investigate the filtering characteristics. The theoretical results show that the wavelength interval is depending on the dynamic settings of the length of the PMFs and the polarization angle of the PCs. By changing the polarization angle of the PCs, a multiple of single, dual or triple wavelength in each channel can be achieved. Based on this study, a flat multiwavelength spectrum can be obtained by adjusting the PMFs and the PCs in the twostage SLF. This finding significantly contributes to the generation of multiwavelength fiber laser (MWFL) that can be used for many optical applications.
BER ANALYSIS FOR DOWNLINK MIMO-NOMA SYSTEMS OVER RAYLEIGH FADING CHANNELSIJCNCJournal
The Multiple-input multiple-output (MIMO) technique combined with non-orthogonal multiple access (NOMA) has been considered to enhance total system performance. This paper studies the bit error rate of two-user power-domain NOMA systems using successive interference cancellation receivers, with zeroforcing equalization over quasi-static Rayleigh fading channels. Successive interference cancellation technique at NOMA receivers has been the popular research topic due to its simple implementation, despite its vulnerability to error propagation. Closed-form expressions are derived for downlink NOMA in single-input single-output and uncorrelated quasi-static MIMO Rayleigh fading channel. Analytical results are consolidated with Monte Carlo simulation.
OPTIMIZATION TECHNIQUES FOR SOURCE FOLLOWER BASED TRACK-AND-HOLD CIRCUIT FOR ...VLSICS Design
Since the current demand for high-resolution and fast analog to digital converters (ADC) is driving the need for track and hold amplifiers (T&H) operating at RF frequencies. A very fast and linear T&H circuit is the key element in any modern wideband data acquisition system. Applications like a cable TV or a broad variety of different radio standards require high processing speeds with high resolution. The track-and-hold (T&H) circuit is a fundamental block for analog-to digital (A/D) converters. Its use allows most dynamic errors of A/D converters to be reduced, especially those showing up when using high frequency input signals. Having a wideband and precise acquisition system is a prerequisite for today’s trend towards multi-standard flexible radios, with as much signal processing as possible in digital domain. This work investigates effect of various design schemes and circuit topology for track
and-hold circuit to achieve acceptable linearly, high slew rate, low power consumption and low noise
Interconnected Serialized Architecture for Transmission SystemsIJERD Editor
Transmission system with proposed multiplexer-flip-flops (MUX-FFs) has a high throughput and low-cost solution for serial link transmitters. MUX-FFs is designed with proposed multiplexer-latches that possess a logic function of various combinational circuits and storing capacity of sequential circuits. Pipeline arrangement with MUX-FFs composed of cascaded latches and MUX-latches with this many latch gates for sequential can be removed. Simulation results show that a 8-to-1 serializer with MUX-FFs reduces 63% gate-count compared to traditional pipeline transmission architecture. The measured results shows that the MUX-FFs and the proposed transmission architecture are almost bit error free and high speed in transmission.
DESIGN AND MODELLING OF DIFFERENT SRAM’S BASED ON CNTFET 32NM TECHNOLOGYVLSICS Design
Carbon nanotube field-effect transistor (CNTFET) refers to a field-effect transistor that utilizes a single carbon nanotube or an array of carbon nanotubes as the channel material instead of bulk silicon in the traditional MOSFET structure. Since it was first demonstrated in 1998, there have been tremendous developments in CNTFETs, which promise for an alternative material to replace silicon in future electronics. Carbon nanotubes are promising materials for the nano-scale electron devices such as nanotube FETs for ultra-high density integrated circuits and quantum-effect devices for novel intelligent circuits, which are expected to bring a breakthrough in the present silicon technology. A Static Random Access Memory (SRAM) is designed to plug two needs: i) The SRAM provides as cache memory, communicating between central processing unit and Dynamic Random Access Memory (DRAM). ii) The SRAM technology act as driving force for low power application since SRAM is portable compared to DRAM, and SRAM doesn’t require any refresh current. On the basis of acquired knowledge, we present
different SRAM's designed for the conventional CNTFET. HSPICE simulations of this circuit using Stanford CNTFET model shows a great improvement in power saving.
DESIGN OF LOW WRITE-POWER CONSUMPTION SRAM CELL BASED ON CNTFET AT 32nm TECHN...VLSICS Design
The SRAM which functions as the cache for system-on-chip is vital in the electronic industry. Carbon Nanotube Field Effect Transistor (CNFET) is used for high performance, high stability and low-power circuit designs as an alternative material to silicon in recent years. Therefore Design of SRAM Cell based on CNTFET is important for Low-power cache memory. In cells, the bit-lines are the most power consuming components because of larger power dissipation in driving long bit-line with large capacitance. The cache write consumes considerable large power due to full voltage swing on the bit-line. This Paper proposes a novel 7T SRAM cell based on CNTFET that only depends on one of bit lines for Write operation and reduce the write-power consumption. The read cycle also improved because of careful transistor
sizing. HSPICE simulations of this circuit using Stanford CNFET model shows that 37.2% write power saving, read cycle improvement of 38.6%.
International Journal of Engineering Research and Applications (IJERA) is an open access online peer reviewed international journal that publishes research and review articles in the fields of Computer Science, Neural Networks, Electrical Engineering, Software Engineering, Information Technology, Mechanical Engineering, Chemical Engineering, Plastic Engineering, Food Technology, Textile Engineering, Nano Technology & science, Power Electronics, Electronics & Communication Engineering, Computational mathematics, Image processing, Civil Engineering, Structural Engineering, Environmental Engineering, VLSI Testing & Low Power VLSI Design etc.
Design and Analysis of Power and Variability Aware Digital Summing CircuitIDES Editor
Due to aggressive scaling and process imperfection
in sub-45 nm technology node Vt (threshold voltage) shift is
more pronounced causing large variations in circuit response.
Therefore, this paper presents the analyses of various popular
1-bit digital summing circuits in light of PVT (process, voltage
and temperature) variations to verify their functionality and
robustness. The investigation is carried with ±3ó process
parameters and ±10% VDD (supply voltage) variation by applying
Gaussian distribution and Monte Carlo analysis at 22 nm
technology node on HSPICE environment. Design guidelines
are derived to select the most suitable topology for the design
features required. Transmission Gate (TG)-based digital
summing circuit is found to be the most robust against PVT
variations. Hence, a TG-based digital summing circuit is
implemented using carbon nanotube field effect transistor
(CNFET). This implementation offers tighter spread in
propagation delay (3×), power dissipation (1.14×) and EDP
(energy delay product) (1.1×) at nominal voltage of VDD = 0.95V
compared to MOSFET-based (TG – topology) digital summing
circuit implying its robustness against PVT variations.
Design and Analysis of New Modified Feedthrough Logic (MFTL) Circuits Using C...IJERA Editor
It is a challenging task for a VLSI design engineer to develop low power VLSI circuits, without sacrificing its performance. Feedthrough Logic (FTL) is a new technology which could be considered better than the existing technologies for improving circuit efficiency. Modified Feedthrough Logic (MFTL), offers a better power factor than the FTL logic structures, and also shows an improvement in the speed factor. But the scenario again changes when the design extends to nano scales of device dimension, where many factors which were neglected otherwise need to be given more importance. To avoid or minimize problems like hot carrier effects, electro migration, drain induced barrier lowering and other issues that becomes prominent in nano scale MOSFET‟s, Carbon Nanotube Field Effect Transistor (CNTFET) is considered to be a promising candidate in future integrated circuits. Hence this work extends the advantages of MFTL logic into nano level by incorporating CNTFETs in place of MOSFETs. The modifications have been implemented using CNTFETs of 16nm technology from HSPICE library on a 10 chain inverter stage, an 8 bit RCA and a Vedic multiplier and performance factors like PDP and ADP are compared to that of the conventional MOSFET circuits.
Combining SFBC_OFDM Systems with SVD Assisted Multiuser Transmitter and Multi...IOSR Journals
Abstract: In this work, we exploit the SVD assisted multiuser transmitter (MUT) and multiuser detector (MUD) technique, using downlink (DL) preprocessing transmitter and DL postprocessing receiver matrice .In combination with space frequency block coding (SFBC). And also propose the precoded DL transmission scheme, were the both proposed schemes take advantage of the channel state information (CSI) of all users at the base station (BS), but only of the mobile station (MS)’s own CSI, to decompose the MU MIMO channels into parallel single input single output (SISO), these two proposed schemes are compared to the vertical layered space time (V_BLAST) combined with SFBC (SFBC_VBLAST). Our Simulation results show that the performance of the proposed scheme with DL Zero Forcing (ZF) transmitter for interference canceller outperforms the SFBC_VBLAST and the precoded DL schemes with ZF receiver in frequency selective fading channels. Keywords – Post processing, Preprocessing,, SFBC, SVD, ZF.
DESIGN OF A HIGH PRECISION, WIDE RANGED ANALOG CLOCK GENERATOR WITH FIELD PRO...VLSICS Design
This paper presents a circuit of a high-precision, wide ranged, analog clock generator with on-chip programmability feature using Floating-gate transistors. The programmable oscillator can attain a continuous range of time-periods lying in the programming precision range of Floating Gates. The circuit consists of two sub circuits: Current Generator circuit and Wave Generator circuit. The current of current generator circuit is programmable and mirrored to the wave generator to generate the desired square wave. The topology is well suited to applications like clocking high performance ADCs and DACs as well as used as the internal clock in structured analog CMOS designs. A simulation model of the circuit was built in T-Spice, 0.35µm CMOS process. The circuit results in finely tuned clock with programmability precision of about 13bit [1]. Simulation results show high amount of temperature insensitivity (0.507ns/°C) for a large range of thermal conditions. The proposed circuit can compensate any change in temperature. The circuit design can be operated at low supply voltage i.e., 1v.
IJERA (International journal of Engineering Research and Applications) is International online, ... peer reviewed journal. For more detail or submit your article, please visit www.ijera.com
A REVIEW OF THE 0.09 µm STANDARD FULL ADDERSVLSICS Design
This paper presents power analysis of the seven full adder cells [6] reported as having a low PDP (Power Delay Product), by means of speed, power consumption and area. These full adders were designed upon various logic styles to derive the sum and carry outputs. The existed standard full adders and the proposed full adders [6] are designed and showed the better result comparison. This paper describes how the proposed full adders [6] are better in contrast to the standard full adders. And mentioned how the standard full adders are not giving faithful results . All these full adders designed using TDK 90 nm Technology and simulated using mentor graphics EDA tool with BSIMv3 (model 49). And the layouts of all these full adders designed in Icstation of Mentor Graphics and presented their areas. The total results of prelayout and postlayout simulation are tabulated.
DESIGN OF A PROGRAMMABLE LOW POWER LOW DROP-OUT REGULATORVLSICS Design
A low power programmable low drop-out regulator capable of providing 1V output has been proposed. The
regulator requires a supply voltage of 1.2V and works in the temperature range of -40 to 125 °C in nominal
corner (i.e, normal doping for PMOS and NMOS Field Effect Transistors), yielding a load regulation of
3%. The output voltage level is controlled externally by means of 2 1-bit control signals. The circuit
provides a DC gain of 30 dB and a maximum DC Power Supply Rejection Ratio of -35 dB and a worst case
PSRR of -20 dB. Power dissipation in the load is nearly 100 μW
LEAKAGE REDUCTION TECHNIQUE AND ANALYSIS OF CMOS D FLIP FLOPVLSICS Design
The expansion of battery operated portable device is continuously increasing the demand for low
power, minimum delay and high speed integrated circuits. In many of the portable devices the
standby periods are longer than the active periods and thus consume more power in the standby
state [2]. It is extremely important to reduce the power consumption in the standby mode. In
today’s high performance integrated circuits the leakage power contributes major power
consumption than overall total power consumption. In deep submicron circuits the leakage
power increases than the dynamic power and also in the circuits when there are no transitions at
the input and the transistors are in steady state [1]. Leakage power is mainly due to leakage
current that flows in the circuit when the circuit is operated in sleep or standby mode. The
leakage current is composed of sub-threshold leakage current, gate current, gate leakage current
and reverses biased leakage. Among all leakages, sub-threshold leakage contributes major part of
the leakage. The sub-threshold leakage current of a metal oxide semiconductor device is
expressed as
Where µo is the mobility of electrons/holes, Cox denotes oxide
capacitance of gate per unit area, W and L are width and channel length of MOS device
respectively, Vgs is the gate to source voltage Vt is the thermal voltage and η is the swing
coefficient. The contents of this paper are organized as follows: Section 2 descr
MINIMALLY BUFFERED ROUTER USING WEIGHTED DEFLECTION ROUTING FOR MESH NETWORK ...VLSICS Design
The scalability, modularity and massive parallelism exhibited by Network on chip(NoC) interconnects
make them highly suitable for the inter core communication framework of multiprocessor system-on-chip
(MPSoC) designs. Routers play the most vital role in transferring flits through the network, hence efficient
microarchitecture and cost effective routing algorithms are highly essential for modern NoC routers.
Elimination of buffers and deflection routing help to achieve energy and area efficiency of these routers.
The advantages of bufferless and buffered designs can be combined by using a minimum number of side
buffers to store a fraction of deflection flits in the router. In this paper, we propose a routing algorithm
based on weighted deflection of flits for minimally buffered deflection routers. Evaluations on 4x4 and 8x8
mesh NoC using synthetic workloads as well as benchmark applications demonstrate that deflection rate
and average network latency are significantly reduced in comparison with the state of the art NoC routers.
Performance analysis of the newly proposed algorithm shows that the network saturation point improves
by 26% compared to earlier designs in this domain
Impact of parameter variations and optimization on dg pnin tunnel fetVLSICS Design
The downscaling of conventional MOSFETs has come to its fundamental limits. TFETs are very attractive
devices for low power applications because of their low off-current and potential for smaller sub threshold
slope. In this paper, the impact of various parameter variations on the performance of a DG-PNIN Tunnel
field effect transistor is investigated. In this work, variations in gate oxide material, source doping, channel
doping, drain doping, pocket doping and body thickness are studied and all these parameters are optimized
as performance boosters to give better current characteristics parameters. After optimization with all these
performance boosters, the device has shown improved performance with increased on-current and reduced
threshold voltage and the Ion/Ioff ratio is > 106.
A Sub Threshold Source Coupled Logic Based Design of Low Power CMOS Analog Mu...VLSICS Design
A novel approach for designing Ultra Low Power and wide dynamic range circuit for multiplexing analog
signals is presented. The design operates in weak inversion (Sub threshold) region and uses Source -
Coupled Logic ( SCL) circuit. The bias current of the SCL gates is varied to scale down linearly the power
consumption and the operating frequency. The multiplexer design employs CMOS transistors as
transmission gate with dynamic threshold voltage. The design exhibits low power dissipation, high
dynamic range and good linearity. The design was implemented in 180 nm technology and was operated at
a supply voltage of 400 mV with a bias current ranging in the order of few Pico-amperes. The ON and
OFF resistance of the transmission gate achieved were 27 ohms and 10 M ohms respectively. The power
dissipation achieved is around 0.79 μW for a dynamic range of 1μV to 0.4 V.
SMART MULTICROSSBAR ROUTER DESIGN IN NOCVLSICS Design
This paper gives the innovative idea of designing a router using multicrossbar switch in Network on
Chip(NoC) . In Network-on-Chip architectures the input buffer can consume a large portion of the total
power. Eliminating all input buffer would result in increased power consumption at high load, while
reducing the size of input buffer degrades the performance. In this paper we have proposed a muticrossbar
router design using elastic buffer by combining the advantage of both buffered and buffer less network. In
the proposed design Power Delay Product is reduced by around 37 .91% as compared to baseline router
Optimal Unate Decomposition Method for Synthesis of Mixed CMOS VLSI CircuitsVLSICS Design
Static CMOS logic style is often the choice of designers for synthesizing low power circuits. This style is
robust in terms of noise integrity however, it offers less speed. Domino logic style, as an alternative is often
found in critical paths of various large scale high performance circuits. Yet, due to high switching activity
they are not suitable for synthesis of low power circuits. To achieve both power and speed benefits, we
propose a method of designing circuit using mixed CMOS logic style, taking advantages of both static and
Domino logic styles. For a given circuit, we extract the unate and binate components using a unate
decomposition algorithm. These are optimized such that the resulting circuit is optimum in terms of power,
area and delay. To do this, a multi-objective genetic algorithm is employed. The optimized unate and binate
blocks are mapped using Domino and static cell libraries, respectively. Testing the efficacy of our
approach with ISCAS85 and MCNC89 benchmark circuits showed an improvement of 25% in delay and
22% in transistor count with 12% more power dissipation compared to circuits with only static CMOS
logic. Thus, mixed CMOS circuits are promising in high speed and area constraint applications.
Design of low power cmos logic circuits using gate diffusion input (gdi) tech...VLSICS Design
The Gate diffusion input (GDI) is a novel technique
for low power digital circuit design. This techniq
ue
reduces the power dissipation, propagation delay, a
rea of digital circuits and it maintains low comple
xity
of logic design. In this paper, the 4×1 Multiplexer
, 8×3 Encoder, BCD Counter and Mealy State Machine
were implemented by using Pass Transistors (PT), Tr
ansmission Gate (TG) and Gate Diffusion Input (GDI)
technique and then they were compared with each oth
er for power dissipation. The Multiplexers and
Encoders are combinational circuits and Counters an
d mealy machines are sequential circuits both of th
em
are very important digital systems so power optimiz
ation should be done to those digital circuits. The
whole processes for development of digital circuits
and simulation was done by using the mentor graphi
cs
backend tool. This method can also be extended to t
he processors and other high level designs for
optimization of power dissipation, area and delay i
n order to increase the circuit efficiency.
FGMOS BASED LOW-VOLTAGE LOW-POWER HIGH OUTPUT IMPEDANCE REGULATED CASCODE CUR...VLSICS Design
Floating Gate MOS (FGMOS) transistors can be very well implemented in lieu of conventional MOSFET
for design of a low-voltage, low-power current mirror. Incredible features of flexibility, controllability and
tunability of FGMOS yields better results with respect to power, supply voltage and output swing. This
paper presents a new current mirror designed with FGMOS which exhibit high output impedance, higher
current range, very low power dissipation and higher matching accuracy. It achieves current range of up to
1500 µA, high output impedance of 1.125 TΩ, bandwidth of 4.1 MHz and dissipates power as low as 10.56
µW. The proposed design has been simulated using Cadence Design Environment in 180 nm CMOS
process technology with +1.0 Volt single power supply
A RAIL-TO-RAIL HIGH SPEED CLASS-AB CMOS BUFFER WITH LOW POWER AND ENHANCED SL...VLSICS Design
A rail-to-rail class-AB CMOS buffer is proposed in this paper to drive large capacitive loads. A new
technique is used to reduce the leakage power of class-AB CMOS buffer circuits without affecting dynamic
power dissipation .The name of applied technique is LECTOR, which gives the high speed buffer with the
reduced low power dissipation (1.05%) and reduced area (2.8%). The proposed buffer is simulated at
45nm CMOS technology and the circuit is operated at 3V supply with cadence software. This analog circuit
is performed with extremely low leakage current as well as high current driving capability for the large
input voltages. The proposed paper is achieved very high speed with very low propagation delay range
i.e.(292×10-12). So the delay of the circuit is reduced to 10%. The settling time of this circuit is reduced by
24% (in ns) at 3V square wave input. The measured quiescent current is 41μA
Vlsics040303LOW POWER DUAL EDGE - TRIGGERED STATIC D FLIP-FLOPVLSICS Design
This paper enumerates new architecture of low power dual-edge triggered Flip-Flop (DETFF) designed at
180nm CMOS technology. In DETFF same data throughput can be achieved with half of the clock
frequency as compared to single edge triggered Flip-Flop (SETFF). In this paper conventional and
proposed DETFF are presented and compared at same simulation conditions. The post layout experimental
results comparison shows that the average power dissipation is improved by 48.17%, 41.29% and 36.84%
when compared with SCDFF, DEPFF and SEDNIFF respectively and improvement in PDP is 42.44%,
33.88% and 24.69% as compared to SCDFF, DEPFF and SEDNIFF respectively. Therefore the proposed
DETFF design is suitable for low power and small area applications
DESIGN OF IMPROVED RESISTOR LESS 45NM SWITCHED INVERTER SCHEME (SIS) ANALOG T...VLSICS Design
This work presents three different approaches which eliminates the resistor ladder completely and hence
reduce the power demand drastically of a Analog to Digital Converter. The first approach is Switched
Inverter Scheme (SIS) ADC; The test result obtained for it on 45nm technology indicates an offset error of
0.014 LSB. The full scale error is of -0.112LSB. The gain error is of 0.07 LSB, actual full scale range of
0.49V, worst case DNL & INL each of -0.3V. The power dissipation for the SIS ADC is 207.987 μwatts;
Power delay product (PDP) is 415.9 fWs, and the area is 1.89μm2. The second and third approaches are
clocked SIS ADC and Sleep transistor SIS ADC. Both of them show significant improvement in power
dissipation as 57.5% & 71% respectively. Whereas PDP is 229.7 fWs and area is 0.05 μm2 for Clocked SIS
ADC and 107.3 fWs & 1.94 μm2 for Sleep transistor SIS ADC.
Multisim design and simulation of 2.2 g hz lna for wireless communicationVLSICS Design
This paper presents the work done on the design and simulation of a high frequency low noise amplifier for
wireless communication. The purpose of the amplifier is to amplify the received RF path of a wireless
network. With high gain, high sensitivity and low noise using Bipolar Junction transistor (BJT). The design
methodology requires analysis of the transistor for stability, proper matching, network selection and
fabrication. The BJT transistor was chosen for the design of the LNA due to its low noise and good gain at
high frequency. These properties were confirmed using some measurement techniques including Network
Analyzer, frequency analyzer Probe and Oscilloscope for the simulation and practical testing of the
amplifier to verify the performance of the designed High frequency Low noise amplifier. The design goals
of noise figure of 0.52dB-0.7dB and bias conditions are Vcc = 3.5 V and Icc= 55 mA to produce 16.8 dB
gain across the 0.4–2.2GHz band.
SINGLE-PORT FIVE-TRANSISTOR SRAM CELL WITH REDUCED LEAKAGE CURRENT IN STANDBYVLSICS Design
In this paper, a new single-port five-transistor (5T) Static Random Access Memory (SRAM) cell with
integrated read/write assist is proposed. Amongst the assist circuitry, a voltage control circuit is coupled to
the sources corresponding to driver transistors of each row memory cells. This configuration is aimed to
control the source voltages of driver transistors under different operating modes. Specifically, during a
write operation, by means of sizing the driver transistor close to bitline to resolve the write ‘1’ issue. In
addition, associated with a two-stage reading mechanism to increase the reading speed and to avoid
unnecessary power consumption. Finally, with the standby start-up cir
Evolution of Structure of Some Binary Group-Based N-Bit Compartor, N-To-2N De...VLSICS Design
Reversible logic has attracted substantial interest due to its low power consumption which is the main
concern of low power VLSI systems. In this paper, a novel 4x4 reversible gate called inventive gate has
been introduced and using this gate 1-bit, 2-bit, 8-bit, 32-bit and n-bit group-based reversible comparator
have been constructed with low value of reversible parameters. The MOS transistor realizations of 1-bit, 2-
bit, and 8-bit of reversible comparator are also presented and finding power, delay and power delay
product (PDP) with appropriate aspect ratio W/L. Novel inventive gate has the ability to use as an n-to-2n
decoder. Different novel reversible circuit design style is compared with the existing ones. The relative
results shows that the novel reversible gate wide utility, group-based reversible comparator outperforms
the present style in terms of number of gates, garbage outputs and constant input.
DESIGNING HIGH-SPEED, LOW-POWER FULL ADDER CELLS BASED ON CARBON NANOTUBE TEC...VLSICS Design
This article presents novel high speed and low power full adder cells based on carbon nanotube field effect transistor (CNFET). Four full adder cells are proposed in this article. First one named CN9P4G) and second one (CN9P8GBUFF) utilizes 13 and 17 CNFETs respectively. Third design that we named CN10PFS uses only 10 transistors and is full swing. Finally, CN8P10G uses 18 transistors and divided into two modules, causing Sum and Cout signals are produced in a parallel manner. All inputs have been used straight, without inverting. These designs also used the special feature of CNFET that is controlling the threshold voltage by adjusting the diameters of CNFETs to achieve the best performance and right voltage levels. All simulation performed using Synopsys HSPICE software and the proposed designs are compared to other classical and modern CMOS and CNFET-based full adder cells in terms of delay, power consumption and power delay product.
HIGH SPEED MULTIPLE VALUED LOGIC FULL ADDER USING CARBON NANO TUBE FIELD EFFE...VLSICS Design
High speed Full-Adder (FA) module is a critical element in designing high performance arithmetic circuits. In this paper, we propose a new high speed multiple-valued logic FA module. The proposed FA is constructed by 14 transistors and 3 capacitors, using carbon nano-tube field effect transistor (CNFET) technology. Furthermore, our proposed technique has been examined in different voltages (i.e., 0.65v and 0.9v). The observed results reveal power consumption and power delay product (PDP) improvements compared to existing FA counterparts.
A NOVEL FULL ADDER CELL BASED ON CARBON NANOTUBE FIELD EFFECT TRANSISTORSVLSICS Design
Presenting a novel full adder cell will be increases all the arithmetic logic unit performance. In this paper, We present two new full adder cell designs using carbon nanotube field effect transistors (CNTFETs). In the first design we have 42 transistors and 5 pull-up resistance so that we have achieved an improvement in the output parameters. Simulations were carried out using HSPICE based on the CNTFET model with 0.9V VDD. The denouments results in that we have a considerable improvement in power, Delay and power delay product than the previous works.
ENERGY EFFICIENT FULL ADDER CELL DESIGN WITH USING CARBON NANOTUBE FIELD EFFE...VLSICS Design
Full Adder is one of the critical parts of logical and arithmetic units. So, presenting a low power full adder cell reduces the power consumption of the entire circuit. Also, using Nano-scale transistors, because of their unique characteristics will save energy consumption and decrease the chip area. In this paper we presented a low power full adder cell by using carbon nanotube field effect transistors (CNTFETs). Simulation results were carried out using HSPICE based on the CNTFET model in 32 nanometer technology in Different values of temperature and VDD.
Carbon Nanotube Based Circuit Designing: A ReviewIJERDJOURNAL
ABSTRACT:- A new material and its associated device which have potential to replace Si and CMOS and can extend the scalability of devices below 22 nm is the carbon nanotube (CNT) and its associated transistor, the carbon nanotube field effect transistor (CNTFET). CNT possesses unique properties that make it a promising future material. Similarly, CNTFET is a promising basic building block to complement the existing silicon based MOSFET and can result in the extension of the validity of Moore's law further. This paper presents the state of the art literature related to carbon nanotubes, carbon nanotube field effect transistors and CNTFET based circuit designing. A review of CNTFET based analog and digital circuits has been presented. It has been observed that the use of CNTFET can improve the performance of both analog and digital circuits. The work will be of utmost use to the people working in the field of CNT based analog and digital circuit designing.
This paper proposes a variation – tolerant dual-diameter CNFET-based 7T (seven transistor) SRAM (static random access memory) cell. The use of appropriate DCNT (diameter of CNFET) and hence Vt of CNFETs is a critical piece of our design strategy. In this work, dual-Vt and dual-diameter CNFETs have been used using suitable chiral vectors for appropriate transistors. It also investigates the impact of process, voltage and temperature variations on its design metrics and compares the results with its counterpart − CMOS-based 7T SRAM cell and standard 6T SRAM cell (only few parameters). The proposed SRAM cell offers 1.35× and 1.25× improvement in standby power on an average @ VDD = 1 V and 0.9 V respectively, 30% improvement in SNM (Static Noise Margin) over CMOS-based 7T cell. Proposed design outperforms 6T in terms of 71.4% improvement in RSNM and shows same read stability as its CMOS counterpart, It shows its robustness by offering 1.4× less spread in TRA (read access time) at 1 V and 1.2× less spread in TRA at 0.9 V than that of its CMOS counterpart at the expense of 1.6× read delay. The proposed bitcell also exhibits higher performance while writing (takes 1.3× and 1.2× less TWA (write access time) @ VDD = 1 V and VDD= 0.9 V respectively). It also proves its robustness against process variations by featuring tighter spread in TWA variability (1.4× and 1.2× @ VDD= 1 V and 0.9 V respectively).
Performance analysis of cmos comparator and cntfet comparator designeSAT Publishing House
IJRET : International Journal of Research in Engineering and Technology is an international peer reviewed, online journal published by eSAT Publishing House for the enhancement of research in various disciplines of Engineering and Technology. The aim and scope of the journal is to provide an academic medium and an important reference for the advancement and dissemination of research results that support high-level learning, teaching and research in the fields of Engineering and Technology. We bring together Scientists, Academician, Field Engineers, Scholars and Students of related fields of Engineering and Technology
Energy Efficient Full Adder Cell Design with Using Carbon Nanotube Field Effe...VLSICS Design
Full Adder is one of the critical parts of logical and arithmetic units. So, presenting a low power full adder
cell reduces the power consumption of the entire circuit. Also, using Nano-scale transistors, because of
their unique characteristics will save energy consumption and decrease the chip area. In this paper we
presented a low power full adder cell by using carbon nanotube field effect transistors (CNTFETs).
Simulation results were carried out using HSPICE based on the CNTFET model in 32 nanometer
technology in Different values of temperature and VDD.
CNTFET Based Analog and Digital Circuit Designing: A ReviewIJMERJOURNAL
ABSTRACT: Silicon has been a material of choice for the last many decades and more than 95% of electronics devices are from silicon. However, silicon has reached to its saturation level and extracting more and more performance is difficult and costly now. A new material which has a potential to replace Si and can extend the scalability of devices below 22 nm is the carbon nanotube (CNT). CNT is a wonderful material possesses unique properties that make it a promising future material. CNT based field effect transistor (Cntfet) is a promising basic building block to complement the existing silicon based MOSFET and can result in the extension of the validity of Moore's law further. CNTFT has been used extensively in realizing electronics circuits. This paper presents the state of the art literature related to carbon nanotubes, carbon nanotube field effect transistors and CNTFET based circuit designing. A review of Cntfet based analog and digital circuits has been presented. It has been observed that the use of CNTFET has improved the performance of both analog and digital circuits. The work will be very useful to the people working in the field of CNT based analog and digital circuit designing.
Performance analysis of cntfet and mosfet focusing channel length, carrier mo...IJAMSE Journal
Enhancement of switching in nanoelectronics, Carbon Nano Tube (CNT) could be utilized in nanoscaled Metal Oxide Semiconductor Field Effect Transistor (MOSFET). In this review, we present an in depth discussion of performances Carbon Nanotube Field Effect Transistor (CNTFET) and its significance in nanoelectronic circuitry in comparison with Metal Oxide Semiconductor Field Effect Transistor(MOSFET). At first, we have discussed the structural unit of Carbon Nanotube and characteristic electrical behaviors beteween CNTFET and MOSFET. Short channel effect and effects of scattering and electric field on mobility of CNTFET and MOSFET have also been discussed. Besides, the nature of ballistic transport
and profound impact of gate capacitance along with dielectric constant on transconductance have also
have been overviewed. Electron ballistic transport would be the key in short channel regime for high speed
switching devices. Finally, a comparative study on the characteristics of contact resistance over switching
capacity between CNTFET and MOSFET has been addressed.
Designing of Low Power CNTFET Based D Flip-Flop Using Forced Stack TechniqueIJERA Editor
Low Power devices in small packages is the need of present and future electronic devices. Electronics Industry is making devices which can be planted in human bodies. CMOS Technology won‟t be able to deliver such devices because it shows short channel effects in Nano scale. So, to overcome the problems of CMOS technology we use CNTs (Carbon Nano Tubes). In electronic devices, power is consumed by various elements like flip-flop, latches, clock sources. So in order to reduce power of a system we used to reduce power consumed by flip-flops. In this paper we design an existing flip-flop “Low power clocked pass transistor flip-flop (LCPTFF)” on CNTFET using Stanford CNTFET model for reference. We propose a design of CNTFET based Forced Stack Low Power Clocked Pass Transistor Flip-Flop (CN-FS-LCPTFF) and observe 12% to 25% power reduction in various conditions like temperature change, CNTFET diameter change, and different voltage supply.
AN EFFICIENT CNTFET-BASED 7-INPUT MINORITY GATEVLSICS Design
Complementary metal oxide semiconductor technology (CMOS) has been faced critical challenges in nanoscale regime. CNTFET (Carbon Nanotube Field effect transistor) technology is a promising alternative for CMOS technology. In this paper, we proposed a novel 7-input minority gate in CNTFET technology that has only 9 CNTFETs. Minority function is utilized in the voting systems for decision making and also it is used in data mining. This proposed 7-input minority gate is utilized less fewer transistors than the conventional CMOS method which utilizes many transistors for implementing sum of products. By means of this proposed 7-input minority gate, a 4-input NAND gate can be implemented, which gets better the conventional design in terms of delay and energy efficiency and has much more deriving power at its output.
Area Efficient Pulsed Clocks & Pulsed Latches on Shift Register TannerIJMTST Journal
This paper introduced a design and implementation of shift register using pulsed latches and flip-flops. As
flip-flop based shift registers requires a clock signal to operate. Multistage flip-flop processes with high clock
switching activity and then increases time latency. Flip-flops also engages fifty percent power out of total
circuit power in clocking. To reduce such power consumptions and to achieve area optimization flip-flops are
replaced by pulsed latches. The design is implemented with 250nm technology in Tanner EDA Tool. With
Vdd=1.8V, Freq=100MHz. Average power of total circuit is 0.465uW and delay of 0.312 us.
Design of carbon nanotube field effect transistor (CNTFET) small signal model IJECEIAES
The progress of Carbon Nanotube Field Effect Transistor (CNTFET) devices has facilitated the trimness of mobile phones, computers and all other electronic devices. CNTFET devices contribute to model these electronics instruments that require designing the devices. This research consists of the design and verification of the CNTFET device's small signal model. Scattering parameters (S-parameters) is extracted from the CNTFET model to construct equivalent small model circuit. Current sources, capacitors and resistors are involved to evaluate this equivalent circuit. S-parameters and small signal models are elaborated to analyze using a technique to form the small signal equivalent circuit model. In this design modeling process, at first intrinsic device's Y-parameters are determined. After that series of impedances are calculated. At last, Y-parameters model are transformed to add parasitic capacitances. The analysis result shows the acquiring high frequency performances are obtained from this equivalent circuit.
Digital multipliers are among the most critical arithmetic functional units. The overall performance of these systems depends on the throughput of the multiplier. Meanwhile, the negative bias temperature instability effect occurs when a pMOS transistor is under negative bias (Vgs = −Vdd), increasing the threshold voltage of the pMOS transistor, and reducing multiplier speed. A similar phenomenon, positive bias temperature instability, occurs when an nMOS transistor is under positive bias. Both effects degrade transistor speed, and in the long term, the system may fail due to timing violations. Therefore, it is important to design reliable high performance multipliers. In this paper, we propose an aging-aware multiplier design with novel adaptive hold logic (AHL) circuit. The multiplier is able to provide higher throughput through the variable latency and can adjust the AHL circuit to mitigate performance degradation that is due to the aging effect. Moreover, the proposed architecture can be applied to a column- or row-bypassing multiplier. The experimental results show that our proposed architecture with 16 ×16 and 32 ×32 column-bypassing multipliers can attain up to 62.88% and 76.28% performance improvement, respectively, compared with 16×16 and 32×32 fixed-latency column-bypassing multipliers. Furthermore, our proposed architecture with 16 × 16 and 32 × 32 row-bypassing multipliers can achieve up to 80.17% and 69.40% performance improvement as compared with 16×16 and 32 × 32 fixed-latency row-bypassing multipliers.
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About
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Indigenized remote control interface card suitable for MAFI system CCR equipment. Compatible for IDM8000 CCR. Backplane mounted serial and TCP/Ethernet communication module for CCR remote access. IDM 8000 CCR remote control on serial and TCP protocol.
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Indigenized remote control interface card suitable for MAFI system CCR equipment. Compatible for IDM8000 CCR. Backplane mounted serial and TCP/Ethernet communication module for CCR remote access. IDM 8000 CCR remote control on serial and TCP protocol.
• Remote control: Parallel or serial interface
• Compatible with MAFI CCR system
• Copatiable with IDM8000 CCR
• Compatible with Backplane mount serial communication.
• Compatible with commercial and Defence aviation CCR system.
• Remote control system for accessing CCR and allied system over serial or TCP.
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Immunizing Image Classifiers Against Localized Adversary Attacksgerogepatton
This paper addresses the vulnerability of deep learning models, particularly convolutional neural networks
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the immunity of models against localized universal attacks by up to 40%. We evaluate our proposed approach
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and CIFAR-100) and ImageNet Large Scale Visual Recognition Challenge (ILSVRC12) datasets, showcasing
accuracy improvements over previous techniques. The results indicate that the combination of the volumetric
input and curriculum learning holds significant promise for mitigating adversarial attacks without necessitating
adversary training.
Welcome to WIPAC Monthly the magazine brought to you by the LinkedIn Group Water Industry Process Automation & Control.
In this month's edition, along with this month's industry news to celebrate the 13 years since the group was created we have articles including
A case study of the used of Advanced Process Control at the Wastewater Treatment works at Lleida in Spain
A look back on an article on smart wastewater networks in order to see how the industry has measured up in the interim around the adoption of Digital Transformation in the Water Industry.
AKS UNIVERSITY Satna Final Year Project By OM Hardaha.pdf
Designing High-Speed, Low-Power Full Adder Cells Based on Carbon Nanotube Technology
1. International Journal of VLSI design & Communication Systems (VLSICS) Vol.5, No.5, October 2014
DESIGNING HIGH-SPEED, LOW-POWER FULL
ADDER CELLS BASED ON CARBON NANOTUBE
TECHNOLOGY
Mehdi Masoudi1, Milad Mazaheri1, Aliakbar Rezaei1 and Keivan Navi4
1Department of Computer Engineering,
Science and Research Branch of IAU, Tehran, Iran
4Department of Electrical and Computer Engineering,
Shahid Beheshti University, Tehran, Iran
ABSTRACT
This article presents novel high speed and low power full adder cells based on carbon nanotube field effect
transistor (CNFET). Four full adder cells are proposed in this article. First one (named CN9P4G) and
second one (CN9P8GBUFF) utilizes 13 and 17 CNFETs respectively. Third design that we named
CN10PFS uses only 10 transistors and is full swing. Finally, CN8P10G uses 18 transistors and divided into
two modules, causing Sum and Cout signals are produced in a parallel manner. All inputs have been used
straight, without inverting. These designs also used the special feature of CNFET that is controlling the
threshold voltage by adjusting the diameters of CNFETs to achieve the best performance and right voltage
levels. All simulation performed using Synopsys HSPICE software and the proposed designs are compared
to other classical and modern CMOS and CNFET-based full adder cells in terms of delay, power
consumption and power delay product.
KEYWORDS
Full Adder, CNT, Carbon Nanotube Field Effect Transistor, High Speed, Low Power, High Performance &
Power Delay Product
1. INTRODUCTION
In digital electronic world, delay and power consumption improvement are the most important
performance parameters of a circuit. To reach this goal, we can reduce scaling of the feature size.
In complementary metal oxide semiconductor (CMOS) technology, reducing the length of
channel to below about 65nm leads to critical problems and challenges such as decreasing gate
control, short channel effect, high power density, high sensitivity to process variation and
exponential leakage current increment [1]. For this reasons reducing the transistors size finally
will stop at a point, leading to taking advantage of new technologies that do not have above
problems may be felt. Therefore, new technologies such as benzene rings, quantum dot cellular
automata (QCA), single electron transistor (SET), carbon nanotube field effect transistor
(CNFET) and others have risen up [2-7].
Special properties of the carbon nanotubes (CNTs) cause to be utilized in various industries such
as nanoelectronic. Some of these features are high thermal conductivity, high tensile strength,
super conductivity, extreme rigidity and be conductor or semiconductor basis on structure.
DOI : 10.5121/vlsic.2014.5503 31
2. International Journal of VLSI design & Communication Systems (VLSICS) Vol.5, No.5, October 2014
Carbon nanotube field effect transistor (CNFET) is an appropriate alternative for CMOS. Owing
to similarity between CNFET and CMOS in case of operation principle and the device structure,
we can perform the established CMOS design infrastructure and CMOS manufacturing process in
the CNFET technology [2]. CNFET is one of the molecular devices that avoid most fundamental
silicon transistor restrictions and have ballistic or near ballistic transport in its channel and have
high current carry ability [6-8]. Generally CNFET is faster and use lesser power consumption
compared to silicon-based MOSFET and for this reason it is very suitable for high frequency and
low voltage applications. Another useful trait of CNFET is that P-CNFET and N-CNFET have
the same mobility and the same current drive capability, which is very important for transistor
sizing in the complex circuits [9].
Recently some designs have been performed by CNFETs such as Galois field circuits [10],
multiple valued logic circuits [1, 10, 11], interconnection networks [12-14] and CNFET full
adders [13, 15]. Full adder cell is a basic element for complex circuits also most of arithmetic
operations can be implemented by full adder cells. So performance increment of full adder causes
to improve system performance [16]. Many efforts have been done to increase the efficiency of
this element. Full adder performance improvement can be performed in various stages such as
algorithm, circuit and technology. In this paper we present design details of high speed and low
power full adder cells based on nanotechnology.
The rest of this paper is organized as follows. In section 2 a brief description about CNFET is
provided. Previous works are presented in section 3. The proposed full adder cells are presented
in section 4. Experimental results, analyses and comparisons are presented in section 5 and finally
section 6 concludes the paper.
2. CARBON NANOTUBE FIELD EFFECT TRANSISTORS (CNFETS)
Carbon nanotube in theoretical definition is a sheet of graphite which is rolled up along a
wrapping vector [17]. CNT can be single-wall (SWCNT) or multi-wall (MWCNT) [18]. Single-wall
CNT is made by one layer of graphite and multi-wall CNT is made by more than one layer
of graphite, then it is rolled up and all cylinders center is same. Carbon nanotubes are represented
by a vector is called chirality vector. According to Figure 1, chirality vector is shown by and
is obtained by: where are lattice unit vectors and are positive
integers which specify the tube’s structure [19]. Depending on and we have three different
kinds of nanotube: zigzag, armchair and chiral (Figure 1(a)) and the SWCNT has different
manners such that if then SWCNT will be conductor otherwise SWCNT will
be semiconductor [6, 20]. Conductive CNT is used as nanowires and semiconductive CNT is
applied as transistor channel [6]. In CNFETs, one or more semiconductive SWCNTs can be used
and a typical CNFET is illustrated in Figure 1(b).
32
Figure 1. (a) Representation of a SWNT by a chiral vector [8]¸ (b) schematic of CNFET [21]
3. International Journal of VLSI design & Communication Systems (VLSICS) Vol.5, No.5, October 2014
of CNFET is calculated approximately based on following equation:
where pitch is the distance between the centers of two
neighbor SWCNTs under the same gate, is the minimum width of the gate and N is the
number of nanotubes.
33
The diameter of nanotube is given by Equation (1) [22].
The threshold voltage of CNFET is an inverse function of the diameter of CNT. We use this
ability to control by changing the . The CNFET threshold voltage ( ) is calculated
based on Equation (2) [22].
Where parameter is the band gap energy, parameter a is the carbon-to-carbon
atom distance, the carbon bond energy, e is the unit electron charge and
is the diameter of CNT.
Depending on the type of connections between source and drain with CNT channel and type of
source, drain and gate, there are three main CNFETs. The first type is schottky barrier CNFET
(SB-CNFET), which the CNT directly contacts to metal source. Schottky barrier junction limits
the transconductance in the ON state, thus ION/IOFF ratio becomes rather low. SB-CNFET is
appropriate for medium to high-performance applications. The second type of CNFET is the
band-to-band tunneling CNFET (T-CNFET). T-CNFET has super cut-off characteristics and low
ON current. These specifications make it suitable for low power and subthreshold application but
it is not appropriate for very high speed applications. The third type of CNFET is MOSFET-like
CNFETs. Source and drain are doped with positive impurities, so a semiconductor-semiconductor
junction between source-drain and channel is made and source-channel junction is not schottky
barrier. As a result MOSFET-like CNFETs have high ON current, high ION/IOFF ratio and
scalability that make it suitable for high performance applications [6, 23, 24]. In this paper we
employ MOSFET-like CNFETs for all proposed designs.
3. PREVIOUS WORKS
As mentioned before, CNFET is a suitable alternative for silicon-based technology that does not
have MOSFET problems. Many full adder designs by MOSFET and CNFET are proposed so far
and each of them has their advantages and disadvantages. In this paper we select 5 popular full
adder cells that three of them are designed with 32nm MOSFET technology and two of them
designed with 32nm CNFET technology. In this section a brief description of some prior works is
presented.
First one is conventional CMOS full adder (CCMOS). It has 28 transistors and consumes high
power and area[25, 26]. This design is based on standard CMOS topology and has full swing
4. International Journal of VLSI design & Communication Systems (VLSICS) Vol.5, No.5, October 2014
output that increases noise margin and reliability. Because of using high number of PMOS in pull
up network, this design has high input capacitance, leading to high delay and dynamic power
consumption. Although, using inverters on the output nodes decreases the rise-time and fall-time
delay and increases the driving ability. Next sample full adder cell is TG-CMOS which has 20
transistors [27]. This full adder uses conventional transmission gates on its structure. In TG-CMOS
full adder all outputs are obtained based on XOR/XNOR gates and afterwards uses MUX
structure. This design has low power dissipation because of using transmission gate but utilizes
high number of transistors.
Next design, CMOS-Bridge uses 24 transistors and takes advantage of the high-performance
bridge structure [28]. In this design Cout signal is produced based on a CMOS style and Sum
signal is generated from Cout by means of a bridge circuit. In addition, to generate Cout and Sum
from and and for enhancing the driving capability, two inverters are utilized at the
output nodes.
Next full adder is proposed in [29] and has been designed by CNFETs (Figure 2(a)) (we named it
CNT-FA1 in this paper). It uses 14 transistors plus three capacitors. This design is based on
majority function and is adjusted by changing the diameters of CNFETs. CNT-FA1 provides
good delay and power properties.
Full adder cell that proposed in [30] (we named it CNT-FA2 in this paper) uses majority function
plus inverter to generate and also by meaning to adjusting the and as result, adjusting
the Vth in PCNFET and NCNFET, NAND and NOR has been created by inverter structure
(Figure 2(b)). This design uses two pass transistors after NAND and NOR to generate
output and using pass transistor causes to the output does not be full swing but the final inverter
fixes it and makes full swing output. This design is symmetric and delay, power consumption and
PDP parameters are suitable.
34
Figure 2. (a) CNT-FA1 full adder, (b) CNT-FA2 full adder
4. PROPOSED DESIGNS
In this section we propose four new full adder cells. The logic formula for a one-bit full adder is
shown in Equation (3). The inputs are A, B, C (C is carry input) and outputs are Sum and Cout.
XOR is shown by symbol.
5. International Journal of VLSI design & Communication Systems (VLSICS) Vol.5, No.5, October 2014
According to Equation (3), we can generate Sum by using XOR twice. First, A and B become
XOR and then the result of previous stage become XOR with C. A XOR module is illustrated in
Figure 3. This module uses two pass transistors and two pull down transistors. Pass transistors can
cover the 3 states of inputs that are 00, 01, 10 and one more remained state (11) is handled by pull
down network. By using twice of this module, is obtained. All proposed designs use
this module to generate Sum signal.
35
Figure 3. XOR module
According to Equation (4), we can use to generate Cout. So in the first proposed design, we
have used a transmission gate to lead C into Cout when is high. In this status two states
remain, when both A and B are high or both A and B are low. First one covered by a pair series of
NCNFETs and second one covered by another pair series of PCNFETs. This design uses 13
transistors. We named it CN9P4G and shown in Figure 4.
Figure 4. CN9P4G (Proposed1)
This design and others that will present later, depending on input values can have threshold losing
in output voltages and are not full swing. For solving this problem we have some method such
asusing transmission gate instead of pass transistor or using output buffers, but these methods
cause to increase transistor using and critical path and in result increasing power consumption and
delay. CNFETs have a special property that can be used for this case. According to Equation (2),
6. International Journal of VLSI design & Communication Systems (VLSICS) Vol.5, No.5, October 2014
the threshold voltage is inversely proportional to the diameter of its CNT. So by increasing the
diameter of CNT, can be reduced. Decreasing of leads to better driving capability and
higher speed and the full swing problem can be solved. According to Equation (1), is
obtained by chiral vector with pair.
So as a result we use for all PCNFETs and NCNFETs. By
this amount of diameter, will be very low.
According to simulation results, voltage drop is very lower than the value of the threshold. This is
due to the very high-speed operation of CNFETs with large diameters in subthreshold region.
Larger CNT diameter leads to have smaller band gap, and smaller band gap leads to higher on-currents
and shorter propagation delay. In addition, CNFETs with smaller band gap and as result
smaller threshold voltage, are less sensitive to process variations and it leads to better
manufacturability [31].
In first proposed design (CN9P4G) two states are exist that Cout is not full swing, when
ABC=001 or ABC=110. When these input patterns occur, pass transistors will have current in
subthreshold region and causes to destroyed output voltage. To fix this problem we use a buffer in
Cout output in second proposed design, CN9P8GBUFF (Figure 5). Using buffer causes to
increase critical path to 5 transistors and consequently more power consumption and delay rather
than first design (CN9P4G). Transistors using is also increased to 17, but outputs become full
swing.
36
Figure 5. CN9P8GBUFF (Proposed2)
In proposed design 3, Cout is generated in another way and transistor using decrement is also
significant (Figure 6). In this design we implement Equation (5) by a NCNFET and a PCNFET
pass transistor.
7. International Journal of VLSI design & Communication Systems (VLSICS) Vol.5, No.5, October 2014
Total used transistors are 10. This design due to using large diameter CNFETs
37
is full swing.
Figure 6. CN10PFS (Proposed3)
Next design (CN8P10G) includes two modules to generate Sum and Cout signals separately
(Figure 7). CN8P10G has a parallel manner in producing Sum and Cout and uses 18 transistors.
Sum made by using XOR module (Figure 3) twice like other proposed designs. Cout signal has
been generated by using Equation (6). Also all output voltages are full swing.
Figure 7. CN8P10G (Proposed4)
5. SIMULATION RESULTS ANALYSIS AND COMPARISON
All proposed designs and previous designs were described in section 3 and 4, have been
simulated by Synopsys HSPICE 2010. CMOS-based circuits are simulated using 32nm CMOS
technology and CNFET-based circuits are simulated using compact SPICE model for 32nm [8,
32-34]. Compact SPICE model has been designed for unipolar MOSFET-like CNFET devices
and each transistor can have one or more CNTs. This model considered schottky barrier effects,
parasitics, CNT charge screening effects, CNT Source/Drain and gate resistances and
8. International Journal of VLSI design & Communication Systems (VLSICS) Vol.5, No.5, October 2014
capacitances. The parameters of this CNFET model, corresponding values and a brief description
are presented in Table 1.
38
Table 1. CNFET model parameters
Parameter Description Value
Lch Physical channel length 32nm
Lgeff The mean free path in the intrinsic CNT channel 100nm
Lss The length of doped CNT source-side extension region 32nm
Ldd The length of doped CNT drain-side extension region 32nm
Kgate The dielectric constant of high-k top gate dielectric material 16
Tox The thickness of high-k top gate dielectric material 4nm
Csub The coupling capacitance between the channel region and the substrate 40 pF/m
Efi The fermi level of the doped S/D tube 6 eV
All four proposed designs output waves are shown in Figure 8. As can be seen CN9P4G is not
full swing for 001 and 110 input patterns and all other designs are full swing.
Figure 8. The input and output signals of 4 proposed full adder
9. International Journal of VLSI design & Communication Systems (VLSICS) Vol.5, No.5, October 2014
Main comparison factor in this paper is PDP (Power Delay Product), so in variation of load
capacitor, frequency, power voltage and temperature, all PDPs have been calculated.
Table 2 shows simulation results for all designs at 250 MHz frequency, 2.1 femto Farad load
capacitor and 25° temperature in variation of supply voltage from 0.5v to 0.8v. Delay, power
consumption and PDP of our designs have been shown in this Table. Our proposed full adders
have lower delay, power and PDP rather than other mentioned previous circuits. For example,
according to Table 2, PDP of CN8P10G at 2.1 femto Farad capacitor and power voltage 0.65 has
86.1% improvement rather than CMOS-bridge, 80.9% improvement rather than C-CMOS, 76.9%
improvement rather than TG-CMOS, 79.3% improvement rather than CNT-FA1 and 66.7%
improvement rather than CNT-FA2.
39
Table 2. Simulation results at frequency=250MHz and load capacitor=2.1 femto Farad
Vdd=0.5 v Vdd=0.65 v Vdd=0.8 v
Delay (E-10 s)
CMOS-Bridge 4.9264 1.926 12.002
CCMOS 3.9300 1.444 9.4001
TG-CMOS 2.3753 0.88103 5.4938
CNT-FA1 3.0340 0.8747 4.8074
CNT-FA2 2.1070 0.79694 5.8841
CN9P4G(P1) 0.40743 0.29928 0.27675
CN9P8GBUFF(P2) 0.43620 0.32865 0.27409
CN10PFS(P3) 0.45567 0.34379 0.28079
CN8P10G(p4) 0.27607 0.27331 0.86408
Power (E-7 w)
CMOS-Bridge 1.6830 3.0314 5.2361
CCMOS 1.6369 2.926 5.0607
TG-CMOS 2.1678 3.9688 7.6154
CNT-FA1 1.5523 4.4724 3.1228
CNT-FA2 1.3761 3.0466 1.6917
CN9P4G(P1) 1.9720 3.0276 4.3138
CN9P8GBUFF(P2) 2.1721 3.3545 4.9056
CN10PFS(P3) 1.8339 2.8507 4.1671
CN8P10G(p4) 1.8620 2.9572 4.3012
PDP (E-17 J)
CMOS-Bridge 8.2742 5.8384 6.2844
CCMOS 6.4329 4.2253 4.7571
TG-CMOS 5.1492 3.4966 4.1837
CNT-FA1 4.7097 3.912 15.013
CNT-FA2 2.8995 2.4279 9.9541
CN9P4G(P1) 0.80345 0.9061 1.1938
CN9P8GBUFF(P2) 0.94746 1.1024 1.3446
CN10PFS(P3) 0.83566 0.98004 1.1701
CN8P10G(p4) 0.51404 0.80823 3.7166
In the next evaluation, load capacitor is increased from 1.4 to 4.9 femto Farad and other
parameters are fixed at Vdd=0.65V, frequency=250MHz and temperature=25°. All delays,
powers and PDPs are calculated and are shown in Figure 9, Figure 10 and Figure 11 respectively.
10. International Journal of VLSI design & Communication Systems (VLSICS) Vol.5, No.5, October 2014
40
Figure 9. Delay of the circuits versus load capacitor variations
Figure 10. Power consumption of the circuits versus load capacitor variations
Figure 11. PDP of the circuits versus load capacitor variations
11. International Journal of VLSI design & Communication Systems (VLSICS) Vol.5, No.5, October 2014
Another changed parameter is frequency (Figure 12). This simulation has been performed in
Vdd=0.65V, Cload=2.1 femto Farad and temperature=25°. CN8P10G has lower PDP in selected
frequencies and also has lower increment ratio.
41
Figure 12. PDP of the circuits versus frequency variations
Figure 13 shows results with temperature variations from 0° to 70°, frequency=250MHz, load
capacitor=2.1 femto Farad and power voltage=0.65V. PDP for all designs has been calculated. In
this analysis, presented designs have lower PDP in all temperature.
Figure 13. PDP of the circuits versus temperature variations
6. CONCLUSIONS
In this article some new full adder designs have been presented which are high speed, low power
and high performance. By using exclusive properties of CNTFET, the efficiency of these designs
was improved. Circuits were simulated in various conditions and simulation results approved the
efficiency of proposed designs rather than other CMOS and CNFET-based designs that
investigated before.
12. International Journal of VLSI design & Communication Systems (VLSICS) Vol.5, No.5, October 2014
REFERENCES
[1] S. Lin, et al., "A novel CNTFET-based ternary logic gate design," in Circuits and Systems, 2009.
42
MWSCAS'09. 52nd IEEE International Midwest Symposium on, 2009, pp. 435-438.
[2] W. Porod, et al., "Quantum-dot cellular automata: computing with coupled quantum dots,"
International Journal of Electronics, vol. 86, pp. 549-590, 1999.
[3] K. Navi, et al., "High speed capacitor-inverter based carbon nanotube full adder," Nanoscale research
letters, vol. 5, pp. 859-862, 2010.
[4] M. H. Sulieman and V. Beiu, "On single-electron technology full adders," Nanotechnology, IEEE
Transactions on, vol. 4, pp. 669-680, 2005.
[5] A. Abu El-Seoud, et al., "On modelling and characterization of single electron transistor,"
International journal of electronics, vol. 94, pp. 573-585, 2007.
[6] A. Raychowdhury and K. Roy, "Carbon nanotube electronics: design of high-performance and low-power
digital circuits," Circuits and Systems I: Regular Papers, IEEE Transactions on, vol. 54, pp.
2391-2401, 2007.
[7] M. H. Moaiyeri, et al., "Design of energy-efficient and robust ternary circuits for nanotechnology,"
Circuits, Devices & Systems, IET, vol. 5, pp. 285-296, 2011.
[8] J. Deng, "Device modeling and circuit performance evaluation for nanoscale devices: silicon
technology beyond 45 nm node and carbon nanotube field effect transistors," Doctoral Dissertation,
Stanford University, 2007.
[9] G. Cho, et al., "Performance evaluation of CNFET-based logic gates," in Instrumentation and
Measurement Technology Conference, 2009. I2MTC'09. IEEE, 2009, pp. 909-912.
[10] P. Keshavarzian and K. Navi, "Efficient carbon nanotube galois field circuit design," IEICE
Electronics Express, vol. 6, pp. 546-552, 2009.
[11] A. Raychowdhury and K. Roy, "Carbon-nanotube-based voltage-mode multiple-valued logic design,"
Nanotechnology, IEEE Transactions on, vol. 4, pp. 168-179, 2005.
[12] K. Navi, et al., "A low-voltage and energy-efficient full adder cell based on carbon nanotube
technology," Nano-Micro Letters, vol. 2, pp. 114-120, 2010.
[13] K. Navi, et al., "Two novel ultra high speed carbon nanotube Full-Adder cells," IEICE Electronics
Express, vol. 6, pp. 1395-1401, 2009.
[14] S. Lin, et al., "CNTFET-based design of ternary logic gates and arithmetic circuits," Nanotechnology,
IEEE Transactions on, vol. 10, pp. 217-225, 2011.
[15] K. Navi, et al., "Five-input majority gate, a new device for quantum-dot cellular automata," Journal of
Computational and Theoretical Nanoscience, vol. 7, pp. 1546-1553, 2010.
[16] K. Navi, et al., "Two new low-power full adders based on majority-not gates," Microelectronics
Journal, vol. 40, pp. 126-130, 2009.
[17] J.-F. Lin, et al., "A novel high-speed and energy efficient 10-transistor full adder design," Circuits and
Systems I: Regular Papers, IEEE Transactions on, vol. 54, pp. 1050-1059, 2007.
[18] P. L. McEuen, et al., "Single-walled carbon nanotube electronics," Nanotechnology, IEEE
Transactions on, vol. 1, pp. 78-85, 2002.
[19] R. Saito, et al., Physical properties of carbon nanotubes vol. 35: World Scientific, 1998.
[20] Y. Jiang, et al., "A novel multiplexer-based low-power full adder," Circuits and Systems II: Express
Briefs, IEEE Transactions on, vol. 51, pp. 345-348, 2004.
[21] M. H. Moaiyeri, et al., "Efficient CNTFET-based ternary full Adder cells for nanoelectronics," Nano-
Micro Letters, vol. 3, pp. 43-50, 2011.
[22] Y. B. Kim, et al., "A novel design methodology to optimize the speed and power of the CNTFET
circuits," in Circuits and Systems, 2009. MWSCAS'09. 52nd IEEE International Midwest Symposium
on, 2009, pp. 1130-1133.
[23] A. Javey, et al., "High performance n-type carbon nanotube field-effect transistors with chemically
doped contacts," Nano letters, vol. 5, pp. 345-348, 2005.
[24] A. Javey, et al., "Self-aligned ballistic molecular transistors and electrically parallel nanotube arrays,"
Nano letters, vol. 4, pp. 1319-1322, 2004.
13. International Journal of VLSI design & Communication Systems (VLSICS) Vol.5, No.5, October 2014
[25] C.-H. Chang, et al., "A review of 0.18-/spl mu/m full adder performances for tree structured
arithmetic circuits," Very Large Scale Integration (VLSI) Systems, IEEE Transactions on, vol. 13, pp.
686-695, 2005.
[26] A. M. Shams, et al., "Performance analysis of low-power 1-bit CMOS full adder cells," Very Large
43
Scale Integration (VLSI) Systems, IEEE Transactions on, vol. 10, pp. 20-29, 2002.
[27] N. H. Weste and K. Eshraghian, "Principles of CMOS VLSI design: a systems perspective," NASA
STI/Recon Technical Report A, vol. 85, p. 47028, 1985.
[28] O. Kavehei, et al., "Design of robust and high-performance 1-bit CMOS Full Adder for nanometer
design," in Symposium on VLSI, 2008. ISVLSI'08. IEEE Computer Society Annual, 2008, pp. 10-15.
[29] A. Khatir, et al., "High speed multiple valued logic full adder using carbon nano tube field effect
transistor," arXiv preprint arXiv:1104.0298, 2011.
[30] M. R. Reshadinezhad, et al., "An Energy-Efficient Full Adder Cell Using CNFET Technology,"
IEICE Transactions on Electronics, vol. 95, pp. 744-751, 2012.
[31] H. Shahidipour, et al., "Effect of variability in SWCNT-based logic gates," in Integrated Circuits,
ISIC'09. Proceedings of the 2009 12th International Symposium on, 2009, pp. 252-255.
[32] J. Deng and H.-S. Wong, "A compact SPICE model for carbon-nanotube field-effect transistors
including nonidealities and its application—Part I: Model of the intrinsic channel region," Electron
Devices, IEEE Transactions on, vol. 54, pp. 3186-3194, 2007.
[33] J. Deng and H.-S. Wong, "A compact SPICE model for carbon-nanotube field-effect transistors
including nonidealities and its application—Part II: Full device model and circuit performance
benchmarking," Electron Devices, IEEE Transactions on, vol. 54, pp. 3195-3205, 2007.
[34] (2013). Stanford CNFET Model | Stanford Nanoelectronics Lab. Available:
https://nano.stanford.edu/stanford-cnfet-model
AUTHORS
Mehdi Masoudi received his B.Sc. degree in hardware engineering from Shahid Beheshti
University, Tehran, Iran, in 2007 and M.Sc. degree in computer architecture from IAU
Science and Research branch, Tehran, Iran, in 2013. He is a research member at
Nanotechnology and Quantum Computing Laboratory of Shahid Beheshti University. His
research interests include High Performance VLSI Designs, Nanoelectronics and new
emerging technologies specially CNFET.
Milad Mazaheri received his M.Sc. degree in computer architecture from Science and
Research Branch, IAU, Tehran, Iran in 2013. He is currently pursuing his Ph.D. degree in
computer architecture from Science and Research Branch of IAU, Tehran, Iran. His
research interests include Photonic Networks-on-chip, VLSI Systems Design, Embedded
Systems, Multiprocessor Systems, Fault Tolerant Design and Computer Architecture.
Aliakbar Reazei received his B.Sc. degree in hardware engineering from Shahid Beheshti
University, Tehran, Iran, in 2007 and M.Sc. degree in computer architecture from IAU
Science and Research branch, Tehran, Iran, in 2013. He is a research member at
Nanotechnology and Quantum Computing Laboratory of Shahid Beheshti University. His
research interests include High Performance VLSI Designs, Sensor Networks and
Computer Architecture.
Keivan Navi received his M.Sc. degree in electronics engineering from Sharif University
of Technology, Tehran, Iran in 1990. He also received his Ph.D. degree in computer
architecture from Paris XI University, Paris, France in 1995. He is currently Professor in
Faculty of Electrical and Computer Engineering of Shahid Beheshti University. His
research interests include Nanoelectronics with emphasis on CNFET, QCA and SET,
Interconnection Network Design, Quantum Computing and Cryptography. He has been a
visiting professor at the University of California, Irvine.