The downscaling of conventional MOSFETs has come to its fundamental limits. TFETs are very attractive
devices for low power applications because of their low off-current and potential for smaller sub threshold
slope. In this paper, the impact of various parameter variations on the performance of a DG-PNIN Tunnel
field effect transistor is investigated. In this work, variations in gate oxide material, source doping, channel
doping, drain doping, pocket doping and body thickness are studied and all these parameters are optimized
as performance boosters to give better current characteristics parameters. After optimization with all these
performance boosters, the device has shown improved performance with increased on-current and reduced
threshold voltage and the Ion/Ioff ratio is > 106.
SUB TEN MICRON CHANNEL DEVICES ACHIEVED BY VERTICAL ORGANIC THIN FILM TRANSI...VLSICS Design
The channel lengths of the top contact organic thin film transistors are usually defined during their fabrication by optical lithography or by shadow masking during the metal deposition process. Realizing short channel (sub-ten micron channel length) transistors by lithography will require costly lithography equipment. On the other hand, it is extremely challenging to achieve short channel transistors using the low cost shadow mask process. One low cost method of achieving short channel devices is to build vertical transistors with the transistor, where the channel gets defined in the vertical part of the device. This paper shows that vertical channel top contact organic thin film transistor has been successfullyrealized on the vertical edge of trench. This helped in creating the device with channel lengths less than ten microns, much smaller than what could be typically achieved with the use of shadow masks.
A Study On Double Gate Field Effect Transistor For Area And Cost Efficiencypaperpublications3
Abstract: Proposal for a field effect transistor had been presented, with numerical device simulations to verify the title in every manner possible. The two transitional field effect transistors like pMOS and nMOS functions are simultaneously performed, working as one or as the other according to the voltage applied to the gate terminal. Increase in the circuit speed is observed when this technology is implemented on the device suggested with respect to the standard CMOS technology, presented a drastic reduction of number devices and associated parasitic capacitances. In addition to it IC obtained with the proposed device are fully compatible with the standard CMOS technology and the fabrication processes. Fabrication of Static Ram cells with three transistors only with minimum dimensions and a single bit line by saving silicon area and increasing the memory performance with respect to standard CMOS technologies. It is also presented that the fully compatible CMOS process can be used to successfully manufacture the new FET structure.
Design of High Speed Phase Frequency Detector in 0.18 μm CMOS Process for PLL...Editor IJCATR
The Phase Frequency Detectors (PFD’s) are
proposed in this research paper by using the
two different structures of D Flip-Flop that is
the traditional D Flip-Flop and modified D
Flip-Flop with a NAND gate which can
overcome the speed and area limitations of the
conventional PFD. Both of the PFD’s use 20
transistors. The traditional PFD consumes
133.92 μW power when operating at 40 MHz
frequency with 1.8 Volts supply voltage
whereas the modified PFD consumes 100.51
μW power operating at 40 MHz frequency with
1.8 Volts supply voltage. The designs are
implemented by using 0.18 meter CMOSprocess in Tanner 13.ov. These can be used in
PLL for high speed applications
Performance Analysis of Interconnect Drivers for Ultralow Power ApplicationsIDES Editor
ultralow power consumption requirement of low
throughput applications needs to operate circuits in
subthreshold region where subthreshold leakage current is used
as active current for necessary computations. This paper
investigates the impact of interconnect drivers on digital circuit
performance in subthreshold region. In particular, we have
investigates the performance of Si-MOSFET and CNFETs at
32nm deep submicron technology node. Performance Analysis
is carried out for different interconnect drivers driving global
interconnect. We have proposed an optimized CNFET driver
which gives the significant improvement in delay and PDP over
conventional CNFET in subthreshold for global and semi-global
interconnect length. HSPICE device model files generated from
“Nano CMOS” tool are use for Si-MOSFET to analyze the
impact of Process and Temperature (P, T) variations on
robustness of circuit for fair comparison with CNFET.
Variability of design metric parameters is evaluated by applying
Gaussian distribution using Monte Carlo simulation run.
Design of a CMOS-based microwave active channelized bandpass filterTELKOMNIKA JOURNAL
A two-branch microwave active bandpass filter is designed through the channelized filtering technique as well as the transversal concept. Both the main and the auxiliary branches, connected without power dividers/combiners, rely on C-coupled active third order Chebyshev bandpass filters. A lumped element signal delay circuit is also introduced in the main channel. Active inductors based on the gyrator-C topology, are involved in the Chebyshev filters’ structure. CMOS-based Operational Transconductor Amplifier (OTA) circuits are the building blocks of these inductors. The proposed active transversal channelized filter produces an elliptic narrow band response, centered at 1.13 GHz. Simulation results, obtained by means of the PSPICE code according to the 0.18 μm TSMC MOS technology, indicate excellent performances illustrating good impedance matching, low insertion losses and high selectivity. Finally, the noise analysis shows that the filter has a low noise figure in the bandwidth.
SUB TEN MICRON CHANNEL DEVICES ACHIEVED BY VERTICAL ORGANIC THIN FILM TRANSI...VLSICS Design
The channel lengths of the top contact organic thin film transistors are usually defined during their fabrication by optical lithography or by shadow masking during the metal deposition process. Realizing short channel (sub-ten micron channel length) transistors by lithography will require costly lithography equipment. On the other hand, it is extremely challenging to achieve short channel transistors using the low cost shadow mask process. One low cost method of achieving short channel devices is to build vertical transistors with the transistor, where the channel gets defined in the vertical part of the device. This paper shows that vertical channel top contact organic thin film transistor has been successfullyrealized on the vertical edge of trench. This helped in creating the device with channel lengths less than ten microns, much smaller than what could be typically achieved with the use of shadow masks.
A Study On Double Gate Field Effect Transistor For Area And Cost Efficiencypaperpublications3
Abstract: Proposal for a field effect transistor had been presented, with numerical device simulations to verify the title in every manner possible. The two transitional field effect transistors like pMOS and nMOS functions are simultaneously performed, working as one or as the other according to the voltage applied to the gate terminal. Increase in the circuit speed is observed when this technology is implemented on the device suggested with respect to the standard CMOS technology, presented a drastic reduction of number devices and associated parasitic capacitances. In addition to it IC obtained with the proposed device are fully compatible with the standard CMOS technology and the fabrication processes. Fabrication of Static Ram cells with three transistors only with minimum dimensions and a single bit line by saving silicon area and increasing the memory performance with respect to standard CMOS technologies. It is also presented that the fully compatible CMOS process can be used to successfully manufacture the new FET structure.
Design of High Speed Phase Frequency Detector in 0.18 μm CMOS Process for PLL...Editor IJCATR
The Phase Frequency Detectors (PFD’s) are
proposed in this research paper by using the
two different structures of D Flip-Flop that is
the traditional D Flip-Flop and modified D
Flip-Flop with a NAND gate which can
overcome the speed and area limitations of the
conventional PFD. Both of the PFD’s use 20
transistors. The traditional PFD consumes
133.92 μW power when operating at 40 MHz
frequency with 1.8 Volts supply voltage
whereas the modified PFD consumes 100.51
μW power operating at 40 MHz frequency with
1.8 Volts supply voltage. The designs are
implemented by using 0.18 meter CMOSprocess in Tanner 13.ov. These can be used in
PLL for high speed applications
Performance Analysis of Interconnect Drivers for Ultralow Power ApplicationsIDES Editor
ultralow power consumption requirement of low
throughput applications needs to operate circuits in
subthreshold region where subthreshold leakage current is used
as active current for necessary computations. This paper
investigates the impact of interconnect drivers on digital circuit
performance in subthreshold region. In particular, we have
investigates the performance of Si-MOSFET and CNFETs at
32nm deep submicron technology node. Performance Analysis
is carried out for different interconnect drivers driving global
interconnect. We have proposed an optimized CNFET driver
which gives the significant improvement in delay and PDP over
conventional CNFET in subthreshold for global and semi-global
interconnect length. HSPICE device model files generated from
“Nano CMOS” tool are use for Si-MOSFET to analyze the
impact of Process and Temperature (P, T) variations on
robustness of circuit for fair comparison with CNFET.
Variability of design metric parameters is evaluated by applying
Gaussian distribution using Monte Carlo simulation run.
Design of a CMOS-based microwave active channelized bandpass filterTELKOMNIKA JOURNAL
A two-branch microwave active bandpass filter is designed through the channelized filtering technique as well as the transversal concept. Both the main and the auxiliary branches, connected without power dividers/combiners, rely on C-coupled active third order Chebyshev bandpass filters. A lumped element signal delay circuit is also introduced in the main channel. Active inductors based on the gyrator-C topology, are involved in the Chebyshev filters’ structure. CMOS-based Operational Transconductor Amplifier (OTA) circuits are the building blocks of these inductors. The proposed active transversal channelized filter produces an elliptic narrow band response, centered at 1.13 GHz. Simulation results, obtained by means of the PSPICE code according to the 0.18 μm TSMC MOS technology, indicate excellent performances illustrating good impedance matching, low insertion losses and high selectivity. Finally, the noise analysis shows that the filter has a low noise figure in the bandwidth.
DC performance analysis of a 20nm gate length n-type Silicon GAA junctionless...IJECEIAES
With integrated circuit scales in the 22-nm regime, conventional planar MOSFETs have approached the limit of their potential performance. To overcome short channel effects 'SCEs' that appears for deeply scaled MOSFETs beyond 10nm technology node many new device structures and channel materials have been proposed. Among these devices such as Gate-all-around FET. Recentely, junctionless GAA MOSFETs JL-GAA MOSFETs have attracted much attention since the junctionless MOSFET has been presented. In this paper, DC characteristics of an n-type JL-GAA MOSFET are presented using a 3-D quantum transport model. This new generation device is conceived with the same doping concentration level in its channel source/drain allowing to reduce fabrication complexity. The performance of our 3D JL-GAA structure with a 20nm gate length and a rectangular cross section have been obtained using SILVACO TCAD tools allowing also to study short channel effects. Our device reveals a favorable on/off current ratio and better SCE characteristics compared to an inversionmode GAA transistor. Our device reveals a threshold voltage of 0.55 V, a sub-threshold slope of 63mV / decade which approaches the ideal value, an Ion/Ioff ratio of 10e + 10 value and a drain induced barrier lowring (DIBL) value of 98mV/V.
Performance Comparison of CMOS and Finfet Based Circuits At 45nm Technology U...IJERA Editor
According to the Moore’s Law, the number of transistors in a unit chip area double every two years. But the existing technology of integrated circuit formation is posing limitations to this law. CMOS technology shows certain limitations as the device is reduced more and more in the nanometer regime out of which power dissipation is an important issue. FinFET is evolving to be a promising technology in this regard. This paper aims to analyze and compare the characteristics of CMOS and FinFET circuits at 45nm technology. Inverter circuit is implemented in order to study the basic characteristics such as voltage transfer characteristics, leakage current and power dissipation. Further the efficiency of FinFET to reduce power as compared to CMOS is proved using SRAM circuit. The results show that the average power is reduced by 92.93% in read operation and by 97.8% in write operation.
Power Efficiency Improvement in CE-OFDM System With 0 dB IBO for Transmission...CSCJournals
Orthogonal frequency division multiplexing (OFDM) OFDM has been adopted for high speed data transmission of multimedia traffic such as HomePlug A/V and Mobile WiMax. However, OFDM also has a drawback of a high PAPR (peak-to-average-power-ratio). Due to this high PAPR amplifier usually does not act in dynamic range. One potential solution for reducing the peak-to-average power ratio (PAPR) in an OFDM system is to utilize a constant envelope OFDM (CE-OFDM) system. Furthermore, by utilizing continuous phase modulation (CPM) in a CE-OFDM system, the PAPR can be effectively reduced to 0 dB, allowing for the signal to be amplified with a power efficient non-linear power amplifier with Input Back-Off (IBO) of 0 dB. This paper describes a CE-OFDM based modem for Power Line Communications (PLC) over the low voltage distribution network. Relying on a preliminary characterization of a PLC network, a complete description of the modem is given. Also CE-OFDM is compared with conventional OFDM under HomePlug 1.0 in the presence of power amplifier nonlinearities, considering different values of IBO.
CNFET BASED BASIC GATES AND A NOVEL FULLADDER CELLVLSICS Design
In this paper two novel high performance designs for AND and OR basic gates and a novel Full-Adder Cell are presented. These designs are based on carbon nanotube technology. In order to compare the proposed designs with previous ones both MOSFET based and CNFET based circuits are selected. By the way the proposed designs have better performance in comparison with previous designs in terms of speed, power consumption and power-delay product (PDP).
Theoretical Analysis of a two-stage Sagnac loop filter Using Jones Matrices IJECEIAES
In this work, a theoretical analysis of a Sagnac loop filter (SLF) with twostage polarization maintaining fibers (PMFs) and polarization controllers (PCs) is presented. The transmission function of this two-stage SLF is calculated in detail by using Jones matrix. The calculation is performed in order to investigate the filtering characteristics. The theoretical results show that the wavelength interval is depending on the dynamic settings of the length of the PMFs and the polarization angle of the PCs. By changing the polarization angle of the PCs, a multiple of single, dual or triple wavelength in each channel can be achieved. Based on this study, a flat multiwavelength spectrum can be obtained by adjusting the PMFs and the PCs in the twostage SLF. This finding significantly contributes to the generation of multiwavelength fiber laser (MWFL) that can be used for many optical applications.
Energy Efficient and Process Tolerant Full Adder in Technologies beyond CMOSIDES Editor
This paper presents 1-bit full adder cell in emerging
technologies like FinFET and CNFET that operates in the
moderate inversion region for energy efficiency, robustness
and higher performance. The performance of the adder is
improved by the optimum selection of important process
parameters like oxide and fin thickness in FinFET and number
of carbon nanotubes, chirality vector and pitch in CNFET.
The optimized CNFET-based full adder (OP-CNFET) has
higher speed, lower PDP (power-delay product) and lower
power dissipation as compared to the MOSFET and FinFET
full adder cells. The OP-CNFET design also offers tight spread
in power, delay and PDP variability against process, voltage
and temperature variations. All the evaluations have been
carried out using HSPICE simulations based on 32 nm BPTM
(Berkeley Predictive Technology Model).
Compact Stepped Impedance Resonator Bandpass Filter with Tunable Transmission...TELKOMNIKA JOURNAL
This paper proposes a compact microstrip bandpass filter (BPF) with tunable transmission zero,
narrow bandwidth and low insertion loss. Transmission zeros are the key to improve the band rejection
and filter frequency selectivity. A λ/4 stepped impedance resonator (SIR) with two additional via holes has
been adopted to obtain a compact size and a pair of transmission zero (TZ). The BPF is designed to
operate at 3.5 GHz with fractional bandwidth (FBW) of 7.2%.Furthermore, three techniques have been
developed to create a pair of controllable transmission zeros on both side of each passband. The TZ can
be controlled by adjusting either magnetic or electric coupling. The measured return losses and insertion
lossis larger than 18 dB and 2.2 dB respectively. The overall size of the proposed design filter is 5.3mm x
5.5mm without considering the feeding lines.
Design and Analysis of Power and Variability Aware Digital Summing CircuitIDES Editor
Due to aggressive scaling and process imperfection
in sub-45 nm technology node Vt (threshold voltage) shift is
more pronounced causing large variations in circuit response.
Therefore, this paper presents the analyses of various popular
1-bit digital summing circuits in light of PVT (process, voltage
and temperature) variations to verify their functionality and
robustness. The investigation is carried with ±3ó process
parameters and ±10% VDD (supply voltage) variation by applying
Gaussian distribution and Monte Carlo analysis at 22 nm
technology node on HSPICE environment. Design guidelines
are derived to select the most suitable topology for the design
features required. Transmission Gate (TG)-based digital
summing circuit is found to be the most robust against PVT
variations. Hence, a TG-based digital summing circuit is
implemented using carbon nanotube field effect transistor
(CNFET). This implementation offers tighter spread in
propagation delay (3×), power dissipation (1.14×) and EDP
(energy delay product) (1.1×) at nominal voltage of VDD = 0.95V
compared to MOSFET-based (TG – topology) digital summing
circuit implying its robustness against PVT variations.
Design of Simulink Model for Constant Envelop OFDM & Analysis of Bit Error RateIJSRD
This paper describes a transformation technique aimed at solving the peak-to-average power ratio (PAPR) problem associated with OFDM (Orthogonal Frequency Division Multiplexing). The Constant Envelop-OFDM solves the problem of high peak-to-average power ratio (PAPR) in OFDM, reducing PAPR to 0 dB. The constant envelope signal can be efficiently amplified with nonlinear power amplifiers thus achieving greater power efficiency. It is shown that CE-OFDM’s performance is better than conventional OFDM when taking into account the effects of the power amplifier. The performance of CE-OFDM is analyzed in additive white Gaussian noise (AWGN) channel. CE-OFDM is shown to achieve good performance with the use of cyclic prefix transmission. By way of computer simulation, CE-OFDM is shown to compare favorably to conventional OFDM. OFDM and CE-OFDM is analyzed on grounds of BER with additive white Gaussian noise (AWGN). The BER is calculated and the performance of OFDM and CE OFDM is compared.
A Low Power High Bandwidth Four Quadrant Analog Multiplier in 32 NM CNFET Tec...VLSICS Design
Carbon Nanotube Field Effect Transistor (CNFET) is a promising new technology that overcomes several limitations of traditional silicon integrated circuit technology. In recent years, the potential of CNFET for analog circuit applications has been explored. This paper proposes a novel four quadrant analog multiplier design using CNFETs. The simulation based on 32nm CNFET technology shows that the proposed multiplier has very low harmonic distortion (<0.45%), large input range (±400mV), large bandwidth (~50GHz) and low power consumption (~247µW), while operating at a supply voltage of ±0.9V.
Performance Comparison of RF CMOS Low Noise Amplifiers in 0.18-µm technology ...VLSICS Design
This paper presents the design theory of conventional single-ended LNA and differential LNA based on CMOS technology. The design concepts give an useful indication to the design trade-offs associated with NF, gain and impedance matching. Four LNA’s have been designed using technological design rules of TSMC 0.18-µm CMOS technology and this work mainly proposed for IEEE 802.11a applications. With 1.8V supply voltage, the proposed LNA’s achieve a gain higher than 19dB, a noise figure less than 4dB and impedance matching less than -10dB at 5GHz frequency. The goal of this paper is to highlight the efficient LNA architecture for achieving simultaneous gain, noise and input matching at low supply voltage. The performance of all LNA’s are analysed and compared using Agilent’s Advanced Design System Electronic Design Automation tools.
Efficient Design of Higher Order Variable Digital Filter for Multi Modulated ...IJTET Journal
The electrocardiogram (ECG) analysis is commonly used technique in clinical examination proposes a method of designing reconfigurable warped digital filter with various low-pass, high-pass, band-pass and band-stop responses. The warped filter is obtain by replacing each element interruption of a digital filter with an all exceed filter. It is widely used for various video and audio processing applications. Warped filters require first-order all pass conversion to obtain low-pass and high-pass responses, and by using second-order all pass conversion to obtain variable band-pass and band-stop responses. To overcome this drawback, proposed method combines warped filters with the coefficient decimation technique. In VLSI circuits in order to reduce hardware cost Command Signals Decoder (CSD) based shift-and-add approach is used for multiplication. It offers extensive savings in opening count and power utilization more than other approaches.
Comparison Static ICIC and Adaptive ICIC on TD-LTERay KHASTUR
The subscriber on the cell edge will have bad experience due to impact of this co-channel interference. There is function of SFR (Soft Frequency Reuse) in LTE-TDD that is manipulated BW into several cell edge style. On Genex U-Net we can use this feature to minimize of inter cell interference, we can chose static ICIC or adaptive ICIC based on field condition.
Comparative analysis of technology advancement from single gate to multi gate...eSAT Journals
Abstract
Among the entire contender in modern microelectronics,DG-MOSFET is a front line runner in planar technology. Itsunique
structure allows scaling the device at sub-nanometer region and mimicking the electrical characteristics of a MOSFET.Here
simulation of NMOS, SOI-NMOS, and DG-NMOS is presentedand relative comparison among short channel characteristics
ispresented.It has been seen that among all the above stated device, DG-MOSFET possess better immune to leakage current with
betterDIBL, whereas SOI MOSFET have better driving capacity.
KeyWords:SOI-MOSFET, DG-MOSFET, UTB, DIBL,SCEs
Performance Analysis of Post Compensated Long Haul High Speed Coherent Optica...Yayah Zakaria
This paper addresses the performance analysis of OFDM transmission system based on coherent detection over high speed long haul optical links with high spectral efficiency modulation formats such as Quadrature Amplitude Modulation (QAM) as a mapping method prior to the OFDM multicarrier representation. Post compensation is used to compensate for
phase noise effects. Coherent detection for signal transmitted at bit rate of 40 Gbps is successfully achieved up to distance of 3200km. Performance is analyzed in terms of Symbol Error Rate and Error Vector Magnitude by varying Optical Signal to Noise Ratio (OSNR) and varying the length of the fiber i.e transmission distance. Transmission performance is also observed through constellation diagrams at different transmission distances and
different OSNRs.
DC performance analysis of a 20nm gate length n-type Silicon GAA junctionless...IJECEIAES
With integrated circuit scales in the 22-nm regime, conventional planar MOSFETs have approached the limit of their potential performance. To overcome short channel effects 'SCEs' that appears for deeply scaled MOSFETs beyond 10nm technology node many new device structures and channel materials have been proposed. Among these devices such as Gate-all-around FET. Recentely, junctionless GAA MOSFETs JL-GAA MOSFETs have attracted much attention since the junctionless MOSFET has been presented. In this paper, DC characteristics of an n-type JL-GAA MOSFET are presented using a 3-D quantum transport model. This new generation device is conceived with the same doping concentration level in its channel source/drain allowing to reduce fabrication complexity. The performance of our 3D JL-GAA structure with a 20nm gate length and a rectangular cross section have been obtained using SILVACO TCAD tools allowing also to study short channel effects. Our device reveals a favorable on/off current ratio and better SCE characteristics compared to an inversionmode GAA transistor. Our device reveals a threshold voltage of 0.55 V, a sub-threshold slope of 63mV / decade which approaches the ideal value, an Ion/Ioff ratio of 10e + 10 value and a drain induced barrier lowring (DIBL) value of 98mV/V.
Performance Comparison of CMOS and Finfet Based Circuits At 45nm Technology U...IJERA Editor
According to the Moore’s Law, the number of transistors in a unit chip area double every two years. But the existing technology of integrated circuit formation is posing limitations to this law. CMOS technology shows certain limitations as the device is reduced more and more in the nanometer regime out of which power dissipation is an important issue. FinFET is evolving to be a promising technology in this regard. This paper aims to analyze and compare the characteristics of CMOS and FinFET circuits at 45nm technology. Inverter circuit is implemented in order to study the basic characteristics such as voltage transfer characteristics, leakage current and power dissipation. Further the efficiency of FinFET to reduce power as compared to CMOS is proved using SRAM circuit. The results show that the average power is reduced by 92.93% in read operation and by 97.8% in write operation.
Power Efficiency Improvement in CE-OFDM System With 0 dB IBO for Transmission...CSCJournals
Orthogonal frequency division multiplexing (OFDM) OFDM has been adopted for high speed data transmission of multimedia traffic such as HomePlug A/V and Mobile WiMax. However, OFDM also has a drawback of a high PAPR (peak-to-average-power-ratio). Due to this high PAPR amplifier usually does not act in dynamic range. One potential solution for reducing the peak-to-average power ratio (PAPR) in an OFDM system is to utilize a constant envelope OFDM (CE-OFDM) system. Furthermore, by utilizing continuous phase modulation (CPM) in a CE-OFDM system, the PAPR can be effectively reduced to 0 dB, allowing for the signal to be amplified with a power efficient non-linear power amplifier with Input Back-Off (IBO) of 0 dB. This paper describes a CE-OFDM based modem for Power Line Communications (PLC) over the low voltage distribution network. Relying on a preliminary characterization of a PLC network, a complete description of the modem is given. Also CE-OFDM is compared with conventional OFDM under HomePlug 1.0 in the presence of power amplifier nonlinearities, considering different values of IBO.
CNFET BASED BASIC GATES AND A NOVEL FULLADDER CELLVLSICS Design
In this paper two novel high performance designs for AND and OR basic gates and a novel Full-Adder Cell are presented. These designs are based on carbon nanotube technology. In order to compare the proposed designs with previous ones both MOSFET based and CNFET based circuits are selected. By the way the proposed designs have better performance in comparison with previous designs in terms of speed, power consumption and power-delay product (PDP).
Theoretical Analysis of a two-stage Sagnac loop filter Using Jones Matrices IJECEIAES
In this work, a theoretical analysis of a Sagnac loop filter (SLF) with twostage polarization maintaining fibers (PMFs) and polarization controllers (PCs) is presented. The transmission function of this two-stage SLF is calculated in detail by using Jones matrix. The calculation is performed in order to investigate the filtering characteristics. The theoretical results show that the wavelength interval is depending on the dynamic settings of the length of the PMFs and the polarization angle of the PCs. By changing the polarization angle of the PCs, a multiple of single, dual or triple wavelength in each channel can be achieved. Based on this study, a flat multiwavelength spectrum can be obtained by adjusting the PMFs and the PCs in the twostage SLF. This finding significantly contributes to the generation of multiwavelength fiber laser (MWFL) that can be used for many optical applications.
Energy Efficient and Process Tolerant Full Adder in Technologies beyond CMOSIDES Editor
This paper presents 1-bit full adder cell in emerging
technologies like FinFET and CNFET that operates in the
moderate inversion region for energy efficiency, robustness
and higher performance. The performance of the adder is
improved by the optimum selection of important process
parameters like oxide and fin thickness in FinFET and number
of carbon nanotubes, chirality vector and pitch in CNFET.
The optimized CNFET-based full adder (OP-CNFET) has
higher speed, lower PDP (power-delay product) and lower
power dissipation as compared to the MOSFET and FinFET
full adder cells. The OP-CNFET design also offers tight spread
in power, delay and PDP variability against process, voltage
and temperature variations. All the evaluations have been
carried out using HSPICE simulations based on 32 nm BPTM
(Berkeley Predictive Technology Model).
Compact Stepped Impedance Resonator Bandpass Filter with Tunable Transmission...TELKOMNIKA JOURNAL
This paper proposes a compact microstrip bandpass filter (BPF) with tunable transmission zero,
narrow bandwidth and low insertion loss. Transmission zeros are the key to improve the band rejection
and filter frequency selectivity. A λ/4 stepped impedance resonator (SIR) with two additional via holes has
been adopted to obtain a compact size and a pair of transmission zero (TZ). The BPF is designed to
operate at 3.5 GHz with fractional bandwidth (FBW) of 7.2%.Furthermore, three techniques have been
developed to create a pair of controllable transmission zeros on both side of each passband. The TZ can
be controlled by adjusting either magnetic or electric coupling. The measured return losses and insertion
lossis larger than 18 dB and 2.2 dB respectively. The overall size of the proposed design filter is 5.3mm x
5.5mm without considering the feeding lines.
Design and Analysis of Power and Variability Aware Digital Summing CircuitIDES Editor
Due to aggressive scaling and process imperfection
in sub-45 nm technology node Vt (threshold voltage) shift is
more pronounced causing large variations in circuit response.
Therefore, this paper presents the analyses of various popular
1-bit digital summing circuits in light of PVT (process, voltage
and temperature) variations to verify their functionality and
robustness. The investigation is carried with ±3ó process
parameters and ±10% VDD (supply voltage) variation by applying
Gaussian distribution and Monte Carlo analysis at 22 nm
technology node on HSPICE environment. Design guidelines
are derived to select the most suitable topology for the design
features required. Transmission Gate (TG)-based digital
summing circuit is found to be the most robust against PVT
variations. Hence, a TG-based digital summing circuit is
implemented using carbon nanotube field effect transistor
(CNFET). This implementation offers tighter spread in
propagation delay (3×), power dissipation (1.14×) and EDP
(energy delay product) (1.1×) at nominal voltage of VDD = 0.95V
compared to MOSFET-based (TG – topology) digital summing
circuit implying its robustness against PVT variations.
Design of Simulink Model for Constant Envelop OFDM & Analysis of Bit Error RateIJSRD
This paper describes a transformation technique aimed at solving the peak-to-average power ratio (PAPR) problem associated with OFDM (Orthogonal Frequency Division Multiplexing). The Constant Envelop-OFDM solves the problem of high peak-to-average power ratio (PAPR) in OFDM, reducing PAPR to 0 dB. The constant envelope signal can be efficiently amplified with nonlinear power amplifiers thus achieving greater power efficiency. It is shown that CE-OFDM’s performance is better than conventional OFDM when taking into account the effects of the power amplifier. The performance of CE-OFDM is analyzed in additive white Gaussian noise (AWGN) channel. CE-OFDM is shown to achieve good performance with the use of cyclic prefix transmission. By way of computer simulation, CE-OFDM is shown to compare favorably to conventional OFDM. OFDM and CE-OFDM is analyzed on grounds of BER with additive white Gaussian noise (AWGN). The BER is calculated and the performance of OFDM and CE OFDM is compared.
A Low Power High Bandwidth Four Quadrant Analog Multiplier in 32 NM CNFET Tec...VLSICS Design
Carbon Nanotube Field Effect Transistor (CNFET) is a promising new technology that overcomes several limitations of traditional silicon integrated circuit technology. In recent years, the potential of CNFET for analog circuit applications has been explored. This paper proposes a novel four quadrant analog multiplier design using CNFETs. The simulation based on 32nm CNFET technology shows that the proposed multiplier has very low harmonic distortion (<0.45%), large input range (±400mV), large bandwidth (~50GHz) and low power consumption (~247µW), while operating at a supply voltage of ±0.9V.
Performance Comparison of RF CMOS Low Noise Amplifiers in 0.18-µm technology ...VLSICS Design
This paper presents the design theory of conventional single-ended LNA and differential LNA based on CMOS technology. The design concepts give an useful indication to the design trade-offs associated with NF, gain and impedance matching. Four LNA’s have been designed using technological design rules of TSMC 0.18-µm CMOS technology and this work mainly proposed for IEEE 802.11a applications. With 1.8V supply voltage, the proposed LNA’s achieve a gain higher than 19dB, a noise figure less than 4dB and impedance matching less than -10dB at 5GHz frequency. The goal of this paper is to highlight the efficient LNA architecture for achieving simultaneous gain, noise and input matching at low supply voltage. The performance of all LNA’s are analysed and compared using Agilent’s Advanced Design System Electronic Design Automation tools.
Efficient Design of Higher Order Variable Digital Filter for Multi Modulated ...IJTET Journal
The electrocardiogram (ECG) analysis is commonly used technique in clinical examination proposes a method of designing reconfigurable warped digital filter with various low-pass, high-pass, band-pass and band-stop responses. The warped filter is obtain by replacing each element interruption of a digital filter with an all exceed filter. It is widely used for various video and audio processing applications. Warped filters require first-order all pass conversion to obtain low-pass and high-pass responses, and by using second-order all pass conversion to obtain variable band-pass and band-stop responses. To overcome this drawback, proposed method combines warped filters with the coefficient decimation technique. In VLSI circuits in order to reduce hardware cost Command Signals Decoder (CSD) based shift-and-add approach is used for multiplication. It offers extensive savings in opening count and power utilization more than other approaches.
Comparison Static ICIC and Adaptive ICIC on TD-LTERay KHASTUR
The subscriber on the cell edge will have bad experience due to impact of this co-channel interference. There is function of SFR (Soft Frequency Reuse) in LTE-TDD that is manipulated BW into several cell edge style. On Genex U-Net we can use this feature to minimize of inter cell interference, we can chose static ICIC or adaptive ICIC based on field condition.
Comparative analysis of technology advancement from single gate to multi gate...eSAT Journals
Abstract
Among the entire contender in modern microelectronics,DG-MOSFET is a front line runner in planar technology. Itsunique
structure allows scaling the device at sub-nanometer region and mimicking the electrical characteristics of a MOSFET.Here
simulation of NMOS, SOI-NMOS, and DG-NMOS is presentedand relative comparison among short channel characteristics
ispresented.It has been seen that among all the above stated device, DG-MOSFET possess better immune to leakage current with
betterDIBL, whereas SOI MOSFET have better driving capacity.
KeyWords:SOI-MOSFET, DG-MOSFET, UTB, DIBL,SCEs
Performance Analysis of Post Compensated Long Haul High Speed Coherent Optica...Yayah Zakaria
This paper addresses the performance analysis of OFDM transmission system based on coherent detection over high speed long haul optical links with high spectral efficiency modulation formats such as Quadrature Amplitude Modulation (QAM) as a mapping method prior to the OFDM multicarrier representation. Post compensation is used to compensate for
phase noise effects. Coherent detection for signal transmitted at bit rate of 40 Gbps is successfully achieved up to distance of 3200km. Performance is analyzed in terms of Symbol Error Rate and Error Vector Magnitude by varying Optical Signal to Noise Ratio (OSNR) and varying the length of the fiber i.e transmission distance. Transmission performance is also observed through constellation diagrams at different transmission distances and
different OSNRs.
International Journal of Engineering Research and Applications (IJERA) is an open access online peer reviewed international journal that publishes research and review articles in the fields of Computer Science, Neural Networks, Electrical Engineering, Software Engineering, Information Technology, Mechanical Engineering, Chemical Engineering, Plastic Engineering, Food Technology, Textile Engineering, Nano Technology & science, Power Electronics, Electronics & Communication Engineering, Computational mathematics, Image processing, Civil Engineering, Structural Engineering, Environmental Engineering, VLSI Testing & Low Power VLSI Design etc.
Physical Scaling Limits of FinFET Structure: A Simulation StudyVLSICS Design
In this work an attempt has been made to analyze the scaling limits of Double Gate (DG) underlap and Triple Gate (TG) overlap FinFET structure using 2D and 3D computer simulations respectively. To analyze the scaling limits of FinFET structure, simulations are performed using three variables: finthickness, fin-height and gate-length. From 2D simulation of DG FinFET, it is found that the gate-length (L) and fin-thickness (Tfin) ratio plays a key role while deciding the performance of the device. Drain Induced Barrier Lowering (DIBL) and Subthreshold Swing (SS) increase abruptly when (L/Tfin) ratio goes below 1.5. So, there will be a trade-off in between SCEs and on- current of the device since on-off current ratio is found to be high at small dimensions. From 3D simulation study on TG FinFET, It is found that both fin-thickness (Tfin) and fin-height (Hfin) can control the SCEs. However, Tfin is found to be more dominant parameter than Hfin while deciding the SCEs. DIBL and SS increase as (Leff/Tfin) ratio decreases. The (Leff/Tfin) ratio can be reduced below 1.5 unlike DG FinFET for the same SCEs. However,
as this ratio approaches to 1, the SCEs can go beyond acceptable limits for TG FinFET structure. The relative ratio of Hfin and Tfin should be maximum at a given Tfin and Leff to get maximum on-current per unit width. However, increasing Hfin degrades the fin stability and degrades SCEs.
Physical Scaling Limits of FinFET Structure: A Simulation StudyVLSICS Design
In this work an attempt has been made to analyze the scaling limits of Double Gate (DG) underlap and Triple Gate (TG) overlap FinFET structure using 2D and 3D computer simulations respectively. To analyze the scaling limits of FinFET structure, simulations are performed using three variables: finthickness, fin-height and gate-length. From 2D simulation of DG FinFET, it is found that the gate-length (L) and fin-thickness (Tfin) ratio plays a key role while deciding the performance of the device. Drain Induced Barrier Lowering (DIBL) and Subthreshold Swing (SS) increase abruptly when (L/Tfin) ratio goes below 1.5. So, there will be a trade-off in between SCEs and on- current of the device since on-off current ratio is found to be high at small dimensions. From 3D simulation study on TG FinFET, It is found that both fin-thickness (Tfin) and fin-height (Hfin) can control the SCEs. However, Tfin is found to be more dominant parameter than Hfin while deciding the SCEs. DIBL and SS increase as (Leff/Tfin) ratio decreases. The (Leff/Tfin) ratio can be reduced below 1.5 unlike DG FinFET for the same SCEs. However,
as this ratio approaches to 1, the SCEs can go beyond acceptable limits for TG FinFET structure. The relative ratio of Hfin and Tfin should be maximum at a given Tfin and Leff to get maximum on-current per unit width. However, increasing Hfin degrades the fin stability and degrades SCEs.
THRESHOLD VOLTAGE CONTROL SCHEMES IN FINFETSVLSICS Design
Conventionally polysilicon is used in MOSFETs for gate material. Doping of polysilicon and thus changing the workfunction is carried out to change the threshold voltage. Additionally polysilicon is not favourable as gate material for smaller dimensional devices because of its high thermal budget process and degradation due to the depletion of the doped polysilicon, thus metal gate is preferred over polysilicon. Control of workfunction in metal gate is a challenging task. The use of metal alloys as gate materials for variable gate workfunction has been already reported in literature. In this work various threshold voltage techniques has been analyzed and a novel aligned dual metal gate technique is proposed for threshold voltage control in FinFETs.
Electrical characterization of si nanowire GAA-TFET based on dimensions downs...IJECEIAES
This research paper explains the effect of the dimensions of Gate-all-around Si nanowire tunneling field effect transistor (GAA Si-NW TFET) on ON/OFF current ratio, drain induces barrier lowering (DIBL), sub-threshold swing (SS), and threshold voltage (V T ). These parameters are critical factors of the characteristics of tunnel field effect transistors. The Silvaco TCAD has been used to study the electrical characteristics of Si-NW TFET. Output (gate voltage-drain current) characteristics with channel dimensions were simulated. Results show that 50nm long nanowires with 9nm-18nm diameter and 3nm oxide thickness tend to have the best nanowire tunnel field effect transistor (Si-NW TFET) characteristics.
Review of Fin FET Technology and Circuit Design ChallengesIJERA Editor
Considering the difficulties in planar CMOS transistor scaling to secure an acceptable gate to channel control
FinFET based multi-gate (MuGFET) devices have been proposed as a technology option for replacing the
existing technology. The desirability of FinFET that it’s operation principle is same as CMOS process. This
permits to lengthening the gate scaling beyond the planar transistor limits, sustaining a steep subthreshold slope,
better performance with bias voltage scaling and good matching due to low doping concentration in the channel.
There are, still, several challenges and limitations that FinFET technology has to face to be competitive with
other technology options: Fin shape, pitch, isolation, doping, crystallographic orientation and stressing as well as
device parasitic, performance and patterning approaches will be discussed.
International Journal of Engineering Research and Applications (IJERA) is an open access online peer reviewed international journal that publishes research and review articles in the fields of Computer Science, Neural Networks, Electrical Engineering, Software Engineering, Information Technology, Mechanical Engineering, Chemical Engineering, Plastic Engineering, Food Technology, Textile Engineering, Nano Technology & science, Power Electronics, Electronics & Communication Engineering, Computational mathematics, Image processing, Civil Engineering, Structural Engineering, Environmental Engineering, VLSI Testing & Low Power VLSI Design etc.
HIGH FIN WIDTH MOSFET USING GAA STRUCTUREVLSICS Design
This paper describes the design and optimization of gate-all-around (GAA) MOSFETs structures. The optimum value of Fin width and Fin height are investigated for superior subthreshold behavior. Also the performance of Fin shaped GAA with gate oxide HfO2 are simulated and compared with conventional gate oxide SiO2 for the same structure. As a result, it was observed that the GAA with high K dielectric gate oxide has more possibility to optimize the Fin width with improved performance. All the simulations are performed on 3-D TCAD device simulator.
Welcome to the first live UiPath Community Day Dubai! Join us for this unique occasion to meet our local and global UiPath Community and leaders. You will get a full view of the MEA region's automation landscape and the AI Powered automation technology capabilities of UiPath. Also, hosted by our local partners Marc Ellis, you will enjoy a half-day packed with industry insights and automation peers networking.
📕 Curious on our agenda? Wait no more!
10:00 Welcome note - UiPath Community in Dubai
Lovely Sinha, UiPath Community Chapter Leader, UiPath MVPx3, Hyper-automation Consultant, First Abu Dhabi Bank
10:20 A UiPath cross-region MEA overview
Ashraf El Zarka, VP and Managing Director MEA, UiPath
10:35: Customer Success Journey
Deepthi Deepak, Head of Intelligent Automation CoE, First Abu Dhabi Bank
11:15 The UiPath approach to GenAI with our three principles: improve accuracy, supercharge productivity, and automate more
Boris Krumrey, Global VP, Automation Innovation, UiPath
12:15 To discover how Marc Ellis leverages tech-driven solutions in recruitment and managed services.
Brendan Lingam, Director of Sales and Business Development, Marc Ellis
Securing your Kubernetes cluster_ a step-by-step guide to success !KatiaHIMEUR1
Today, after several years of existence, an extremely active community and an ultra-dynamic ecosystem, Kubernetes has established itself as the de facto standard in container orchestration. Thanks to a wide range of managed services, it has never been so easy to set up a ready-to-use Kubernetes cluster.
However, this ease of use means that the subject of security in Kubernetes is often left for later, or even neglected. This exposes companies to significant risks.
In this talk, I'll show you step-by-step how to secure your Kubernetes cluster for greater peace of mind and reliability.
Transcript: Selling digital books in 2024: Insights from industry leaders - T...BookNet Canada
The publishing industry has been selling digital audiobooks and ebooks for over a decade and has found its groove. What’s changed? What has stayed the same? Where do we go from here? Join a group of leading sales peers from across the industry for a conversation about the lessons learned since the popularization of digital books, best practices, digital book supply chain management, and more.
Link to video recording: https://bnctechforum.ca/sessions/selling-digital-books-in-2024-insights-from-industry-leaders/
Presented by BookNet Canada on May 28, 2024, with support from the Department of Canadian Heritage.
State of ICS and IoT Cyber Threat Landscape Report 2024 previewPrayukth K V
The IoT and OT threat landscape report has been prepared by the Threat Research Team at Sectrio using data from Sectrio, cyber threat intelligence farming facilities spread across over 85 cities around the world. In addition, Sectrio also runs AI-based advanced threat and payload engagement facilities that serve as sinks to attract and engage sophisticated threat actors, and newer malware including new variants and latent threats that are at an earlier stage of development.
The latest edition of the OT/ICS and IoT security Threat Landscape Report 2024 also covers:
State of global ICS asset and network exposure
Sectoral targets and attacks as well as the cost of ransom
Global APT activity, AI usage, actor and tactic profiles, and implications
Rise in volumes of AI-powered cyberattacks
Major cyber events in 2024
Malware and malicious payload trends
Cyberattack types and targets
Vulnerability exploit attempts on CVEs
Attacks on counties – USA
Expansion of bot farms – how, where, and why
In-depth analysis of the cyber threat landscape across North America, South America, Europe, APAC, and the Middle East
Why are attacks on smart factories rising?
Cyber risk predictions
Axis of attacks – Europe
Systemic attacks in the Middle East
Download the full report from here:
https://sectrio.com/resources/ot-threat-landscape-reports/sectrio-releases-ot-ics-and-iot-security-threat-landscape-report-2024/
GraphRAG is All You need? LLM & Knowledge GraphGuy Korland
Guy Korland, CEO and Co-founder of FalkorDB, will review two articles on the integration of language models with knowledge graphs.
1. Unifying Large Language Models and Knowledge Graphs: A Roadmap.
https://arxiv.org/abs/2306.08302
2. Microsoft Research's GraphRAG paper and a review paper on various uses of knowledge graphs:
https://www.microsoft.com/en-us/research/blog/graphrag-unlocking-llm-discovery-on-narrative-private-data/
The Metaverse and AI: how can decision-makers harness the Metaverse for their...Jen Stirrup
The Metaverse is popularized in science fiction, and now it is becoming closer to being a part of our daily lives through the use of social media and shopping companies. How can businesses survive in a world where Artificial Intelligence is becoming the present as well as the future of technology, and how does the Metaverse fit into business strategy when futurist ideas are developing into reality at accelerated rates? How do we do this when our data isn't up to scratch? How can we move towards success with our data so we are set up for the Metaverse when it arrives?
How can you help your company evolve, adapt, and succeed using Artificial Intelligence and the Metaverse to stay ahead of the competition? What are the potential issues, complications, and benefits that these technologies could bring to us and our organizations? In this session, Jen Stirrup will explain how to start thinking about these technologies as an organisation.
A tale of scale & speed: How the US Navy is enabling software delivery from l...sonjaschweigert1
Rapid and secure feature delivery is a goal across every application team and every branch of the DoD. The Navy’s DevSecOps platform, Party Barge, has achieved:
- Reduction in onboarding time from 5 weeks to 1 day
- Improved developer experience and productivity through actionable findings and reduction of false positives
- Maintenance of superior security standards and inherent policy enforcement with Authorization to Operate (ATO)
Development teams can ship efficiently and ensure applications are cyber ready for Navy Authorizing Officials (AOs). In this webinar, Sigma Defense and Anchore will give attendees a look behind the scenes and demo secure pipeline automation and security artifacts that speed up application ATO and time to production.
We will cover:
- How to remove silos in DevSecOps
- How to build efficient development pipeline roles and component templates
- How to deliver security artifacts that matter for ATO’s (SBOMs, vulnerability reports, and policy evidence)
- How to streamline operations with automated policy checks on container images
Removing Uninteresting Bytes in Software FuzzingAftab Hussain
Imagine a world where software fuzzing, the process of mutating bytes in test seeds to uncover hidden and erroneous program behaviors, becomes faster and more effective. A lot depends on the initial seeds, which can significantly dictate the trajectory of a fuzzing campaign, particularly in terms of how long it takes to uncover interesting behaviour in your code. We introduce DIAR, a technique designed to speedup fuzzing campaigns by pinpointing and eliminating those uninteresting bytes in the seeds. Picture this: instead of wasting valuable resources on meaningless mutations in large, bloated seeds, DIAR removes the unnecessary bytes, streamlining the entire process.
In this work, we equipped AFL, a popular fuzzer, with DIAR and examined two critical Linux libraries -- Libxml's xmllint, a tool for parsing xml documents, and Binutil's readelf, an essential debugging and security analysis command-line tool used to display detailed information about ELF (Executable and Linkable Format). Our preliminary results show that AFL+DIAR does not only discover new paths more quickly but also achieves higher coverage overall. This work thus showcases how starting with lean and optimized seeds can lead to faster, more comprehensive fuzzing campaigns -- and DIAR helps you find such seeds.
- These are slides of the talk given at IEEE International Conference on Software Testing Verification and Validation Workshop, ICSTW 2022.
The Art of the Pitch: WordPress Relationships and SalesLaura Byrne
Clients don’t know what they don’t know. What web solutions are right for them? How does WordPress come into the picture? How do you make sure you understand scope and timeline? What do you do if sometime changes?
All these questions and more will be explored as we talk about matching clients’ needs with what your agency offers without pulling teeth or pulling your hair out. Practical tips, and strategies for successful relationship building that leads to closing the deal.
UiPath Test Automation using UiPath Test Suite series, part 4DianaGray10
Welcome to UiPath Test Automation using UiPath Test Suite series part 4. In this session, we will cover Test Manager overview along with SAP heatmap.
The UiPath Test Manager overview with SAP heatmap webinar offers a concise yet comprehensive exploration of the role of a Test Manager within SAP environments, coupled with the utilization of heatmaps for effective testing strategies.
Participants will gain insights into the responsibilities, challenges, and best practices associated with test management in SAP projects. Additionally, the webinar delves into the significance of heatmaps as a visual aid for identifying testing priorities, areas of risk, and resource allocation within SAP landscapes. Through this session, attendees can expect to enhance their understanding of test management principles while learning practical approaches to optimize testing processes in SAP environments using heatmap visualization techniques
What will you get from this session?
1. Insights into SAP testing best practices
2. Heatmap utilization for testing
3. Optimization of testing processes
4. Demo
Topics covered:
Execution from the test manager
Orchestrator execution result
Defect reporting
SAP heatmap example with demo
Speaker:
Deepak Rai, Automation Practice Lead, Boundaryless Group and UiPath MVP
Climate Impact of Software Testing at Nordic Testing DaysKari Kakkonen
My slides at Nordic Testing Days 6.6.2024
Climate impact / sustainability of software testing discussed on the talk. ICT and testing must carry their part of global responsibility to help with the climat warming. We can minimize the carbon footprint but we can also have a carbon handprint, a positive impact on the climate. Quality characteristics can be added with sustainability, and then measured continuously. Test environments can be used less, and in smaller scale and on demand. Test techniques can be used in optimizing or minimizing number of tests. Test automation can be used to speed up testing.
Epistemic Interaction - tuning interfaces to provide information for AI supportAlan Dix
Paper presented at SYNERGY workshop at AVI 2024, Genoa, Italy. 3rd June 2024
https://alandix.com/academic/papers/synergy2024-epistemic/
As machine learning integrates deeper into human-computer interactions, the concept of epistemic interaction emerges, aiming to refine these interactions to enhance system adaptability. This approach encourages minor, intentional adjustments in user behaviour to enrich the data available for system learning. This paper introduces epistemic interaction within the context of human-system communication, illustrating how deliberate interaction design can improve system understanding and adaptation. Through concrete examples, we demonstrate the potential of epistemic interaction to significantly advance human-computer interaction by leveraging intuitive human communication strategies to inform system design and functionality, offering a novel pathway for enriching user-system engagements.
Dev Dives: Train smarter, not harder – active learning and UiPath LLMs for do...UiPathCommunity
💥 Speed, accuracy, and scaling – discover the superpowers of GenAI in action with UiPath Document Understanding and Communications Mining™:
See how to accelerate model training and optimize model performance with active learning
Learn about the latest enhancements to out-of-the-box document processing – with little to no training required
Get an exclusive demo of the new family of UiPath LLMs – GenAI models specialized for processing different types of documents and messages
This is a hands-on session specifically designed for automation developers and AI enthusiasts seeking to enhance their knowledge in leveraging the latest intelligent document processing capabilities offered by UiPath.
Speakers:
👨🏫 Andras Palfi, Senior Product Manager, UiPath
👩🏫 Lenka Dulovicova, Product Program Manager, UiPath
Dev Dives: Train smarter, not harder – active learning and UiPath LLMs for do...
Impact of parameter variations and optimization on dg pnin tunnel fet
1. International Journal of VLSI design & Communication Systems (VLSICS) Vol.5, No.3, June 2014
DOI : 10.5121/vlsic.2014.5305 47
IMPACT OF PARAMETER VARIATIONS AND
OPTIMIZATION ON DG-PNIN TUNNEL FET
Priya Jhalani and Manisha Pattanaik
ABV-Indian Institute of Information Technology and Management,
Gwalior, India
ABSTRACT
The downscaling of conventional MOSFETs has come to its fundamental limits. TFETs are very attractive
devices for low power applications because of their low off-current and potential for smaller sub threshold
slope. In this paper, the impact of various parameter variations on the performance of a DG-PNIN Tunnel
field effect transistor is investigated. In this work, variations in gate oxide material, source doping, channel
doping, drain doping, pocket doping and body thickness are studied and all these parameters are optimized
as performance boosters to give better current characteristics parameters. After optimization with all these
performance boosters, the device has shown improved performance with increased on-current and reduced
threshold voltage and the Ion/Ioff ratio is > 106
.
KEYWORDS
Tunnel Field Effect Transistor (TFET), Band to Band Tunneling (BTBT), DG-PIN TFET, DG-PNIN TFET,
Ion/Ioff Ratio
1. INTRODUCTION
Since the invention of transistor at Bell labs, the semiconductor industry has been witnessed a
record growth in terms of revenue and transistor count on a chip with the trend following the well
known Moore’s law [1]. With each generation of scaled technology, the transistor performance
has been improved. But, the aggressive scaling of MOSFET to meet various design constraints
like low power consumption, smaller area, higher speed etc. is approaching to its fundamental
limits [2-3]. To replace conventional MOSFET, new device structures are being investigated
which must be compatible to CMOS circuit architecture and technology. Due to their low sub
threshold swing (SS<60mv/dec), less susceptibility to short channel effects (SCEs), very low
leakage current, Tunnel Field Effect Transistor (TFET) has been considered as an alternative for
low power CMOS applications[4-12].
However the main disadvantage of TFET is, its low on-current. Therefore many TFET
performance enhancing solutions have been proposed to enhance on-current such as 1)
Modification of the TFET architecture (Like Hetero structures [13-15], Strained Silicon [16],
High-k gate dielectric [17-18]), 2) Use of small band gap materials at tunnel junction to reduce
the tunneling height [19-23]), 3) Use of a pocket at source channel tunnel junction to reduce the
tunneling width[24] etc. All these ideas are considered as performance boosters but, all of these
performance boosters are often applied independently. Therefore, in consideration to achieve
better current characteristics of TFET, as many as possible performance boosters should be
applied to the device.
Tunnel FETs are gated reverse biased PIN diodes, where the gate is used to modulate an effective
tunneling barrier height. The injection mechanism of Tunnel FETs is based on band to band
tunneling (BTBT). To switch the device on, the diode is reverse biased and a voltage is applied to
2. International Journal of VLSI design & Communication Systems (VLSICS) Vol.5, No.3, June 2014
48
the gate. When device is off, there will be a large tunnel barrier between the bands. Hence, charge
carriers will not tunnel from valence band to conduction band and a very small off-current will
flow. When the device is on, the bands are pushed down towards each other and current flows.
In this work, a double gate PNIN Tunnel field effect transistor (DG-PNIN-TFET) device is
designed and the impact of various parameter variations (like gate oxide material, doping, and
body thickness variations) has been investigated. Now based on the variation analyses, the device
parameters are optimized in order to work as performance boosters. After that, all these
performance boosters are applied to the device to get superior current characteristics.
2. DEVICE STRUCTURE AND SIMULATION PARAMETERS
By increasing the doping level of some part of channel region near the source region, electric
field can be increased. This small region is known as pocket and the device is called pocket doped
TFET [24]. In this paper, an n-type pocket layer is used near the p+ heavily doped source region.
The intrinsic region is lightly doped and drain region is n+ heavily doped. This device can be also
termed as PNIN TFET device. Fig.1 shows the basic device structure of double gate PNIN (DG-
PNIN) TFET. In this paper, double gate structure will be used due to better gate control provided
by both gates.
Figure 1. DG-PNIN-TFET Device Structure
The fundamental device parameters used for the device simulations are listed in table 1. All
simulations are performed using SILVACO ATLAS with nonlocal BTBT model, Shockley Read
Hall (SRH) and Fermi Dirac models [25] at room temperature with Vgs=1V.
Table 1. Parameters used in the simulation of the TFET
No. Parameter Value
1 Gate Oxide Thickness (tox) 3nm
2 Silicon Body Thickness (tBody) 15nm
3 Gate Length (Lg) 60nm
4 Gate Work Function 4.0ev
5 Channel Doping (Nchannel) 1017
atoms/cm3
6 Source Doping (p+
) and Drain Doping (n+
) 1020
atoms/cm3
7 Pocket Doping (Npocket) 1019
atoms/cm3
8 Pocket Length (Lpocket) 10nm
9 Gate Source Overlap (Lov) 5nm
A comparison graph of Ids-Vgs characteristics of various TFET topologies like SG-PIN, SG-
PNIN, DG-PIN and DG-PNIN TFET is presented in Fig. 2 and from the graph it can be seen that
3. International Journal of VLSI design & Communication Systems (VLSICS) Vol.5, No.3, June 2014
49
for PNIN-TFET device, on current is higher than the PIN -TFET device. The impact of double
gate with improved performance can also be seen in the graph. All these devices are simulated
with parameters listed in table 1 and SiO2 layer is used as gate oxide material.
Figure 2. Comparison of Ids-Vgs characteristics of DG-PNIN, DG-PIN, SG-PNIN and SG-PIN
TFET
3. IMPACT OF PARAMETER VARIATIONS
In this section the impact of various parameter variations on DG-PNIN TFET device is studied
and investigated.
3.1. Gate Oxide Material Variations
Effect of gate oxide material on the performance of DG-PNIN TFET is evaluated and the
materials that have been analyzed are SiO2, Si3N4 and HfO2 whose dielectric constant is 3.9, 7and
25 respectively. Fig.3 shows the Id-Vgs characteristics of the PNIN TFET device with different
gate oxide material. From the figure, it is clear that by using high-k gate oxide dielectric layer (i.e.
HfO2) the on-current is increased due to better gate coupling provided by the high-k dielectric.
With high-k dielectric, the Off-current is also increased but it is acceptable because it’s still very
low. So for all the further simulations HfO2 layer will be used as a gate oxide for better
performance.
3.2. Doping Variations
The doping levels of the Tunnel FET device must be carefully optimized in order to maximize
on current and Ion/Ioff ratio and minimize off-current. In DG-PNIN TFET, there are four types
of doping level and these are source, drain, intrinsic and pocket doping levels. When doping level
increases, the band gap reduces. With the reduction in band gap, current characteristics
parameters of the device will improve. Here, by using this fact, these doping levels are studied
and investigated.
4. International Journal of VLSI design & Communication Systems (VLSICS) Vol.5, No.3, June 2014
50
Figure 3. Ids-Vgs characteristics of DG-PNIN TFET with varying gate oxide materials
3.2.1 Source Doping Variations
In TFET tunneling takes place between source and intrinsic region therefore, source doping (Ns)
has a great effect on that tunneling phenomenon. The PNIN TFET device is simulated at various
source doping levels such as 1*1020
, 1.5*1020
and 2*1020
. Fig. 4 shows, the comparison graph of
Id-Vgs characteristics of DG-PNIN TFET device with varying source doping. As source doping
increases, on-current also increases due to electric field enhancement at tunneling junction. Thus,
the highest feasible source doping is preferable for DG-PNIN TFET optimization.
Figure 4. Ids-Vgs characteristics of DG-PNIN TFET with varying Source doping
5. International Journal of VLSI design & Communication Systems (VLSICS) Vol.5, No.3, June 2014
51
3.2.2 Drain Doping Variations
Now the next doping level is drain doping level and this doping level is important for another
reason. The effect of drain doping level on a device characteristic can be seen when it is operating
in negative region. Fig. 5 shows, the comparative graph of current characteristic of DG-PNIN
TFET device with varying drain doping. When the device is in positive region there is no effect
of drain doping variations on the current characteristic but, for negative region it shows the
ambipolar characteristics which are undesirable for the circuit designers. The DG-PNIN TFET
shows ambipolar behavior when drain doping level is equal to the source doping level. So for the
device optimization, a low drain doping is preferable but it should not be too low that the contact
formation becomes difficult.
Figure 5. Ids-Vgs characteristics of DG-PNIN TFET with varying Drain doping
3.2.3 Intrinsic Doping Variations
Now the next doping level is intrinsic region doping level. This doping level has a little effect on
Tunnel FET characteristics until the doping level becomes high. Fig. 6 shows the comparative
graph of current characteristic of device with varying intrinsic doping from 1015
atoms/cm3
to 1019
atoms/cm3
. When intrinsic doping is less than 1018
atoms/cm3
it has a little effect on the current
characteristics of DG-PNIN TFET device and exact concentration and type is not important
because at low concentration it does not affect the gates ability to control the band to band
tunneling at tunneling junction. But when the intrinsic doping level increases, off-current also
increases rapidly because at higher doping level intrinsic region is no more intrinsic. Thus a
lightly doped intrinsic region is preferable for DG-PNIN TFET optimization.
3.2.4 Pocket Doping Variations
Now the next and the last doping level is pocket doping level which has to be considered for
TFET optimization. In PNIN TFET device, an n-type layer is used as pocket in channel region
near the source region to increase Ion/Ioff ratio. So this pocket doping level also has a great effect
on the device characteristics. Here, the DG-PNIN TFET device is simulated at various pocket
doping levels and the comparative current characteristics of the device is shown in Fig. 7. When
the pocket doping increases or becomes equal to source doping then it gives a large amount of
off-current due to great amount of charge carrier available at the channel region which will tunnel
6. International Journal of VLSI design & Communication Systems (VLSICS) Vol.5, No.3, June 2014
52
from channel to source in off-state resulting off-current. And if the pocket doping is made too low
then the advantage of using pocket cannot be utilized. So balanced pocket doping level is
preferable for the DG-PNIN TFET optimization.
Figure 6. Ids-Vgs characteristics of DG-PNIN TFET with varying Intrinsic doping
Figure 7. Ids-Vgs characteristics of DG-PNIN TFET with varying Pocket doping
3.3. Body Thickness Variations
Another important parameter is body thickness of Silicon and TFET device is very much
sensitive to this thickness. Fig. 8 shows, the comparison of current characteristics of DG-PNIN
TFET device with varying body thickness. For larger body TFET device, the tunneling
probability reduces thus on-current also reduces. Therefore, thin body TFET structures are needed
for better performance. As body thickness becomes smaller than 10nm the on-current decreases in
a large amount due to decreased tunneling area for the current flow of the device. So for DG-
7. International Journal of VLSI design & Communication Systems (VLSICS) Vol.5, No.3, June 2014
53
PNIN TFET optimization, thin body structures are beneficial but it must stay above some critical
thickness so that on-current will not degrade.
Figure 8. Ids-Vgs characteristics of DG-PNIN TFET with varying Body thickness
4. DG-PNIN TFET OPTIMIZATION
In this section the optimization of fundamental DG-PNIN TFET parameters has been done based
on the parameter variation analysis. The main analysis that has been done is, the on-current
increases with the high-k gate oxide layer due to increased dielectric permittivity, At source
channel tunnel junction with increased source doping on-current also increases due to band
bending in between conduction and valance bands, to suppress ambipolar behavior drain doping
should be low, at high intrinsic doping off-current increases so low intrinsic doping is desirable,
pocket doping should be moderate because at high pocket doping off-current increases and low
doping leads to on-current decrement, Finally a thin body TFET structure is needed for current
improvement but it must be above 10nm because below 10nm the performance degrades badly
due to small tunneling area.
The Tunnel FETs have a low off-current and the potential for a small SS, but they suffer from a
lower on-current than conventional MOSFETs. Many solutions and topologies have been
proposed, but performance boosters are often suggested independently, like just adding a high-k
dielectric, or just using a thin body or just decreasing the band gap at the tunnel junction etc.
These techniques, though they increase on-current and reduce sub threshold swing, only have
limited power to improve device characteristics. In order to achieve superior characteristics for
Tunnel FETs, it is essential to apply as many boosters as possible to the same device, so that the
improvements in device performance are progressive. Then with the fully optimized device,
parameter fluctuations can be investigated in great detail.
With Wentzel-Kramer-Brillouin (WKB) approximation and taking the tunnel barrier as a
triangularly shaped potential barrier the band-to-band tunneling transmission is given by equation
1.
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54
In this equation Eg represents the band-gap of the material, m* is the effective mass of the
tunneling particle (material dependent), is the energy range over which tunneling takes place,
is the screening length and it depends on (permittivity of silicon), tox (oxide thickness), tSi
(Silicon body thickness) and (permittivity of gate oxide layer). To get higher current, tunneling
probability must be higher.
There are three main parameters that can help to increase T(E) of TFET device. These
parameters are m*, Eg and . Where m* and Eg are material dependent and by using small band
gap and smaller mass materials the tunneling probability can increase, is the device dependent
parameter. It depends on dielectric layer thickness, body thickness etc. and by optimizing these
parameters, can also be optimized and tunneling probability will increase. That is why m*, Eg
and are considered as performance boosters for TFET. With the help of these performance
boosters, TFET performance can be boosted to meet its target parameters, that are high on-current
(in the range of hundreds of mA), sub threshold slope (SS) less than 60mv/dec and Ion/Ioff ratio
greater than 10
6
. By achieving these target parameters, TFET can give the performance
comparable to CMOS in future technology. Based on the above all parameter variations analysis,
these parameters are optimized in such a manner that device current characteristics parameters
improves. The optimized parameters of the TFET device are listed in table 2. The column 2 of the
table 2 describes the parameter on which optimization has been performed and column 3 and 4
describes the value of these parameters before and after optimization.
. Table 2. DG-PNIN TFET parameters before and after optimization
No. Parameter Before Optimization After Optimization
1 Gate Oxide Material SiO2 HfO2
2 Source Doping (Ns) 1020
atoms/cm3
2*1020
atoms/cm3
3 Drain Doping (Nd) 1020
atoms/cm3
1019
atoms/cm3
4 Channel Doping (Nchannel) 1017
atoms/cm3
1015
atoms/cm3
5 Pocket Doping (Npocket) 1019
atoms/cm3
5*1018
atoms/cm3
6 Body Thickness(Tbody) 15nm 10nm
Now the DG-PNIN TFET device (Fig.1) is simulated in SILVACO ATLAS with all optimized
parameters with tox=3nm, Lg=60nm with nonlocal band to band tunneling (BTBT), Shockley
Read Hall (SRH) and Fermi Dirac models at room temperature. Fig. 9 shows the comparative
graph of current characteristics of the device with and without parameter optimization. From the
figure it is clear, that due to heavy source doping, lesser body thickness and due to high-k
dielectric layer the on-current is increased. Because, as source doing increases the electric field
increases at tunnel junction and because of that, band bending occurs between valence and
conduction bands. As intrinsic doping is reduced, so there will be lesser electric field in reverse
direction so, off-current is still low and in acceptable range.
A comparison of current characteristics parameters for before and after optimization has been
done in table 3. By applying all optimized parameters together the device performance improves
with on-current enhancement from 0.8µA to 45µA. Its off-current also increases slightly but still
very low in pA and lies within the acceptable range. The threshold voltage (Vth) for optimized
device is 0.39V calculated by constant current method. The Ion/Ioff ratio is greater than 106
which
is good.
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55
Figure 9. Comparison of Ids-Vgs characteristics of DG-PNIN-TFET before and after optimization
Table 3. DG-PNIN TFET current characteristics parameters before and after optimization
Ion Ioff Ion/Ioff Vth
Before Optimization 0.8µA 6pA 1.33*105
0.71V
After Optimization 45 µA 10pA 4.5*106
0.39V
5. CONCLUSIONS
A DG-PNIN Tunnel field effect transistor is designed and investigated with different parameter
variations. The main findings are:- (1) By using HfO2 as dielectric layer material instead of SiO2
dielectric layer material, the on-current increases due to better gate coupling provided by high-k
dielectric material (i.e. HfO2 ). (2) To improve the current characteristics, a high source doping
is beneficial to increase tunneling between source and channel regions by increasing electric
fields, a low drain doping is desirable to suppress the ambipolar behavior in negative regions and
a lightly doped intrinsic region (below 1018
atoms/cm3
) is desirable to decrease off-current in off-
state. (3) Smaller body thickness is required to increase tunneling probability by optimizing the
tunneling area of the device but, it must not be below from the critical thickness of body
(i.e. 10nm). Based on these analyses, an optimization has been performed on PNIN TFET device
parameters for on-current improvement. So resulting optimized device had a double gate, a high-k
dielectric layer, a high source doping, a low drain doping, a lightly doped intrinsic region, smaller
body thickness that should be above of its critical thickness. With these optimized parameters the
on-current increases from 0.8µA to 45µA with high Ion / Ioff ratio (>106
). But the on-current is still
in µA range and the further enhancement of on-current is required without any compromise in
off-current to meet the TFET target parameters.
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56
ACKNOWLEDGEMENTS
The authors would like to thank to VLSI Design Lab., ABV-Indian Institute of Information
Technology and management, Gwalior, for providing the computational resources.
REFERENCES
[1] G.E. Moore, “Cramming more components on to the integrated circuits”, Electronics, vol. 38, no. 8,
pp. 114-117, Apr. 1965.
[2] Seabaugh, Alan C.; Qin Zhang, “Low-Voltage Tunnel Transistors for Beyond CMOS Logic”,
Proceedings of the IEEE, vol.98, no.12, pp. 2095-2110, Dec. 2010.
[3] J. D. Meindehl, Q. Chen, J. A. Davis, “Limits of Silicon Nano electronics for Terascale
Integration”,Science, vol. 293, pp. 2044-2049, 2001.
[4] Pan, A.; Songtao Chen; Chi On Chui, “Electrostatic Modeling and Insights Regarding Multigate
Lateral Tunneling Transistors”, Electron Devices, IEEE Transactions on, vol.60, no.9, pp. 2712-2720,
Sept. 2013.
[5] E. Gnani, A. Gnudi, S. Reggiani, and G. Baccarani, “Drain-conductance optimization in nanowire
TFETs by means of a physics-based analytical model”, Solid-State Electron., vol. 84, pp. 96-102, Jun.
2013.
[6] A. Mallik, and A. Chattopadhyay, “The impact of fringing field on the device performance of a p-
channel tunnel field-effect transistor with a high-k gate dielectric”, IEEE Transactions on Electron
Devices, Vol. 59, No. 2, pp. 277-282, 2012.
[7] A. M. Ionescu, and H. Riel, “Tunnel field-effect transistors as energy-efficient electronic switches”,
Nature, Vol. 479, pp. 329-337, 2011.
[8] D. Leonelli, A. Vandooren, R. Rooyackers, S. De Gendt, M. M. Heyns, and G. Groeseneken, “Drive
current enhancement in p-tunnel FETs by optimization of the process conditions,” Solid-State
Electron., vol. 65, no.6, pp. 28-32, Nov. 2011.
[9] A. Chattopadhyay, and A. Mallik, “Impact of a spacer dielectric and a gate overlap/underlap on the
device performance of a tunnel field-effect transistor”, IEEE Transactions on Electron Devices, Vol.
58, No. 3, pp. 677-683, 2011.
[10] W. Lee, and W. Choi, “Influence of inversion layer on tunneling field-effect transistors”, IEEE
Electron Device Lett., Vol. 32, No. 9,pp. 1191-1193, 2011.
[11] W. Y. Choi, B.-G. Park, J. D. Lee, and T.-J. K. Liu, “Tunneling field-effect transistors (TFETs) with
sub threshold swing (SS) less than 60 mV/dec,” IEEE Electron Device Lett., vol. 28, no. 8, pp. 743–
745, Aug. 2007.
[12] Brinda Bhowmick, Srimanta Baishya,” An Analytical Model for Fringing Capacitance in Double gate
Hetero Tunnel FET and Analysis of effect of Traps and Oxide charges on Fringing Capacitance”, in
International Journal of VLSI design & Communication Systems (VLSICS), vol. 3, no.1, Feb. 2012.
[13] A. S. Verhulst, W. G. Vandenberghe, K. Maex, S. De Gendt, M. M. Heyns, and G. Groeseneken,”
Complementary silicon-based heterostructure tunnel-FETs with high tunnel rates,” IEEE Electron
Device Lett., vol. 29, no. 12, pp. 1398–1401, Dec. 2008.
[14] L. Wang, E. Yu, Y. Taur and P. Asbeck, “Design of tunneling fieldeffect transistors based on
staggered hetojunctions for ultralowpower applications,” IEEE Electron Device Lett., vol. 31, no. 5,
pp- 431-433, May 2010.
[15] O. M. Nayfeh, C. N. Chleirigh, J. Hennessy, L. Gomez, J. L. Hoyt and D. A. Antoniadis, “Design of
Tunneling Field-Effect Transisitors Using Strained-Silicon/Strained-Germanium Type-II Staggered
Heterojunctions,” IEEE Electron Device Lett., vol. 29, no. 9, pp- 1074-1077, Sept. 2008.
[16] K. Boucart, W. Riess, and A. M. Ionescu, “Lateral strain profile as key technology booster for all-
silicon Tunnel FETs,” IEEE Electron Device Lett.,vol.30,no. 6, pp. 656-658, Jun.2009.
[17] K. Boucart and A. M. Ionescu, “Double-gate tunnel FET with high-κ gate dielectric,” IEEE
Trans.Electron Devices, vol. 54, no. 7, pp. 1725–1733, Jul. 2007.
[18] M. Schlosser, K. K. Bhuwalka, M. Sauter, T. Zilbauer, T. Sulima, and I. Eisele, “Fringing-induced
drain current improvement in the tunnel fieldeffect transistor with high-κ gate dielectrics,” IEEE
Trans. Electron Devices, vol. 56, no. 1, pp. 100–108, Jan. 2009.
[19] Beneventi, G.B.; Gnani, E.; Gnudi, A.; Reggiani, S.; Baccarani, G., “Dual-Metal-Gate InAs Tunnel
FET With Enhanced Turn-On Steepness and High On-Current,” Electron Devices, IEEE Transactions
on, vol.61, no.3, pp. 776-784, March 2014.
11. International Journal of VLSI design & Communication Systems (VLSICS) Vol.5, No.3, June 2014
57
[20] A. Dey, B. Borg, B. Ganjipour, M. Ek, K. Dick, E. Lind, P. Nilsson, C. Thelander, and L.
Wernersson, “High current density InAsSb/GaSb tunnel field effect transistors,” in Device Research
Conference (DRC), 70th Annual, pp. 205-206, 18-20 June 2012.
[21] Moselund, K. E.; Schmid, H.; Bessire, C.; Bjork, M.T.; Ghoneim, H.; Riel, H., “InAs-.Si Nanowire
Heterojunction Tunnel FETs,” Electron Device Letters, IEEE, vol.33, no.10, pp. 1453-1455, Oct.
2012.
[22] Guangle Zhou; Li, R.; Vasen, T.; Qi, M.; Chae, S.; Lu, Y.; Zhang, Q.; Zhu, H.; Kuo, J.-M.; Kosel, T.;
Wistey, M.; Fay, P.; Seabaugh, A.; Huili Xing, “Novel gate-recessed vertical InAs/GaSb TFETs with
record high ION of 180 µA/µAm at VDS = 0.5 V,” Electron Devices Meeting (IEDM), IEEE
International , pp.32.6.1-32.6.4, 10-13 Dec. 2012.
[23] Zhao, H.; Chen, Y.; Wang, Y.; Zhou, F.; Xue, F.; Lee, J., “InGaAs Tunneling Field-Effect-Transistors
With Atomic-Layer-Deposited Gate Oxides,” Electron Devices, IEEE Transactions on, vol.58, no.9,
pp. 2990-2995, Sept. 2011.
[24] Ritesh Jhaveri, Venkatagirish Nagavarapu,Jason C. S. Woo, “Effect of Pocket Doping and Annealing
Schemes on the source -Pocket Tunnel Field-Effect Transistor” in IEEE transaction on Electron
Device. Vol.58, no. 1,pp. 80-86, Jan 2011.
[25] Atlas User manual, Silvaco Int., Santa Clara CA, 2013.