The document summarizes the performance analysis of a modified quasi-static energy recovery logic (MQSERL) circuit. Some key points:
1) MQSERL aims to improve energy efficiency over previous quasi-static energy recovery logic (QSERL) circuits by reducing non-adiabatic losses. It replaces diodes with transistors to minimize voltage drop.
2) The circuit uses two complementary sinusoidal power clocks for evaluation and hold phases. During evaluation, the load capacitance is slowly charged or discharged via transistors.
3) Simulation results show the MQSERL inverter has 30% lower energy dissipation than CMOS and 20% lower than QSERL up to 20MHz and 20fF
Space Vector of Three Phase Three level Neutral Point Clamped Quasi Z Source ...IJTET Journal
Space vector of three phase three level neutral point clamped quasi z source inverter is proposed in this paper. Space vector modulation is the pulse width modulation consists of number of switching states. Space vector pulse width modulation technique utilizes 15% more power from DC source. Harmonics are reduced by the presence of switching states. Quasi Z-source inverter is advanced topologies which performs both boost and buck operation of a converter. The proposed inverter obtains continuous input current and the boost converter is not needed. So, maximum voltage can be obtained in the load and system complexity is reduced. Maximum power can be obtained from the solar panel by using MPPT. The implementation of MPPT is to operate a PV array under constant voltage and power reference to modify the duty cycle of the inverter.The simulation of proposed topology is done in MATLAB/SIMULINK software.
Design and Control of Switched-Inductor Quasi-Z-Source Inverter for Photovolt...irjes
The conventional Z-Source Inverter (ZSI) used for photovoltaic applications has certain
shortcomings such as high stress across the passive components and low boost factor. This paper presents the
design and analysis of three phase switched inductor quasi Z-source inverter (SL-QZSI) for photovoltaic (PV)
applications. The wide voltage gain and the compensation for dead time effect of SL-QZSI with the help of
shoot-through states makes it suitable for PV application. Modulation strategies such as Simple boost,
Maximum boost and Constant maximum boost control methods are investigated for the operation and control
of SL-QZSI. PV source is modeled in MATLAB and incremental & conductance MPPT algorithm is
implemented .Simulation of the SL-QZSI circuit powered by PV source is carried out by implementing
maximum boost control method and the performance parameters are discussed.
Design of a Low Power Combinational Circuit by using Adiabatic LogicIJERA Editor
A novel low power and Positive Feedback Adiabatic Logic (PFAL) combinational low power circuit is presented in this paper. The power consumption and general characteristics of the PFAL combinationallow power circuit arethen compared against two combinational low power circuit Efficient Charge Recovery Logic (ECRL), Conventional CMOS. The proposed PFAL combinational low power circuit design was proven to be superior to the other two designs in power dissipation and area. The combination of low power and low transistor count makes the new PFAL cell a viable option for low power design.
POWER COMPARISON OF CMOS AND ADIABATIC FULL ADDER CIRCUITSVLSICS Design
Full adders are important components in applications such as digital signal processors (DSP) architectures and microprocessors. Apart from the basic addition adders also used in performing useful operations such as subtraction, multiplication, division, address calculation, etc. In most of these systemsthe adder lies in the critical path that determines the overall performance of the system. In this paper conventional complementary metal oxide emiconductor (CMOS) and adiabatic adder circuits are analyzed in terms of power and transistor count using 0.18UM technology.
LCL Filter for Grid Connected VSC Converter
Comprehensive analysis and modeling of the three-phase LCL filter for VSC converters, suitable for wind energy or photovoltaic applications.
Space Vector of Three Phase Three level Neutral Point Clamped Quasi Z Source ...IJTET Journal
Space vector of three phase three level neutral point clamped quasi z source inverter is proposed in this paper. Space vector modulation is the pulse width modulation consists of number of switching states. Space vector pulse width modulation technique utilizes 15% more power from DC source. Harmonics are reduced by the presence of switching states. Quasi Z-source inverter is advanced topologies which performs both boost and buck operation of a converter. The proposed inverter obtains continuous input current and the boost converter is not needed. So, maximum voltage can be obtained in the load and system complexity is reduced. Maximum power can be obtained from the solar panel by using MPPT. The implementation of MPPT is to operate a PV array under constant voltage and power reference to modify the duty cycle of the inverter.The simulation of proposed topology is done in MATLAB/SIMULINK software.
Design and Control of Switched-Inductor Quasi-Z-Source Inverter for Photovolt...irjes
The conventional Z-Source Inverter (ZSI) used for photovoltaic applications has certain
shortcomings such as high stress across the passive components and low boost factor. This paper presents the
design and analysis of three phase switched inductor quasi Z-source inverter (SL-QZSI) for photovoltaic (PV)
applications. The wide voltage gain and the compensation for dead time effect of SL-QZSI with the help of
shoot-through states makes it suitable for PV application. Modulation strategies such as Simple boost,
Maximum boost and Constant maximum boost control methods are investigated for the operation and control
of SL-QZSI. PV source is modeled in MATLAB and incremental & conductance MPPT algorithm is
implemented .Simulation of the SL-QZSI circuit powered by PV source is carried out by implementing
maximum boost control method and the performance parameters are discussed.
Design of a Low Power Combinational Circuit by using Adiabatic LogicIJERA Editor
A novel low power and Positive Feedback Adiabatic Logic (PFAL) combinational low power circuit is presented in this paper. The power consumption and general characteristics of the PFAL combinationallow power circuit arethen compared against two combinational low power circuit Efficient Charge Recovery Logic (ECRL), Conventional CMOS. The proposed PFAL combinational low power circuit design was proven to be superior to the other two designs in power dissipation and area. The combination of low power and low transistor count makes the new PFAL cell a viable option for low power design.
POWER COMPARISON OF CMOS AND ADIABATIC FULL ADDER CIRCUITSVLSICS Design
Full adders are important components in applications such as digital signal processors (DSP) architectures and microprocessors. Apart from the basic addition adders also used in performing useful operations such as subtraction, multiplication, division, address calculation, etc. In most of these systemsthe adder lies in the critical path that determines the overall performance of the system. In this paper conventional complementary metal oxide emiconductor (CMOS) and adiabatic adder circuits are analyzed in terms of power and transistor count using 0.18UM technology.
LCL Filter for Grid Connected VSC Converter
Comprehensive analysis and modeling of the three-phase LCL filter for VSC converters, suitable for wind energy or photovoltaic applications.
Compact low power high slew-rate cmos buffer amplifier with power gating tech...VLSICS Design
A qualitative analysis of different parameters such as Phase noise, Slew rate and tranconductance by using
power gating reduction technique is presented. The circuit achieves the large driving capability by
employing simple comparators to sense the transients of the input to turn on the output stages, which are
statically off in the stable state. The effect of the different number of transistors and their topologies on the
phase noise and Slew rate is analyzed. Good agreement between qualitative and quantitative measurements
is observed. Scope of reducing of Noise and avoidance of Leakage due to various sources is discussed.
Performance and Analysis of Hybrid Multilevel Inverter fed Induction Motor Drivernvsubbarao koppineni
This paper presents the Five level inverter with single DC source which is used to generate a five level output with two bridges and six switches and performance of three phase induction motor is analyzed when connected to PV array For this two identical dc sources of 50V each for two bridges in five levels using Multi level inverter and five level output is obtained by using a single DC source of 100V with six switches. A virtual DC source (charged capacitor acts as virtual DC source) is used for getting the output. The same technique is implemented for three-phase circuit i.e. by using single DC source. An asynchronous motor (three-phase) is connected as load and its performance characteristics are analyzed. And further the DC source is replaced by a renewable resource such as solar panels, fuel cell etc. and DC voltage is obtained. Performance characteristics of three-phase asynchronous motor are analyzed with PV array connected. The method can be easily extended to an m-level inverter.
A DC Inrush Current Minimisation Method using Modified Z-Source Inverter in A...IAES-IJPEDS
The adjustable speed drives employ PWM converter-inverter system in order
to obtain unity power factor. The DC inrush current in DC link capacitors of
the rectifier limits the operation of power devices. Hence, this paper proposes
a new approach to reduce the DC inrush current by employing modified
Z-source inverter in a Adjustable Speed Drive system. The operating
principles, design procedure and simulation results are shown and compared
with the conventional Z-Source inverter.
Control Method for Unified Power Quality Conditioner Using Fuzzy Based Nine-S...IJERA Editor
A nine-switch power converter having two sets of out-put terminals was recently proposed in place of the
traditional back-to-back power converter that uses 12 switches in total. The nine-switch converter has already
been proven to have certain advantages, in addition to its component saving topological feature. Despite these
advantages, the nine-switch converter has so far found limited applications due to its many perceived
performance tradeoffs like requiring an oversized dc-link capacitor, limited amplitude sharing, and constrained
phase shift between its two sets of output terminals. Instead of accepting these tradeoffs as limitations, a nineswitch
power conditioner is proposed here that virtually “converts” most of these topological short comings into
interesting performance advantages. Aiming further to reduce its switching losses, an appropriate discontinuous
modulation scheme is proposed and studied here in detail to doubly ensure that maxi-mal reduction of
commutations is achieved. With an appropriately designed control scheme then incorporated, the nine-switch
converter is shown to favorably raise the overall power quality in experiment, hence justifying its role as a
power conditioner at a reduced semiconductor cost.
A three level quasi-two-stage single-phase pfc converter with flexible output...LeMeniz Infotech
A three level quasi-two-stage single-phase pfc converter with flexible output voltage and improved conversion efficiency
To Get this projects Call : 9566355386 / 99625 88976
Visit : www.lemenizinfotech.com / www.ieeemaster.com
Mail : projects@lemenizinfotech.com
In this paper the multicarrier pulse width modulation (MCPWM) with multi value DC voltage source multilevel inverter is presented. These MLI’s are suitable in high voltage & high power application due to their ability to synthesize waveforms with better harmonic spectrum. Seven level inverter is simulated using MATLAB/Simulink. The use of Photovoltaic Cell as a DC source for the multilevel Inverter is proposed here.
An operational amplifier with recycling folded cascode topology and adaptive ...VLSICS Design
This paper presents a highly adaptive operational amplifier with high gain, high bandwidth, high speed
and low power consumption. By adopting the recycling folded cascode topology along with an adaptivebiasing
circuit, this design achieves high performance in terms of gain-bandwidth product (GBW) and slew
rate (SR). This single stage op-amp has been designed in 0.18μm technology with a power supply of 1.8V
and a 5pF load. The simulation results show that the amplifier achieved a GBW of 335.5MHz, Unity Gain
Bandwidth of 247.1MHz and a slew rate of 92.8V/μs.
SIMULATION STUDY OF QZSI Z-SOURCE INVERTER FOR RESISTIVE AND INDUCTIVE LOADijiert bestjournal
This paper involves design and simulation of a step up dc/dc converter topology connected with the chopper circuit
intended for resistive and inductive load. The topology contains voltage fed qzsi Z Source Inverter (qzsi), a high
frequency isolation transformer with reduced turn’s ratio, a Voltage Doubler Rectifier (VDR). A carrier based PulseWidth
Modulation (PWM) which employs shoot through state strategy for qzsi is implemented which gives significantly
high voltage gain compared to traditional PWM techniques. To improve the power density of converter, three phase aclink
and three-phase VDR is implemented. The designed step up dc/dc converter is tested for various kinds of resistive
and inductive load in MATLAB/SIMULIKN platform.
A Sub Threshold Source Coupled Logic Based Design of Low Power CMOS Analog Mu...VLSICS Design
A novel approach for designing Ultra Low Power and wide dynamic range circuit for multiplexing analog
signals is presented. The design operates in weak inversion (Sub threshold) region and uses Source -
Coupled Logic ( SCL) circuit. The bias current of the SCL gates is varied to scale down linearly the power
consumption and the operating frequency. The multiplexer design employs CMOS transistors as
transmission gate with dynamic threshold voltage. The design exhibits low power dissipation, high
dynamic range and good linearity. The design was implemented in 180 nm technology and was operated at
a supply voltage of 400 mV with a bias current ranging in the order of few Pico-amperes. The ON and
OFF resistance of the transmission gate achieved were 27 ohms and 10 M ohms respectively. The power
dissipation achieved is around 0.79 μW for a dynamic range of 1μV to 0.4 V.
This paper presents investigation and performance analysis of novel down sampling based clamping SV PWM technique for diode and cascaded Multi-level Invereter fed to Induction motor drive. A novel down sampling based clamping SVPWM has developed by adding triangular off set to sinusoidal fundamental waveform is modified by down sampling the reference wave by order of 10 so this technique is called clamping space vector pulse width modulation techniques such as PD, POD and APOD. so as to shift the lower order harmonics to higher order side. This novel carrier is compared with the offset injected space vector reference waveform to generate the required PWM pulses to the inverter. To analyze the performance of the proposed PWM technique it is implemented on seven level diode and cascaded Multi-level Inverter using Matlab/Simulink software tool for output line, phase voltage, currents, speed, torque and Total harmonic distortion analysis.
Now day’s the power factor has become a major problem in power system to improve the power quality of the grid, as power factor is affected on the grid due to the nonlinear loads connected to it. Single phase bridgeless AC/DC power factor correction (PFC) topology to improve the power factor as well as the total harmonic distortion (THD) of the utility grid is proposed. By removing the input bridge in conventional PFC converters, the control circuit is simplified; the total harmonics distortion (THD) and power factor (PF) are improved. The PI controller operates in two loops one is the outer control loop which calculates the reference current through LC filter and signal processing. Inner current loop generates PWM switching signals through the PI controller. The output of the proposed PFC topology is verified for prototype using MATLAB circuit simulations. The experimental system is developed, and the simulation results are obtained.
Modeling and Analysis of Transformerless High Gain Buck-boost DC-DC ConvertersIAES-IJPEDS
This paper proposes a transfomerless switched capacitor buck boost converter model, which provides higher voltage gain and higher efficiency when compared to the conventional buck boost converter. The averaged model based on state- space description is analyzed in the paper. The simulation results are presented to confirm the capability of the converter to generate high voltage ratios. The comparison between the proposed model and the traditional model is also provided to reveal the improvement. The proposed converter is suitable for for a wide application which requires high step-up DC-DC converters such as DC micro-grids and solar electrical energy.
SINGLE-PORT FIVE-TRANSISTOR SRAM CELL WITH REDUCED LEAKAGE CURRENT IN STANDBYVLSICS Design
In this paper, a new single-port five-transistor (5T) Static Random Access Memory (SRAM) cell with
integrated read/write assist is proposed. Amongst the assist circuitry, a voltage control circuit is coupled to
the sources corresponding to driver transistors of each row memory cells. This configuration is aimed to
control the source voltages of driver transistors under different operating modes. Specifically, during a
write operation, by means of sizing the driver transistor close to bitline to resolve the write ‘1’ issue. In
addition, associated with a two-stage reading mechanism to increase the reading speed and to avoid
unnecessary power consumption. Finally, with the standby start-up cir
Compact low power high slew-rate cmos buffer amplifier with power gating tech...VLSICS Design
A qualitative analysis of different parameters such as Phase noise, Slew rate and tranconductance by using
power gating reduction technique is presented. The circuit achieves the large driving capability by
employing simple comparators to sense the transients of the input to turn on the output stages, which are
statically off in the stable state. The effect of the different number of transistors and their topologies on the
phase noise and Slew rate is analyzed. Good agreement between qualitative and quantitative measurements
is observed. Scope of reducing of Noise and avoidance of Leakage due to various sources is discussed.
Performance and Analysis of Hybrid Multilevel Inverter fed Induction Motor Drivernvsubbarao koppineni
This paper presents the Five level inverter with single DC source which is used to generate a five level output with two bridges and six switches and performance of three phase induction motor is analyzed when connected to PV array For this two identical dc sources of 50V each for two bridges in five levels using Multi level inverter and five level output is obtained by using a single DC source of 100V with six switches. A virtual DC source (charged capacitor acts as virtual DC source) is used for getting the output. The same technique is implemented for three-phase circuit i.e. by using single DC source. An asynchronous motor (three-phase) is connected as load and its performance characteristics are analyzed. And further the DC source is replaced by a renewable resource such as solar panels, fuel cell etc. and DC voltage is obtained. Performance characteristics of three-phase asynchronous motor are analyzed with PV array connected. The method can be easily extended to an m-level inverter.
A DC Inrush Current Minimisation Method using Modified Z-Source Inverter in A...IAES-IJPEDS
The adjustable speed drives employ PWM converter-inverter system in order
to obtain unity power factor. The DC inrush current in DC link capacitors of
the rectifier limits the operation of power devices. Hence, this paper proposes
a new approach to reduce the DC inrush current by employing modified
Z-source inverter in a Adjustable Speed Drive system. The operating
principles, design procedure and simulation results are shown and compared
with the conventional Z-Source inverter.
Control Method for Unified Power Quality Conditioner Using Fuzzy Based Nine-S...IJERA Editor
A nine-switch power converter having two sets of out-put terminals was recently proposed in place of the
traditional back-to-back power converter that uses 12 switches in total. The nine-switch converter has already
been proven to have certain advantages, in addition to its component saving topological feature. Despite these
advantages, the nine-switch converter has so far found limited applications due to its many perceived
performance tradeoffs like requiring an oversized dc-link capacitor, limited amplitude sharing, and constrained
phase shift between its two sets of output terminals. Instead of accepting these tradeoffs as limitations, a nineswitch
power conditioner is proposed here that virtually “converts” most of these topological short comings into
interesting performance advantages. Aiming further to reduce its switching losses, an appropriate discontinuous
modulation scheme is proposed and studied here in detail to doubly ensure that maxi-mal reduction of
commutations is achieved. With an appropriately designed control scheme then incorporated, the nine-switch
converter is shown to favorably raise the overall power quality in experiment, hence justifying its role as a
power conditioner at a reduced semiconductor cost.
A three level quasi-two-stage single-phase pfc converter with flexible output...LeMeniz Infotech
A three level quasi-two-stage single-phase pfc converter with flexible output voltage and improved conversion efficiency
To Get this projects Call : 9566355386 / 99625 88976
Visit : www.lemenizinfotech.com / www.ieeemaster.com
Mail : projects@lemenizinfotech.com
In this paper the multicarrier pulse width modulation (MCPWM) with multi value DC voltage source multilevel inverter is presented. These MLI’s are suitable in high voltage & high power application due to their ability to synthesize waveforms with better harmonic spectrum. Seven level inverter is simulated using MATLAB/Simulink. The use of Photovoltaic Cell as a DC source for the multilevel Inverter is proposed here.
An operational amplifier with recycling folded cascode topology and adaptive ...VLSICS Design
This paper presents a highly adaptive operational amplifier with high gain, high bandwidth, high speed
and low power consumption. By adopting the recycling folded cascode topology along with an adaptivebiasing
circuit, this design achieves high performance in terms of gain-bandwidth product (GBW) and slew
rate (SR). This single stage op-amp has been designed in 0.18μm technology with a power supply of 1.8V
and a 5pF load. The simulation results show that the amplifier achieved a GBW of 335.5MHz, Unity Gain
Bandwidth of 247.1MHz and a slew rate of 92.8V/μs.
SIMULATION STUDY OF QZSI Z-SOURCE INVERTER FOR RESISTIVE AND INDUCTIVE LOADijiert bestjournal
This paper involves design and simulation of a step up dc/dc converter topology connected with the chopper circuit
intended for resistive and inductive load. The topology contains voltage fed qzsi Z Source Inverter (qzsi), a high
frequency isolation transformer with reduced turn’s ratio, a Voltage Doubler Rectifier (VDR). A carrier based PulseWidth
Modulation (PWM) which employs shoot through state strategy for qzsi is implemented which gives significantly
high voltage gain compared to traditional PWM techniques. To improve the power density of converter, three phase aclink
and three-phase VDR is implemented. The designed step up dc/dc converter is tested for various kinds of resistive
and inductive load in MATLAB/SIMULIKN platform.
A Sub Threshold Source Coupled Logic Based Design of Low Power CMOS Analog Mu...VLSICS Design
A novel approach for designing Ultra Low Power and wide dynamic range circuit for multiplexing analog
signals is presented. The design operates in weak inversion (Sub threshold) region and uses Source -
Coupled Logic ( SCL) circuit. The bias current of the SCL gates is varied to scale down linearly the power
consumption and the operating frequency. The multiplexer design employs CMOS transistors as
transmission gate with dynamic threshold voltage. The design exhibits low power dissipation, high
dynamic range and good linearity. The design was implemented in 180 nm technology and was operated at
a supply voltage of 400 mV with a bias current ranging in the order of few Pico-amperes. The ON and
OFF resistance of the transmission gate achieved were 27 ohms and 10 M ohms respectively. The power
dissipation achieved is around 0.79 μW for a dynamic range of 1μV to 0.4 V.
This paper presents investigation and performance analysis of novel down sampling based clamping SV PWM technique for diode and cascaded Multi-level Invereter fed to Induction motor drive. A novel down sampling based clamping SVPWM has developed by adding triangular off set to sinusoidal fundamental waveform is modified by down sampling the reference wave by order of 10 so this technique is called clamping space vector pulse width modulation techniques such as PD, POD and APOD. so as to shift the lower order harmonics to higher order side. This novel carrier is compared with the offset injected space vector reference waveform to generate the required PWM pulses to the inverter. To analyze the performance of the proposed PWM technique it is implemented on seven level diode and cascaded Multi-level Inverter using Matlab/Simulink software tool for output line, phase voltage, currents, speed, torque and Total harmonic distortion analysis.
Now day’s the power factor has become a major problem in power system to improve the power quality of the grid, as power factor is affected on the grid due to the nonlinear loads connected to it. Single phase bridgeless AC/DC power factor correction (PFC) topology to improve the power factor as well as the total harmonic distortion (THD) of the utility grid is proposed. By removing the input bridge in conventional PFC converters, the control circuit is simplified; the total harmonics distortion (THD) and power factor (PF) are improved. The PI controller operates in two loops one is the outer control loop which calculates the reference current through LC filter and signal processing. Inner current loop generates PWM switching signals through the PI controller. The output of the proposed PFC topology is verified for prototype using MATLAB circuit simulations. The experimental system is developed, and the simulation results are obtained.
Modeling and Analysis of Transformerless High Gain Buck-boost DC-DC ConvertersIAES-IJPEDS
This paper proposes a transfomerless switched capacitor buck boost converter model, which provides higher voltage gain and higher efficiency when compared to the conventional buck boost converter. The averaged model based on state- space description is analyzed in the paper. The simulation results are presented to confirm the capability of the converter to generate high voltage ratios. The comparison between the proposed model and the traditional model is also provided to reveal the improvement. The proposed converter is suitable for for a wide application which requires high step-up DC-DC converters such as DC micro-grids and solar electrical energy.
SINGLE-PORT FIVE-TRANSISTOR SRAM CELL WITH REDUCED LEAKAGE CURRENT IN STANDBYVLSICS Design
In this paper, a new single-port five-transistor (5T) Static Random Access Memory (SRAM) cell with
integrated read/write assist is proposed. Amongst the assist circuitry, a voltage control circuit is coupled to
the sources corresponding to driver transistors of each row memory cells. This configuration is aimed to
control the source voltages of driver transistors under different operating modes. Specifically, during a
write operation, by means of sizing the driver transistor close to bitline to resolve the write ‘1’ issue. In
addition, associated with a two-stage reading mechanism to increase the reading speed and to avoid
unnecessary power consumption. Finally, with the standby start-up cir
LEAKAGE REDUCTION TECHNIQUE AND ANALYSIS OF CMOS D FLIP FLOPVLSICS Design
The expansion of battery operated portable device is continuously increasing the demand for low
power, minimum delay and high speed integrated circuits. In many of the portable devices the
standby periods are longer than the active periods and thus consume more power in the standby
state [2]. It is extremely important to reduce the power consumption in the standby mode. In
today’s high performance integrated circuits the leakage power contributes major power
consumption than overall total power consumption. In deep submicron circuits the leakage
power increases than the dynamic power and also in the circuits when there are no transitions at
the input and the transistors are in steady state [1]. Leakage power is mainly due to leakage
current that flows in the circuit when the circuit is operated in sleep or standby mode. The
leakage current is composed of sub-threshold leakage current, gate current, gate leakage current
and reverses biased leakage. Among all leakages, sub-threshold leakage contributes major part of
the leakage. The sub-threshold leakage current of a metal oxide semiconductor device is
expressed as
Where µo is the mobility of electrons/holes, Cox denotes oxide
capacitance of gate per unit area, W and L are width and channel length of MOS device
respectively, Vgs is the gate to source voltage Vt is the thermal voltage and η is the swing
coefficient. The contents of this paper are organized as follows: Section 2 descr
MINIMALLY BUFFERED ROUTER USING WEIGHTED DEFLECTION ROUTING FOR MESH NETWORK ...VLSICS Design
The scalability, modularity and massive parallelism exhibited by Network on chip(NoC) interconnects
make them highly suitable for the inter core communication framework of multiprocessor system-on-chip
(MPSoC) designs. Routers play the most vital role in transferring flits through the network, hence efficient
microarchitecture and cost effective routing algorithms are highly essential for modern NoC routers.
Elimination of buffers and deflection routing help to achieve energy and area efficiency of these routers.
The advantages of bufferless and buffered designs can be combined by using a minimum number of side
buffers to store a fraction of deflection flits in the router. In this paper, we propose a routing algorithm
based on weighted deflection of flits for minimally buffered deflection routers. Evaluations on 4x4 and 8x8
mesh NoC using synthetic workloads as well as benchmark applications demonstrate that deflection rate
and average network latency are significantly reduced in comparison with the state of the art NoC routers.
Performance analysis of the newly proposed algorithm shows that the network saturation point improves
by 26% compared to earlier designs in this domain
SMART MULTICROSSBAR ROUTER DESIGN IN NOCVLSICS Design
This paper gives the innovative idea of designing a router using multicrossbar switch in Network on
Chip(NoC) . In Network-on-Chip architectures the input buffer can consume a large portion of the total
power. Eliminating all input buffer would result in increased power consumption at high load, while
reducing the size of input buffer degrades the performance. In this paper we have proposed a muticrossbar
router design using elastic buffer by combining the advantage of both buffered and buffer less network. In
the proposed design Power Delay Product is reduced by around 37 .91% as compared to baseline router
Impact of parameter variations and optimization on dg pnin tunnel fetVLSICS Design
The downscaling of conventional MOSFETs has come to its fundamental limits. TFETs are very attractive
devices for low power applications because of their low off-current and potential for smaller sub threshold
slope. In this paper, the impact of various parameter variations on the performance of a DG-PNIN Tunnel
field effect transistor is investigated. In this work, variations in gate oxide material, source doping, channel
doping, drain doping, pocket doping and body thickness are studied and all these parameters are optimized
as performance boosters to give better current characteristics parameters. After optimization with all these
performance boosters, the device has shown improved performance with increased on-current and reduced
threshold voltage and the Ion/Ioff ratio is > 106.
Designing High-Speed, Low-Power Full Adder Cells Based on Carbon Nanotube Tec...VLSICS Design
This article presents novel high speed and low power full adder cells based on carbon nanotube field effect
transistor (CNFET). Four full adder cells are proposed in this article. First one (named CN9P4G) and
second one (CN9P8GBUFF) utilizes 13 and 17 CNFETs respectively. Third design that we named
CN10PFS uses only 10 transistors and is full swing. Finally, CN8P10G uses 18 transistors and divided into
two modules, causing Sum and Cout signals are produced in a parallel manner. All inputs have been used
straight, without inverting. These designs also used the special feature of CNFET that is controlling the
threshold voltage by adjusting the diameters of CNFETs to achieve the best performance and right voltage
levels. All simulation performed using Synopsys HSPICE software and the proposed designs are compared
to other classical and modern CMOS and CNFET-based full adder cells in terms of delay, power
consumption and power delay product.
Optimal Unate Decomposition Method for Synthesis of Mixed CMOS VLSI CircuitsVLSICS Design
Static CMOS logic style is often the choice of designers for synthesizing low power circuits. This style is
robust in terms of noise integrity however, it offers less speed. Domino logic style, as an alternative is often
found in critical paths of various large scale high performance circuits. Yet, due to high switching activity
they are not suitable for synthesis of low power circuits. To achieve both power and speed benefits, we
propose a method of designing circuit using mixed CMOS logic style, taking advantages of both static and
Domino logic styles. For a given circuit, we extract the unate and binate components using a unate
decomposition algorithm. These are optimized such that the resulting circuit is optimum in terms of power,
area and delay. To do this, a multi-objective genetic algorithm is employed. The optimized unate and binate
blocks are mapped using Domino and static cell libraries, respectively. Testing the efficacy of our
approach with ISCAS85 and MCNC89 benchmark circuits showed an improvement of 25% in delay and
22% in transistor count with 12% more power dissipation compared to circuits with only static CMOS
logic. Thus, mixed CMOS circuits are promising in high speed and area constraint applications.
DESIGN OF IMPROVED RESISTOR LESS 45NM SWITCHED INVERTER SCHEME (SIS) ANALOG T...VLSICS Design
This work presents three different approaches which eliminates the resistor ladder completely and hence
reduce the power demand drastically of a Analog to Digital Converter. The first approach is Switched
Inverter Scheme (SIS) ADC; The test result obtained for it on 45nm technology indicates an offset error of
0.014 LSB. The full scale error is of -0.112LSB. The gain error is of 0.07 LSB, actual full scale range of
0.49V, worst case DNL & INL each of -0.3V. The power dissipation for the SIS ADC is 207.987 μwatts;
Power delay product (PDP) is 415.9 fWs, and the area is 1.89μm2. The second and third approaches are
clocked SIS ADC and Sleep transistor SIS ADC. Both of them show significant improvement in power
dissipation as 57.5% & 71% respectively. Whereas PDP is 229.7 fWs and area is 0.05 μm2 for Clocked SIS
ADC and 107.3 fWs & 1.94 μm2 for Sleep transistor SIS ADC.
Vlsics040303LOW POWER DUAL EDGE - TRIGGERED STATIC D FLIP-FLOPVLSICS Design
This paper enumerates new architecture of low power dual-edge triggered Flip-Flop (DETFF) designed at
180nm CMOS technology. In DETFF same data throughput can be achieved with half of the clock
frequency as compared to single edge triggered Flip-Flop (SETFF). In this paper conventional and
proposed DETFF are presented and compared at same simulation conditions. The post layout experimental
results comparison shows that the average power dissipation is improved by 48.17%, 41.29% and 36.84%
when compared with SCDFF, DEPFF and SEDNIFF respectively and improvement in PDP is 42.44%,
33.88% and 24.69% as compared to SCDFF, DEPFF and SEDNIFF respectively. Therefore the proposed
DETFF design is suitable for low power and small area applications
A RAIL-TO-RAIL HIGH SPEED CLASS-AB CMOS BUFFER WITH LOW POWER AND ENHANCED SL...VLSICS Design
A rail-to-rail class-AB CMOS buffer is proposed in this paper to drive large capacitive loads. A new
technique is used to reduce the leakage power of class-AB CMOS buffer circuits without affecting dynamic
power dissipation .The name of applied technique is LECTOR, which gives the high speed buffer with the
reduced low power dissipation (1.05%) and reduced area (2.8%). The proposed buffer is simulated at
45nm CMOS technology and the circuit is operated at 3V supply with cadence software. This analog circuit
is performed with extremely low leakage current as well as high current driving capability for the large
input voltages. The proposed paper is achieved very high speed with very low propagation delay range
i.e.(292×10-12). So the delay of the circuit is reduced to 10%. The settling time of this circuit is reduced by
24% (in ns) at 3V square wave input. The measured quiescent current is 41μA
FGMOS BASED LOW-VOLTAGE LOW-POWER HIGH OUTPUT IMPEDANCE REGULATED CASCODE CUR...VLSICS Design
Floating Gate MOS (FGMOS) transistors can be very well implemented in lieu of conventional MOSFET
for design of a low-voltage, low-power current mirror. Incredible features of flexibility, controllability and
tunability of FGMOS yields better results with respect to power, supply voltage and output swing. This
paper presents a new current mirror designed with FGMOS which exhibit high output impedance, higher
current range, very low power dissipation and higher matching accuracy. It achieves current range of up to
1500 µA, high output impedance of 1.125 TΩ, bandwidth of 4.1 MHz and dissipates power as low as 10.56
µW. The proposed design has been simulated using Cadence Design Environment in 180 nm CMOS
process technology with +1.0 Volt single power supply
DESIGN OF A PROGRAMMABLE LOW POWER LOW DROP-OUT REGULATORVLSICS Design
A low power programmable low drop-out regulator capable of providing 1V output has been proposed. The
regulator requires a supply voltage of 1.2V and works in the temperature range of -40 to 125 °C in nominal
corner (i.e, normal doping for PMOS and NMOS Field Effect Transistors), yielding a load regulation of
3%. The output voltage level is controlled externally by means of 2 1-bit control signals. The circuit
provides a DC gain of 30 dB and a maximum DC Power Supply Rejection Ratio of -35 dB and a worst case
PSRR of -20 dB. Power dissipation in the load is nearly 100 μW
Multisim design and simulation of 2.2 g hz lna for wireless communicationVLSICS Design
This paper presents the work done on the design and simulation of a high frequency low noise amplifier for
wireless communication. The purpose of the amplifier is to amplify the received RF path of a wireless
network. With high gain, high sensitivity and low noise using Bipolar Junction transistor (BJT). The design
methodology requires analysis of the transistor for stability, proper matching, network selection and
fabrication. The BJT transistor was chosen for the design of the LNA due to its low noise and good gain at
high frequency. These properties were confirmed using some measurement techniques including Network
Analyzer, frequency analyzer Probe and Oscilloscope for the simulation and practical testing of the
amplifier to verify the performance of the designed High frequency Low noise amplifier. The design goals
of noise figure of 0.52dB-0.7dB and bias conditions are Vcc = 3.5 V and Icc= 55 mA to produce 16.8 dB
gain across the 0.4–2.2GHz band.
Design of low power cmos logic circuits using gate diffusion input (gdi) tech...VLSICS Design
The Gate diffusion input (GDI) is a novel technique
for low power digital circuit design. This techniq
ue
reduces the power dissipation, propagation delay, a
rea of digital circuits and it maintains low comple
xity
of logic design. In this paper, the 4×1 Multiplexer
, 8×3 Encoder, BCD Counter and Mealy State Machine
were implemented by using Pass Transistors (PT), Tr
ansmission Gate (TG) and Gate Diffusion Input (GDI)
technique and then they were compared with each oth
er for power dissipation. The Multiplexers and
Encoders are combinational circuits and Counters an
d mealy machines are sequential circuits both of th
em
are very important digital systems so power optimiz
ation should be done to those digital circuits. The
whole processes for development of digital circuits
and simulation was done by using the mentor graphi
cs
backend tool. This method can also be extended to t
he processors and other high level designs for
optimization of power dissipation, area and delay i
n order to increase the circuit efficiency.
Evolution of Structure of Some Binary Group-Based N-Bit Compartor, N-To-2N De...VLSICS Design
Reversible logic has attracted substantial interest due to its low power consumption which is the main
concern of low power VLSI systems. In this paper, a novel 4x4 reversible gate called inventive gate has
been introduced and using this gate 1-bit, 2-bit, 8-bit, 32-bit and n-bit group-based reversible comparator
have been constructed with low value of reversible parameters. The MOS transistor realizations of 1-bit, 2-
bit, and 8-bit of reversible comparator are also presented and finding power, delay and power delay
product (PDP) with appropriate aspect ratio W/L. Novel inventive gate has the ability to use as an n-to-2n
decoder. Different novel reversible circuit design style is compared with the existing ones. The relative
results shows that the novel reversible gate wide utility, group-based reversible comparator outperforms
the present style in terms of number of gates, garbage outputs and constant input.
International Journal of Engineering Research and Applications (IJERA) is a team of researchers not publication services or private publications running the journals for monetary benefits, we are association of scientists and academia who focus only on supporting authors who want to publish their work. The articles published in our journal can be accessed online, all the articles will be archived for real time access.
Our journal system primarily aims to bring out the research talent and the works done by sciaentists, academia, engineers, practitioners, scholars, post graduate students of engineering and science. This journal aims to cover the scientific research in a broader sense and not publishing a niche area of research facilitating researchers from various verticals to publish their papers. It is also aimed to provide a platform for the researchers to publish in a shorter of time, enabling them to continue further All articles published are freely available to scientific researchers in the Government agencies,educators and the general public. We are taking serious efforts to promote our journal across the globe in various ways, we are sure that our journal will act as a scientific platform for all researchers to publish their works online.
Power Comparison of CMOS and Adiabatic Full Adder Circuits VLSICS Design
Full adders are important components in applications such as digital signal processors (DSP) architectures and microprocessors. Apart from the basic addition adders also used in performing useful operations such as subtraction, multiplication, division, address calculation, etc. In most of these systems the adder lies in the critical path that determines the overall performance of the system. In this paper conventional complementary metal oxide semiconductor (CMOS) and adiabatic adder circuits are analyzed in terms of power and transistor count using 0.18UM technology.
This paper deals with the design of filters and THD analysis of a low - frequency ac (20Hz) transmission system. The LFAC system is interfaced with the 50Hz main power grid with a cycloconverter. The wind power is collected in dc form,and is connected to the L FAC transmission line with a twelve pulse inverter. The waveforms at the sending end and receiving end of the transmission line are plotted.THD analysis of LFAC system is carried out. The circuit model of LFAC system is simulated in MATLAB/SIMULINK.
AN OPERATIONAL AMPLIFIER WITH RECYCLING FOLDED CASCODE TOPOLOGY AND ADAPTIVE ...VLSICS Design
This paper presents a highly adaptive operational amplifier with high gain, high bandwidth, high speed and low power consumption. By adopting the recycling folded cascode topology along with an adaptivebiasing circuit, this design achieves high performance in terms of gain-bandwidth product (GBW) and slew rate (SR). This single stage op-amp has been designed in 0.18µm technology with a power supply of 1.8V and a 5pF load. The simulation results show that the amplifier achieved a GBW of 335.5MHz, Unity Gain Bandwidth of 247.1MHz and a slew rate of 92.8V/µs.
Hysteresis SVM for Coupled Inductor Z Source Diode Clamped 3-Level Inverter B...IAES-IJPEDS
Due to its advantages such as it can defeat problems such as leakage current
and insertion of DC in the grid and provides low stress on power devices,
Diode-clamped three-level inverter (DCTLI) is habitually used in
transformerless photovoltaic (PV) connected to grid network. But it still has
a problem of shoot-through which dwells in its legs, so its operation not
reliable. Z source network is employed to permit operation without shoot
through risk and improve its reliability. Coupled inductors are replaced the
line transformers in to attain lower cost, reduced size, and improved its
reliability and efficiency. Coupled inductor which avoids leakage current
problem and losses. It employs coupled inductor z source diode clamped
three level inverter (CI-Z-DC-TLI) to boost the voltage and further progress
the consistency of the proposed system by avoiding the shoot through the
problem. The proposed system assures that common-mode voltage
and shoot-through risk is avoided. Moreover, controlling DC-TLI with
Hysteresis SVM algorithm which improves output voltage and current
control. Simulation and experimental results of this proposed system were
analyzed using MATLAB environment and FPGA hardware.
Transformerless Topology for Grid-Conected Inverters With Unipolar PWM ControlIJERA Editor
Most of the PV systems are designed with transformer for safety purpose with galvanic isolation. However, the transformer is big, heavy and expensive. Also, it reduces the overall frequency of the conversion stage. Generally PV inverter with transformer is having good efficiency. To overcome these problems, transformer less PV system is introduced. It is smaller, lighter, cheaper and higher in efficiency. However, dangerous leakage current will flow between PV array and the grid due to the stray capacitance. There are different types of configurations available for transformer less inverters like H5, H6, HERIC, and Dual paralleled buck inverter. But each configuration is suffering from its own disadvantages like high conduction losses, shoot-through issues of switches, dead-time requirements at zero crossing instants of grid voltage to avoid grid shoot-through faults and MOSFET reverse recovery issues. The main objective of the proposed transformer less inverter is to address two key issues: One key issue for a transformer less inverter is that it is necessary to achieve high efficiency compared to other existing inverter topologies. Another key issue is that the inverter configuration should not have any shoot-through issues for higher reliability.
Design of 5.1 GHz ultra-low power and wide tuning range hybrid oscillatorIJECEIAES
The objective of the proposed work is to demonstrate the use of a hybrid approach for the design of a voltage-controlled oscillator (VCO) which can lead to higher performance. The performance is improved in terms of the tuning range, frequency of oscillation, voltage swing, and power consumption. The proposed hybrid VCO is designed using an active load common source amplifier and current starved inverter that are cascaded alternatively to achieve low power consumption. The proposed VCO achieves a measured phase noise of -74 dBc/Hz and a figure of merit (FOM) of -152.6 dBc/Hz at a 1 MHz offset when running at 5.1 GHz frequency. The hybrid current starved-current starved VCO (CS-CS VCO) consumes a power of 289 µW using a 1.8 V supply and attains a wide tuning range of 96.98%. Hybrid VCO is designed using 0.09 µm complementary metal– oxide–semiconductor (CMOS) technology. To justify the robustness, reliability, and scalability of the circuit different corner analysis is performed through 500 runs of Monte-Carlo simulation.
Dual-Level Adaptive Supply Voltage System with Bandgap Reference MPR for Vari...IJERA Editor
Nowadays VLSI circuits have become much advanced by overcoming many challenges such as extra power
consumption, but circuit aging along with process variations are still challenging the advancements in power
efficient VLSI circuits. The aim of this dissertation is to propose the new adaptive technique to efficiently
compensate the fine grained variations by addressing the limitations in existing adaption approach. Adaptive
supply voltage (ASV) is proved to be one among the top most adaptation approaches in tuning of power
performance. Controlling power leakage is the main advantage in using ASV, while delivery overheads along
with voltage generation from conventional ASV systems make their application to mitigate fine-grained
variations demanding. The main aim of this dissertation is to present a dual level ASV system with band gap
reference Miniature programmable regulator (BGRMPR). Reference voltage independent of process and
temperature variations can be achieved because of using band gap reference voltage. Another advantage of
adapting this approach is because less power is consumed by system when compared to dual-level ASV system
with MPR.
Experiments confirmed that Transformerless Inverters (TIs) deliver more reliability and higher energy efficiency. Nonetheless, one of the shortcomings of TIs is the leakage current that occurs between the photovoltaic (PV) string terminals and the ground. Such a drawback is justified by the non-galvanic isolation caused by the transformer being omitted. As such, this study is intended to develop a novel TI inverter topology for solar PV systems. The latter is meant to remove the leakage current and enhance the operating system of the entire PV conversion as well. Added to its null zero-crossing distortion and capability regarding energy efficiency, the developed TI, being validated by simulation and experiment, eradicated the leakage current.
An inclination towards renewable energy resources has been increased due to the requirement of clean environment and to satisfy the increasing power demand for the long run. A grid connected system requires the availability of a transformer in its power conversion stages that provides galvanic isolation between the grid and the power system. But inclusion of transformer results in making the system bulky and more expensive. In this paper different transformer-less PV inverter topologies are analyzed by comparing their efficiency, leakage current and THD of load current using MATLAB/Simulink environment. In order to achieve maximum power, maximum power point tracking (P&O algorithm) is used. From the simulation results, modified HB-ZVR is found to have minimum leakage current and constant common mode voltage with higher efficiency. Also, the hardware results are obtained for modified HB-ZVR topology.
Analysis and Modeling of Transformerless Photovoltaic Inverter SystemsIJMER
International Journal of Modern Engineering Research (IJMER) is Peer reviewed, online Journal. It serves as an international archival forum of scholarly research related to engineering and science education.
A low power cmos analog circuit design for acquiring multichannel eeg signalsVLSICS Design
EEG signals are the signatures of neural activities and are captured by multiple-electrodes and the signals are recorded from pairs of electrodes. To acquire these multichannel signals a low power CMOS circuit was designed and implemented. The design operates in weak inversion region employing sub threshold
source coupled logic. A 16 channel differential multiplexer is designed by utilizing a transmission gate with
dynamic threshold logic and a 4 to 16 decoder is used to select the individual channels. The ON and OFF
resistance of the transmission gate obtained is 27 ohms and 10 M ohms respectively. The power dissipation
achieved is around 337nW for a dynamic range of 1μV to 0.4 V.
DESIGN & ANALYSIS OF A CHARGE RE-CYCLE BASED NOVEL LPHS ADIABATIC LOGIC CIRCU...VLSICS Design
This paper focuses on principles of adiabatic logic, its classification and comparison of various adiabatic logic designs. An attempt has been made in this paper to modify 2PASCL (Two Phase Adiabatic Static CMOS Logic) adiabatic logic circuit to minimize delay of the different 2PASCL circuit designs. This modifications in the circuits leads to improvement of Power Delay Product (PDP) which is one of the figure of merit to optimize the circuit with factors like power dissipation and delay of the circuit. This paper investigates the design approaches of low power adiabatic gates in terms of energy dissipation and uses of Simple PN diode instead of MOS diode which reduces the effect of Capacitances at high transition and power clock frequency. A computer simulation using SPECTRE from Cadence is carried out on different adiabatic circuits, such as Inverter, NAND, NOR, XOR and 2:1 MUX.
International Journal of Engineering Research and Applications (IJERA) is an open access online peer reviewed international journal that publishes research and review articles in the fields of Computer Science, Neural Networks, Electrical Engineering, Software Engineering, Information Technology, Mechanical Engineering, Chemical Engineering, Plastic Engineering, Food Technology, Textile Engineering, Nano Technology & science, Power Electronics, Electronics & Communication Engineering, Computational mathematics, Image processing, Civil Engineering, Structural Engineering, Environmental Engineering, VLSI Testing & Low Power VLSI Design etc.
Accelerate your Kubernetes clusters with Varnish CachingThijs Feryn
A presentation about the usage and availability of Varnish on Kubernetes. This talk explores the capabilities of Varnish caching and shows how to use the Varnish Helm chart to deploy it to Kubernetes.
This presentation was delivered at K8SUG Singapore. See https://feryn.eu/presentations/accelerate-your-kubernetes-clusters-with-varnish-caching-k8sug-singapore-28-2024 for more details.
Generative AI Deep Dive: Advancing from Proof of Concept to ProductionAggregage
Join Maher Hanafi, VP of Engineering at Betterworks, in this new session where he'll share a practical framework to transform Gen AI prototypes into impactful products! He'll delve into the complexities of data collection and management, model selection and optimization, and ensuring security, scalability, and responsible use.
Transcript: Selling digital books in 2024: Insights from industry leaders - T...BookNet Canada
The publishing industry has been selling digital audiobooks and ebooks for over a decade and has found its groove. What’s changed? What has stayed the same? Where do we go from here? Join a group of leading sales peers from across the industry for a conversation about the lessons learned since the popularization of digital books, best practices, digital book supply chain management, and more.
Link to video recording: https://bnctechforum.ca/sessions/selling-digital-books-in-2024-insights-from-industry-leaders/
Presented by BookNet Canada on May 28, 2024, with support from the Department of Canadian Heritage.
Smart TV Buyer Insights Survey 2024 by 91mobiles.pdf91mobiles
91mobiles recently conducted a Smart TV Buyer Insights Survey in which we asked over 3,000 respondents about the TV they own, aspects they look at on a new TV, and their TV buying preferences.
PHP Frameworks: I want to break free (IPC Berlin 2024)Ralf Eggert
In this presentation, we examine the challenges and limitations of relying too heavily on PHP frameworks in web development. We discuss the history of PHP and its frameworks to understand how this dependence has evolved. The focus will be on providing concrete tips and strategies to reduce reliance on these frameworks, based on real-world examples and practical considerations. The goal is to equip developers with the skills and knowledge to create more flexible and future-proof web applications. We'll explore the importance of maintaining autonomy in a rapidly changing tech landscape and how to make informed decisions in PHP development.
This talk is aimed at encouraging a more independent approach to using PHP frameworks, moving towards a more flexible and future-proof approach to PHP development.
Observability Concepts EVERY Developer Should Know -- DeveloperWeek Europe.pdfPaige Cruz
Monitoring and observability aren’t traditionally found in software curriculums and many of us cobble this knowledge together from whatever vendor or ecosystem we were first introduced to and whatever is a part of your current company’s observability stack.
While the dev and ops silo continues to crumble….many organizations still relegate monitoring & observability as the purview of ops, infra and SRE teams. This is a mistake - achieving a highly observable system requires collaboration up and down the stack.
I, a former op, would like to extend an invitation to all application developers to join the observability party will share these foundational concepts to build on:
Pushing the limits of ePRTC: 100ns holdover for 100 daysAdtran
At WSTS 2024, Alon Stern explored the topic of parametric holdover and explained how recent research findings can be implemented in real-world PNT networks to achieve 100 nanoseconds of accuracy for up to 100 days.
Welcome to the first live UiPath Community Day Dubai! Join us for this unique occasion to meet our local and global UiPath Community and leaders. You will get a full view of the MEA region's automation landscape and the AI Powered automation technology capabilities of UiPath. Also, hosted by our local partners Marc Ellis, you will enjoy a half-day packed with industry insights and automation peers networking.
📕 Curious on our agenda? Wait no more!
10:00 Welcome note - UiPath Community in Dubai
Lovely Sinha, UiPath Community Chapter Leader, UiPath MVPx3, Hyper-automation Consultant, First Abu Dhabi Bank
10:20 A UiPath cross-region MEA overview
Ashraf El Zarka, VP and Managing Director MEA, UiPath
10:35: Customer Success Journey
Deepthi Deepak, Head of Intelligent Automation CoE, First Abu Dhabi Bank
11:15 The UiPath approach to GenAI with our three principles: improve accuracy, supercharge productivity, and automate more
Boris Krumrey, Global VP, Automation Innovation, UiPath
12:15 To discover how Marc Ellis leverages tech-driven solutions in recruitment and managed services.
Brendan Lingam, Director of Sales and Business Development, Marc Ellis
Securing your Kubernetes cluster_ a step-by-step guide to success !KatiaHIMEUR1
Today, after several years of existence, an extremely active community and an ultra-dynamic ecosystem, Kubernetes has established itself as the de facto standard in container orchestration. Thanks to a wide range of managed services, it has never been so easy to set up a ready-to-use Kubernetes cluster.
However, this ease of use means that the subject of security in Kubernetes is often left for later, or even neglected. This exposes companies to significant risks.
In this talk, I'll show you step-by-step how to secure your Kubernetes cluster for greater peace of mind and reliability.
Elevating Tactical DDD Patterns Through Object CalisthenicsDorra BARTAGUIZ
After immersing yourself in the blue book and its red counterpart, attending DDD-focused conferences, and applying tactical patterns, you're left with a crucial question: How do I ensure my design is effective? Tactical patterns within Domain-Driven Design (DDD) serve as guiding principles for creating clear and manageable domain models. However, achieving success with these patterns requires additional guidance. Interestingly, we've observed that a set of constraints initially designed for training purposes remarkably aligns with effective pattern implementation, offering a more ‘mechanical’ approach. Let's explore together how Object Calisthenics can elevate the design of your tactical DDD patterns, offering concrete help for those venturing into DDD for the first time!
zkStudyClub - Reef: Fast Succinct Non-Interactive Zero-Knowledge Regex ProofsAlex Pruden
This paper presents Reef, a system for generating publicly verifiable succinct non-interactive zero-knowledge proofs that a committed document matches or does not match a regular expression. We describe applications such as proving the strength of passwords, the provenance of email despite redactions, the validity of oblivious DNS queries, and the existence of mutations in DNA. Reef supports the Perl Compatible Regular Expression syntax, including wildcards, alternation, ranges, capture groups, Kleene star, negations, and lookarounds. Reef introduces a new type of automata, Skipping Alternating Finite Automata (SAFA), that skips irrelevant parts of a document when producing proofs without undermining soundness, and instantiates SAFA with a lookup argument. Our experimental evaluation confirms that Reef can generate proofs for documents with 32M characters; the proofs are small and cheap to verify (under a second).
Paper: https://eprint.iacr.org/2023/1886
Epistemic Interaction - tuning interfaces to provide information for AI supportAlan Dix
Paper presented at SYNERGY workshop at AVI 2024, Genoa, Italy. 3rd June 2024
https://alandix.com/academic/papers/synergy2024-epistemic/
As machine learning integrates deeper into human-computer interactions, the concept of epistemic interaction emerges, aiming to refine these interactions to enhance system adaptability. This approach encourages minor, intentional adjustments in user behaviour to enrich the data available for system learning. This paper introduces epistemic interaction within the context of human-system communication, illustrating how deliberate interaction design can improve system understanding and adaptation. Through concrete examples, we demonstrate the potential of epistemic interaction to significantly advance human-computer interaction by leveraging intuitive human communication strategies to inform system design and functionality, offering a novel pathway for enriching user-system engagements.
A tale of scale & speed: How the US Navy is enabling software delivery from l...sonjaschweigert1
Rapid and secure feature delivery is a goal across every application team and every branch of the DoD. The Navy’s DevSecOps platform, Party Barge, has achieved:
- Reduction in onboarding time from 5 weeks to 1 day
- Improved developer experience and productivity through actionable findings and reduction of false positives
- Maintenance of superior security standards and inherent policy enforcement with Authorization to Operate (ATO)
Development teams can ship efficiently and ensure applications are cyber ready for Navy Authorizing Officials (AOs). In this webinar, Sigma Defense and Anchore will give attendees a look behind the scenes and demo secure pipeline automation and security artifacts that speed up application ATO and time to production.
We will cover:
- How to remove silos in DevSecOps
- How to build efficient development pipeline roles and component templates
- How to deliver security artifacts that matter for ATO’s (SBOMs, vulnerability reports, and policy evidence)
- How to streamline operations with automated policy checks on container images
GraphRAG is All You need? LLM & Knowledge GraphGuy Korland
Guy Korland, CEO and Co-founder of FalkorDB, will review two articles on the integration of language models with knowledge graphs.
1. Unifying Large Language Models and Knowledge Graphs: A Roadmap.
https://arxiv.org/abs/2306.08302
2. Microsoft Research's GraphRAG paper and a review paper on various uses of knowledge graphs:
https://www.microsoft.com/en-us/research/blog/graphrag-unlocking-llm-discovery-on-narrative-private-data/
Dev Dives: Train smarter, not harder – active learning and UiPath LLMs for do...UiPathCommunity
💥 Speed, accuracy, and scaling – discover the superpowers of GenAI in action with UiPath Document Understanding and Communications Mining™:
See how to accelerate model training and optimize model performance with active learning
Learn about the latest enhancements to out-of-the-box document processing – with little to no training required
Get an exclusive demo of the new family of UiPath LLMs – GenAI models specialized for processing different types of documents and messages
This is a hands-on session specifically designed for automation developers and AI enthusiasts seeking to enhance their knowledge in leveraging the latest intelligent document processing capabilities offered by UiPath.
Speakers:
👨🏫 Andras Palfi, Senior Product Manager, UiPath
👩🏫 Lenka Dulovicova, Product Program Manager, UiPath
Dev Dives: Train smarter, not harder – active learning and UiPath LLMs for do...
PERFORMANCE ANALYSIS OF MODIFIED QSERL CIRCUIT
1. International Journal of VLSI design & Communication Systems (VLSICS) Vol.4, No.4, August 2013
DOI : 10.5121/vlsic.2013.4403 19
PERFORMANCE ANALYSIS OF MODIFIED QSERL
CIRCUIT
Shipra Upadhyay *1
, R.A. Mishra 2
and R. K. Nagaria 3
1
Department of Electronics & Communication Engineering, Motilal Nehru
National Institute of Technology Allahabad -211004, India
*shipraupadhyay2@gmail.com
2
Department of Electronics & Communication Engineering, Motilal Nehru National
Institute of Technology, Allahabad -211004, India
ramishra@mnnit.ac.in
3
Department of Electronics & Communication Engineering, Motilal Nehru National
Institute of Technology, Allahabad -211004, India
rkn@mnnit.ac.in
ABSTRACT
This work is based on a new approach for minimizing energy consumption in quasi static energy recovery
logic (QSERL) circuit which involves optimization by removing the non adiabatic losses completely.
Energy recovering circuitry based on adiabatic principles is a promising technique leading towards low-
power high performance circuit design. The efficiency of such circuits may be increased by reducing the
adiabatic and non-adiabatic losses drawn by them during the charging and recovery operations. In this
paper, performance of the proposed logic style is analyzed and compared with CMOS in their
representative inverters, gates, flip flops and adder circuits. All the circuits were simulated by VIRTUOSO
SPECTRE simulator of Cadence in 0.18µm technology. In our proposed inverter the energy efficiency has
been improved to almost 30% & 20% upto 20MHz and 20fF external load capacitance in comparison to
CMOS & QSERL circuits respectively. Our proposed circuit provides energy efficient performance up to
100 MHz and thus it has proven to be used in high-performance VLSI circuitry.
KEYWORDS
Adiabatic logic circuits, Energy, Diode, Power clock.
1. INTRODUCTION
With the growing requirement of portable communication many research have been done to
reduce energy dissipation [1]-[4], among them adiabatic logic technique [5] is very promising. In
adiabatic circuits energy dissipation occurs due to adiabatic and non adiabatic losses. If we lower
the rate of charging, then lesser amount of power is drawn from the source and lesser will be
adiabatic losses. Non adiabatic losses occur due to the voltage drop of terminals of a transistor (as
a switch)/diode when it is on. Most of the adiabatic circuits have these non adiabatic losses due to
the voltage drop across the diodes or incomplete energy recovery. The basic idea for reducing
adiabatic losses is that; clock transient time T is kept much larger than intrinsic time constant RCL
of the device [6]. Non adiabatic losses are minimized by recovering the energy stored in load
capacitances [7]. The energy in charging the load capacitances is recovered during discharging
and stored for reuse. In adiabatic logic circuits time varying voltage supply is used so that the
nodal capacitance are charged or discharged at a constant current which makes voltage drop
2. International Journal of VLSI design & Communication Systems (VLSICS) Vol.4, No.4, August 2013
20
almost negligible, whereas in CMOS logic circuits we use constant DC voltage source. The word
‘adiabatic’ is used in a reversible thermodynamic process [8] where a transformation is done so
that no gain or loss of heat or energy occurs. By making the transformation process very slow the
heat or energy loss can be made almost zero ideally.
In recent years many adiabatic logic structures have been proposed which work on the same
theory but have different circuit structures and complexity. The quasi-static energy recovery logic
(QSERL) circuit [9] attempts to reduce the drawbacks of the previous energy recovery logic
(ERL) families due to its static logic resemblance circuit structure, reduced switching activity and
number of power clocks but it have drawback of in-robustness and output floating due to the
alternate hold phases. Complementary energy path adiabatic logic (CEPAL) provides
improvement to the QSERL circuit because it does not need feedback keeper to remove floating
output which in turn improves area and power overhead [10]. Also its throughput is better (twice)
than QSERL. But due to the extra MOSFET diodes in charging and discharging path a bit larger
power dissipation than QSERL circuits occurs.
Due to these challenges with reported adiabatic logic circuits [11-19] we propose modified quasi
static energy recovery logic (MQSERL) circuit. MQSERL inherits all the advantages of recently
reported QSERL circuits with additional improvement in power saving by reducing the non
adiabatic losses as well as adiabatic losses. We have designed and simulated various MQSERL
based logic circuits and their performances have been evaluated and compared with some
reported adiabatic circuits and conventional CMOS circuits.
This paper contains four sections. Section 1 deals the introduction part. Section 2 describes the
proposed energy recovery logic (MQSERL) circuit and it’s working. In section 3 we have
simulation results and discussion. The section 4 summarizes the conclusion.
2. PROPOSED ENERGY RECOVERY LOGIC CIRCUIT
2.1. Circuit description
The circuit of modified quasi static energy recovery logic (MQSERL) is shown in Fig. 1(a). It is
composed of with two complementary sinusoidal power clocks (VΦ and V φ ), a charging pMOS
transistor (P1) whose gate is connected by the power clock V φ , and a P-network in charging path,
and a discharging nMOS transistor (N1) whose gate is connected by the power clock VΦ , and a
N-network in discharging path. The power clock (VΦ) is in phase whereas the other clock (V φ ) is
180 degree out of phase. The sinusoidal clock charges/discharges the load capacitance
comparatively slowly than the triangular or trapezoidal power clocks. We have discussed in
previous section that we can enhance power efficiency of adiabatic logic circuits by ensuring that
how slowly the nodal capacitances are charged or discharged thus power dissipation is minimized
by using these sinusoidal clocks. The peak to peak voltage of power clocks VΦ and V φ is 1.8 V.
The transistor (P1) in the pull up network and transistors (N1) in the pull down network are used
instead of the diode (which was used in QSERL circuit) for reducing the non adiabatic losses.
Power clock (VΦ) controls the ON and OFF time of transistor (N1) and (V φ ) controls the ON and
OFF time of transistors (P1). The noticeable source of power dissipation in QSERL circuits was
due to the MOSFET diode’s threshold voltage drop (which is non adiabatic loss) whereas in the
proposed MQSERL circuit, the main source of power loss is due to the ON resistance of channels
of MOSFET transistors P1 & N1 [12].
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The losses due to the ON resistance of P1 & N1 are significantly lower than the losses due to the
threshold voltage drop through diodes and overall losses can further be lowered by lowering the
charging speed. Thus by using transistors (P1 & N1), power dissipation is much reduced in
comparison to the diode based circuits. However we can not remove the power dissipation
completely because of the non reversible nature of the proposed circuit.
2.2. Circuit operation
The operation of the circuit is divided into two stages based on the supply clock phases,
evaluation and hold. In evaluation phase VΦ gradually increases from low to high voltage while
V φ gradually decreases from high to low voltage, whereas in hold phase VΦ gradually decreases
from high to low and Vφ increases from low to high voltage as shown in Fig. 1(b).
Figure 1. Proposed MQSERL topology (a) circuit diagram, (b) simulation waveforms of 4
inverter chain
Figure 1. Proposed MQSERL topology (a) circuit diagram, (b) simulation waveforms of 4 inverter chain
In evaluation phase, if output node (Vout) is at LOW logic and the P tree is turned ON, load
capacitance (CL) is charged through pMOS transistor (P1) producing HIGH logic at the output.
Whereas if output node (Vout) is at HIGH logic and N tree turns ON, discharging and recycling to
the power clock (V φ ) via nMOS transistor (N1) occurs, producing LOW output logic. In hold
phase, VΦ decreases from high to low and Vφ increases from low to high and when they reaches
below the threshold voltage of P1 & N1 both turns OFF thus no transitions shown at the output.
Vφ
φV
(a)
(b)
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Dynamic switching is reduced because of the hold phase, which will again reduce the energy
dissipation.
The simulated waveforms of proposed MQSERL 4 inverter chain in Fig 1(b) shows that the
output signals of cascaded logics not affecting the performance in MQSERL inverter circuit.
3. SIMULATION RESULTS AND DISCUSSION
Adiabatic circuits cannot be designed by using conventional method [20] therefore the accurate
design of proposed MQSERL gates will assist the better performance of the larger circuits [21,
22]. In the remaining paper several MQSERL based circuits have been presented.
We have simulated all the circuits with width to length ratio of the nMOS transistor as 240
nm/180 nm, pMOS as 540 nm /180nm respectively. The supply waveform is sinusoidal; and the
supply frequency is 200 MHz. Input is a square voltage pulse with a frequency of 50 MHz. The
peak supply voltage is fixed at 1.8 V, which is enough to drive the transistors with reasonable
logic values.
3.1. Proposed energy recovery logic inverter
The inverter circuit (obtained by replacing P-network and N-network with pMOS and nMOS
respectively in Fig. 1(a)) is simulated using VIRTUOSO SPECTRE simulator of cadence. The
energy dissipation is calculated by subtracting the energy pumped back from the energy drawn.
3.1.1. Energy efficiency with frequency
Figure 2. Simulation results of the performance comparison of inverters with frequency
To check the performance of proposed inverter with frequency, input and supply frequencies are
varied simultaneously (keeping supply frequency four times the input frequency for better
performance) from 1 MHz to 100 MHz and load capacitance is set to 20fF as shown in Fig. 2.
With the frequency, energy dissipation of QSERL & CMOS inverters decreases whereas
proposed MQSERL inverter has lesser energy dissipation in comparison to these two inverters.
After 50 MHz QSERL inverter fails to give correct output logics so it has lesser energy
dissipation than proposed inverter after this frequency. The drawback is that a continuous
decrease in percentage energy saving of proposed over other two inverters with frequency is
observed.
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3.1.2. Effect of variation of load capacitance
To check the performance with load capacitance variation we added extra capacitive load at the
output node one by one from 10fF to 100fF as shown in Fig. 3. Clock & data rate kept fixed at
160 MHz & 40 MHz respectively.
When we increase the load capacitance, energy dissipation of all three inverters increases
however the proposed inverter has good energy efficiency than CMOS at each point whereas
QSERL output logic becomes incorrect after 10fF and thus have lower energy dissipation than
proposed circuit.
Figure 3. Simulation results of the performance comparison of inverters with load capacitance
3.2. Proposed energy recovery logic NOR Gate
(a)
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(b)
Figure 4. Proposed MQSERL NOR gate (a) circuit diagram, (b) simulation waveforms
The proposed MQSERL NOR gate is shown in Fig. 4(a). This circuit is made from two pMOS
transistors (M1 and M2) and two nMOS transistors (M3 and M4). A charging pMOS transistor P1
& discharging nMOS transistor N1 is also present whose gate is tied with sinusoidal power clocks
(V φ and VΦ respectively). Input A is connected with the gates of M1 and M4 and gates of M2
and M3 are connected with another input B. The simulated timing waveforms having bottom two
graph as input strings A= ‘100100100100100100100100100100’, B=
‘110110110110110110110110110110’and the top two graphs as power clocks & output=
‘001001001001001001001001001001’ respectively are shown in Fig 4(b).
3.3. Proposed energy recovery logic NAND Gate
(a)
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(b)
Figure 5. Proposed MQSERL NAND gate (a) circuit diagram, (b) simulation waveforms
The proposed MQSERL NAND gate is shown in Fig. 5(a). The circuit is made from two pMOS
transistors (M1 and M2) tied in parallel and two nMOS transistors (M3and M4) which are
connected in series. Output load capacitance is charged/discharged through charging/discharging
pMOS/nMOS transistors P1 & N1 whose gate is directly connected with sinusoidal power clock
(V φ and VΦ respectively). M1 and M3 gates are connected together with an input A and M2 and
M4 gates are connected with another input B.
The simulated timing waveforms having bottom two graph as input strings A=
‘100100100100100100100100100100’, B= ‘110110110110110110110110110110’ and the top
two graphs as power clocks & output= ‘011011011011011011011011011011’
respectively are shown in Fig 5(b).
3.4. Proposed energy recovery logic XOR Gate
(a)
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(b)
Figure 6. Proposed MQSERL XOR gate (a) circuit diagram, (b) simulation waveforms
The proposed MQSERL XOR gate is shown in Fig. 6(a). Its’ circuit is made from a P network
with four pMOS transistors (M1, M2 tied in parallel and M3, M4 connected in parallel) and a N
network with four nMOS transistors (M5 and M7 connected in parallel with M6 and M8). A
charging pMOS transistor P1 and a discharging nMOS transistor N1 is also used which are
controlled by sinusoidal power clocks (V φ and VΦ respectively). M1 & M6 gates are connected
with input A, and M3 & M5 with A . However M2 & M8 gates are connected with input B and
M4 & M7 with B .
Simulated timing waveforms having bottom two graph as input strings A=
‘110110110110110110110110110110’, B= ‘100100100100100100100100100100’and the top
two graphs as power clocks and output= ‘010010010010010010010010010010’ respectively are
shown in Fig 6(b).
3.5. Proposed energy recovery logic 1 bit Full adder
The MQSERL full adder consists of two MQSERL half adders and an OR gate. The block level
diagram of our MQSERL half adder is given in Fig. 7(a). It is made from a XOR gate and one
AND gate.
Simulated timing waveforms having bottom three graphs as input strings
A=‘1000100010001000100010001000100010001000’,B=‘1100110011001100110011001100110
011001100’and Cin= ‘1110111011101110111011101110111011101110’ the top three graphs as
power clocks & outputs, Carry= ‘1100110011001100110011001100110011001100’ and Sum =
‘1010101010101010101010101010101010101010’ respectively are shown in Fig 7(b).
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(a)
Figure 7. Proposed MQSERL Full adder (a) circuit diagram, (b) simulation waveforms
3.6. Proposed energy recovery logic D flip flop
The proposed MQSERL D flip flop is shown in Fig. 8(a), it is made from two MQSERL 3 input
NAND gates and two MQSERL 2 input NAND gates and a MQSERL inverter circuit.
Simulated timing waveforms from the top for power clocks, inputs D=
‘100100100100100100100100100100’ & CLK= ‘110110110110110110110110110110’ outputs
(b)
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Q= ‘100100100100100100100100100100’ & Qbar= ‘001001001001001001001001001001’
respectively are shown in Fig. 8(b).
(a)
(b)
Figure 8. Proposed MQSERL D flip flop (a) circuit diagram, (b) simulation waveforms
The simulated timing waveforms of proposed MQSERL based all the circuits verifies the
functionality of proposed logic style. These circuits are compared with CMOS circuits using
equal switching probability of inputs whereas W/L ratio in proposed MQSERL circuits is same as
given in the starting of this section i.e. for pMOS it is 540nm/180nm and for nMOS it is
240nm/180nm however in CMOS circuits it is same for pMOS and nMOS i.e. 240nm/180nm. It
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is observed from the Table 1 that the proposed MQSERL circuits have almost 36% or greater
energy saving to the conventional CMOS circuits except half adder (25.7% energy saving).
Table 1 Comparison of proposed MQSERL and CMOS circuits at (f Φ , fφ ) =200MHz, fin =50MHz
4. CONCLUSIONS
In this paper we have presented modified quasi static energy recovery logic (MQSERL) family.
Specifically we presented the performance analysis of MQSERL inverter to validate the operating
capability and energy efficiency of proposed circuit with variation in frequency and load
capacitance. The simulation results and comparative performance evaluation revealed that energy
dissipation in the MQSERL logic are considerably lower than the CMOS and QSERL logic. The
proposed MQSERL family outperforms and provides almost 36% of energy saving at 50MHz for
almost all the MQSERL based logic circuits.
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