This document describes the design of a low drop-out voltage regulator using a feed-forward ripple cancellation technique. The technique aims to improve line and load regulation by minimizing fluctuations in the output voltage due to variations in the input supply voltage or load current. An error amplifier with a gain of 76.1dB and phase margin of 73.2 degrees was designed. Simulation results showed that the feed-forward technique improved line regulation from -33dB to -85.1dB and improved load regulation from 46uA to 68uA.

1. Design of Low Drop-Out Voltage Regulator with
Feed-Forward Ripple Cancellation Technique
Niharika S. Vranda Baweja Priya Pandey
M.Tech VLSI(1st
Year ) M.Tech VLSI(1st
Year ) M.Tech VLSI(1st
Year )
VIT University VIT University VIT University
Under The Guidance Of:
Prof. Subhakumar Reddy
VLSI Division
VIT University
Tamil Nadu, India
Abstract—This paper includes the design of low drop out
regulator (LDO) using feed forward ripple cancellation technique
that uses low power and has the capability to reject fluctuations
occurring in the supply voltage (line regulation) and the load
current (load regulation). The required error amplifier for LDO
was designed with a gain of 76.114dB and a phase margin of
73.182deg. By using the feed-forward technique, we obtained line
regulation of -85.1dB better than -33dB without the technique
with a drop-out voltage of 600mV upto load current of 68µA. By
using the ripple cancellation technique, we improved load
regulation from 46µA to 68µA. The proposed LDO was designed
using gpdk90nm technology on Cadence Virtuoso tool.
Keywords—ldo,line regulation,load regulation,feed forward
ripple cancellation
I. INTRODUCTION
There is a great interest in efficient power management ICs.
An important building block in power management is the low
drop-out (LDO) linear regulator which often follows a DC-DC
switching converter. It is used to regulate the supplies ripples to
provide a clean voltage source for the noise-sensitive
analog/RF blocks. Designing a stable LDO for a wide range of
load conditions, while achieving high power-supply rejection
(PSR), low drop-out voltage, and low quiescent current, is the
main target using state-of-the-art CMOS technologies.
Recently, there has been an increasing demand to integrate
the whole power management system into a single system-on-
chip (SoC) solution. Hence, operating frequencies of switching
converters are increasing to allow higher level of integration.
This trend increases the frequency of output ripples and
therefore the subsequent LDO regulator should provide high
PSR up to switching frequencies. Several techniques have been
proposed to achieve this. A low drop-out (LDO) regulator
with a feed-forward ripple cancellation (FFRC) technique is
proposed in this paper.
The FFRC-LDO achieves a high power-supply rejection
(PSR) over a wide frequency range[1]
. Ultra low-power
operation is achieved for the power block by realizing a nano-
power bandgap reference circuit whose total power
consumption including LDO is only just 95nW for
1.2Vsupply. The resistor-less reference circuit with no
external capacitor for LDO stability results in a very compact
design occupying just 0.033 mm2[2]
. The paths for power
supply noise leakage in low drop-out (LDO) voltage
regulators are analyzed, and techniques are discussed to
minimize their effects on the output voltage. An internally
compensated high power supply rejection (PSR) LDO voltage
regulator with adaptive supply noise compensation scheme is
presented[3]
. Effectively overcomes the drawbacks that exist in
the conventional compensation schemes by generating an
internal low-frequency zero[4]
. A bulky external capacitor is
avoided to make the LDO suitable for system-on-chip (SoC)
applications while maintaining the capability to reduce high-
frequency supply noise. The paths of the power supply noise
to the LDO output are analyzed, and a power supply noise
cancellation circuit is developed. The PSR performance is
improved by using a replica circuit that tracks the main supply
noise under process-voltage-temperature variations and all
operating conditions[5]
. Conventional LDOs have poor PSR at
high frequencies (above 300 kHz) especially the ones
implemented using sub-250 nm technologies. The main reasons
for poor PSR are summarized as follows- 1) Finite output
conductance of the pass transistor, 2) Low DC gain ofsub-
250nm technologies which requires complex gain stages to

2. achieve better regulation, and 3) finite bandwidth of the
feedback path.
Researchers have contributed to improve power-supply
rejection techniques. Some of those techniques are- 1) Using
simple RC filtering at the output of the LDO, 2) Cascading two
regulators, and 3) Cascading another transistor with the pMOS
pass transistor along with RC filtering, using special
technologies such as drain-extended FET devices, and/or
charge-pump techniques to bias the gate of one of the
transistors.
II. LOW DROP-OUT VOLTAGE REGULATOR
Fig.1 shows the basic architecture of a voltage regulator.
A low-dropout or LDO regulator is a DC linear voltage
regulator which can regulate the output voltage even when the
supply voltage is very close to the output voltage. The
advantages of a low dropout voltage regulator over other DC
to DC regulators include the absence of switching noise (as no
switching takes place), smaller device size (as neither large
inductors nor transformers are needed), and greater design
simplicity (usually consists of a reference, an amplifier, and a
pass element). A significant disadvantage is that, unlike
switching regulators, linear DC regulators must dissipate
power across the regulation device in order to regulate the
output voltage.
Block diagram of an LDO consists of:
i. Error amplifier
ii. Pass device/ pass transistor
iii. Voltage divider circuit
iv. Reference voltage
Fig 1. Basic LDO architecture
A. Performance parametrics of LDO
a. Dropout Voltage
The Dropout voltage (VDROPOUT) is the input-to-output
voltage difference at which the LDO is no longer able to
regulate against further decreases in the input voltage. In the
dropout region, the pass element acts like a resistor with a
value equal to the drain-to-source on resistance (RDSON). The
dropout voltage, expressed in terms of RDSON and load current,
is
VDROPOUT = ILOAD × RDSON
b. Quiescent and Ground Current
Quiescent current (IQ) is the current required to power the
LDO’s internal circuitry when the external load current is
zero. It includes the operating currents of the band-gap
reference, error amplifier, output voltage divider, and
overcurrent and overtemperature sensing circuits. The amount
of quiescent current is determined by the topology, input
voltage, and temperature.
IQ = IIN @ no load
Ground current (IGND) is the difference between the input and
output currents, and necessarily includes the quiescent current.
A low ground current maximizes the LDO efficiency.
IGND= IIN– IOUT
c. Efficiency
The efficiency of an LDO is determined by the ground
current and input/output voltages:
Efficiency = IOUT/(IOUT + IGND) × VOUT/VIN × 100%
The power dissipation of an LDO is
(VIN – VOUT) × IOUT
d. DC load regulation
Load regulation is a measure of the LDO’s ability to
maintain the specified output voltage under varying load
conditions. Load regulation, shown in Figure 6, is defined
as
Load regulation = ∆VOUT/∆IOUT
e. DC line regulation
Line regulation is a measure of the LDO’s ability to
maintain the specified output voltage with varying input
voltage. Line regulation is defined as
Line regulation = ∆VOUT/∆VIN
f. Power Supply Rejection
PSRR is a measure of how well a circuit suppresses
extraneous signals (noise and ripple) on the power supply
input to keep them from corrupting the output. PSRR is
defined as
PSRR = |20 × log(VEIN/VEOUT)|
where VEIN and VEOUT are the extraneous signals
appearing at the input and output, respectively.

3. III. PROPOSED ARCHITECTURE
In LDO, to design an error amplifier, we have used a
two stage operational amplifier which is capable of
rejecting common mode signal and providing a good
output voltage. We have also used feed forward ripple
cancellation method to eliminate the noise ripple appearing
at the output. The ripple cancellation block include as a
summing amplifier and a feed forward amplifier in which
the feedback path is introduced between the input and the
output intentionally to eliminate the ripple at the output by
giving an out of phase ripple voltage at the NMOS pass
transistor input.
A. Design Of Error Amplifier using Two-Stage Operational
Amplifier
Fig.2 shows the design of LDO using an operational amplifier
as error amplifier.
Fig 2. LDO with two stage operational amplifier as error
amplifier
B. Using feedforward ripple cancellation block
Fig.3 shows the complete LDO architecture along with the
feed forward ripple cancellation block. The feedforward ripple
cancellation technique consists of a summing amplifier and an
error amplifier in addition with the basic error amplifier. The
basic idea behind this technique is to provide the ripple
voltage coming from the supply and its out of phase value to
the pass transistor to the pass device so that the net ripple
appearing at the output is minimized.
Fig 3. LDO architecture using feed forward block
IV. SIMULATION RESULTS
We obtained a gain of 76.113dB and phase margin of 74.6deg
with the error amplifier alone. Fig.4 shows the gain and phase
plot of the error amplifier:
Fig 4. Gain and phase plot of error amplifier
To obtain the load regulation, we varied the load current from
0 to 1mA. Fig.4 shows the plot of the load regulation before
applying ripple cancellation technique and Fig.5 and Fig.6 are
showing load regulation after ripple cancellation technique..
We observed that before application of ripple cancellation, the
load regulation was 46µA while after application of ripple
cancellation, load relation was 68µA.
Fig 5. Load regulation before ripple cancellation technique
Fig 6. Load regulation after ripple cancellation technique
Line regulation is performed to see the change in the output
due to the ripples present in the input supply voltage.
Before application of ripple cancellation method, line
regulation was obtained as -33.435dB.
We obtained line regulation of -85.1dB after applying ripple
cancellation technique. Fig.7 shown the line regulation after
ripple cancellation.

4. Fig 7. Line regulation after ripple cancellation technique
V. DISCUSSION
We designed an LDO using feed forward ripple cancellation
technique. We obtained load regulation of 23µA and PSR
better than -67.0598dB up to 900Hz.
TABLE I. Comparison of LDO parameters with and with and
without ripple cancellation technique
Parameters LDO without
feedforward
technique
LDO with
feedforward
technique
1 Line
regulation(Gain) -33.435dB -85.1dB
2 Load regulation 46µA 68uA
To eliminate input ripples from appearing at the output, a
zero transfer gain is necessary from the input to the output. In
the ideal case (without considering), this is achieved by
implementing a feed-forward path that replicates same input
ripples at the gate of the pass transistor.
VI. CONCLUSION
The design of LDO using Feed-Forward ripple cancellation
technique was proposed in this paper. The FFRC can be
extended to existing LDOs to improve their performance.
Using this technique the line regulation of -67.0598dB was
obtained up to 23µA.
REFERENCES
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Sinencio,"High PSR Low Drop-Out Regulator with Feed-Forward
Ripple Cancellation Technique,"In IEEE Journal of Solid-State Circuits,
vol.45, no.3, pp.565-577, March 2010.
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LDO with high PSR”,IEEE MTT-S,978-1-4673-6096-8/13/$31.00
©2013 IEEE
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Techniques for External Capacitor-Less LDOs With High PSR over
Wide Frequncy Range”IEEE Journal, 978-1-4799-4132-2/14/$31.00
©2014 IEEE
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Low- DropOut Regulator with Wide-Band High-PSR
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[5] Chang-Joon Park, M. Onabajo, and J. Silva-Martinez,”External
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Supply Rejection in the 0.4-4 Mhz Range”IEEE Journal of Solid-State
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