The document describes the design of an encoder-decoder system in Verilog. It includes a 4-to-2 encoder, 2-to-4 decoder, and a top-level module that instantiates the encoder and decoder. The encoder and decoder are designed based on their truth tables. Verilog code and RTL schematics are provided for the encoder, decoder, and top-level modules. A full testbench and waveform are also included to test the system.

1. Hanbat
Hanbat
National
National
University
University
Encoder-Decoder in VerilogEncoder-Decoder in Verilog
Gookyi Dennis A. N.Gookyi Dennis A. N.
SoC Design Lab.SoC Design Lab.
July.15.2014

2. ContentsContents
 Objectives
 Encoder
 Decoder
 Encoder-Decoder
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3. ObjectivesObjectives
 Wish to design a system that encodes at one end and
decode at the other end
 Design a 4 to 2 encoder
 Design a 2 to 4 decoder
 Design a top level module that instantiates the
encoder and the decoder
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4. Block diagramBlock diagram
 The block diagram of the whole system is shown
below:
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4 to 2
Encoder
2 to 4
Decoder
4 Bit input 4 Bit output
2 Bit
inout

5. EncoderEncoder
 Truth table of 4 to 2 encoder is shown below:
 Output equations are as follows:
out[0] = ((~in[3])&(~in[2])&(in[1])&(~in[0])) | (((in[3])&(~in[2])&(~in[1])&(~in[0])))out[0] = ((~in[3])&(~in[2])&(in[1])&(~in[0])) | (((in[3])&(~in[2])&(~in[1])&(~in[0])))
out[1] = ((~in[3])&(in[2])&(~in[1])&(~in[0])) | (((in[3])&(~in[2])&(~in[1])&(~in[0])))out[1] = ((~in[3])&(in[2])&(~in[1])&(~in[0])) | (((in[3])&(~in[2])&(~in[1])&(~in[0])))
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In[3] In[2] In[1] In[0] Out[1] Out[0]
0 0 0 1 0 0
0 0 1 0 0 1
0 1 0 0 1 0
1 0 0 0 1 1

6. EncoderEncoder
 Verilog code for encoder (submodule)
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7. EncoderEncoder
 RTL schematic
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8. DecoderDecoder
 Truth table for 2 to 4 decoder
 Output equations are as follows:
out[0] = (~in[0]) & (~in[1])
out[1] = (in[0]) & (~in[1])
out[2] = (~in[0]) & (in[1])
out[3] = (in[0]) & (in[1])
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In[1] In[0] Out[3] Out[2] Out[1] Out[0]
0 0 0 0 0 1
0 1 0 0 1 0
1 0 0 1 0 0
1 0 1 0 0 0

9. DecoderDecoder
 Verilog code for decoder (submodule)
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10. DecoderDecoder
 RTL schematic
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11. Encoder_DecoderEncoder_Decoder
 Verilog code
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12. Encoder_DecoderEncoder_Decoder
 RTL schematic
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13. Encoder_DecoderEncoder_Decoder
 Full testbench
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14. Encoder_DecoderEncoder_Decoder
 Waveform
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