ppt based on combinational circuits

1. Module 4
Digital Electronics
Combinational Circuits

2. Combinational Circuits
• Combinational Circuit is a logic circuit whose
outputs depends only on present inputs. Which
means a Combinational Circuit doesn’t have
memory of it’s previous outputs.
• Examples : Arithmetic circuits, Decoders,
Multiplexers, Encoders etc.
• A Circuit which have memory of it’s previous
outputs is a sequential circuit.

3. Half Adder
Truth Table of a H.A.
INPUTS OUTPUTS
A B SUM CARRY
0 0 0 0
0 1 1 0
1 0 1 0
1 1 0 1
for H.A.
• SUM is an XOR function
• CARRY is an AND function
SUM = A XOR B = A ⊕ B
CARRY = AAND B = A.B
Half adder is a combinational circuit which will add two
bits and give two outputs as SUM(S) & CARRY(C)

4. Half Adder-Logic circuit

5. Full Adder
Truth Table of a F.A.
Full adder is a combinational circuit which will add three
input bits(A,B,Cin) and give two outputs as SUM(S),
CARRY(Cout)

6. Full adder-Expression of SUM(S)
SUM = A XOR B XOR Cin = A ⊕ B ⊕ Cin
An XOR function can not be
simplified(minimized) .
Simplification of F.A. SUM expression using K-map

7. Full adder-Expression of CARRY(Cout)
From the truth table, we can
found the alternate form of Cout
as
Cout=AB+(A ⊕ B).Cin
from the simplification of K-
map,
Cout=AB+ACin+BCin
Simplification of F.A. CARRY expression using K-map
* Any one of the above two Cout
expressions can be taken for the
realization of F.A. logic circuit

8. Full adder-Circuit & Block diagram
Circuit of F.A. from
simplified SUM &
CARRY (Cout)
expressions.
* 2nd expression of
Cout is taken for this
circuit realization.
Block diagram of F.A.

9. Full adder using two Half adders
Circuit diagram of F.A. using two H.A.

10. Full adder using two Half adders
Block diagram of F.A. using two H.A.

11. Multiplexer(MUX)
• The multiplexer is a combinational logic circuit
designed to switch one of several input lines to a
single common output line by the application of a
control logic.

12. Truth Table:
Block Diagram:
4×1 Multiplexer
The logical expression of the term Y is as follows:
Y=S1' S0' A0+S1' S0 A1+S1 S0' A2+S1 S0 A3

13. 4×1 Multiplexer
The Logical circuit of Y is

14. Binary multiplier
• The standard 2 X 2 binary multiplier is as follows.

15. Encoders & Decoders
• An Encoder is a combinational circuit with
maximum of 2n input lines and ‘n’ output lines. It
will produce a binary code equivalent to the input.
Therefore, the encoder encodes 2n input lines with
‘n’ bits.
• Decoder is a combinational circuit that has ‘n’ input
lines and maximum of 2noutput lines. One of these
outputs will be active High based on the
combination of inputs present. (performs the reverse
operation of Encoder)

16. Encoder Types
1. Octal to Binary Encoder
2. Hexa to Binary Encoder
3. Decimal to Binary Coded Decimal
(BCD) Encoder
4. Priority Encoder

17. A1=Y3+Y2
A0=Y3+Y1
4 to 2 Encoder

18. 4 to 2 Encoder

19. Octal to Binary or 8 to 3 Encoder

20. Octal to Binary or 8 to 3 Encoder

21. A2=Y7+Y6+Y5+Y4
A1=Y7+Y6+Y3+Y2
A0=Y7+Y5+Y3+Y1
Octal to Binary or 8 to 3 Encoder

22. Octal to Binary or 8 to 3 Encoder

23. Decimalto BCD Encoder

24. A3 = Y9 + Y8
A2 = Y7 + Y6 + Y5 +Y4
A1 = Y7 + Y6 + Y3 +Y2
A0 = Y9 + Y7 +Y5 +Y3 + Y1
Decimalto BCD Encoder

25. Decimalto BCD Encoder

26. Drawbacks of normal Encoder
• There is an ambiguity, when all outputs of encoder
are equal to zero. output may become zero when
there is no input is high (or) output may be zero
when LSB of the input is high.
• If more than one input is active High, then the
encoder produces an output, which may not be the
correct code.
• To overcome these drawbacks, we can go for
priority encoder.

27. Priority Encoder
• A priority encoder provide n bits of binary coded
output representing the position of the highest
order active input of 2ninputs. If two or more
inputs are high at the same time, the input having
the highest priority will take precedence.
4x2
Priority
Encoder
Y0
Y1
Y2
Y3
A0
A1
V

28. Priority Encoder
• A 4 to 2 priority encoder has four inputs Y3, Y2,
Y1 & Y0 and two outputs A1 & A0. Here, the
input, Y3 has the highest priority, whereas the
input, Y0 has the lowest priority.
• In this case, even if more than one input is ‘1’ at
the same time, the output will be the (binary)
code corresponding to the input, which is
having higher priority.

29. Priority Encoder
• We considered one more output, V in order to
know, whether the code available at outputs is
valid or not.
• If at least one input of the encoder is ‘1’, then
the code available at outputs is a valid one. In
this case, the output, V will be equal to 1.
• If all the inputs of encoder are ‘0’, then the code
available at outputs is not a valid one. In this
case, the output, V will be equal to 0.

30. Priority Encoder Design-Truth table

31. Priority Encoder Design
• K-map based simplification of expressions for
each output.
K-map for
simplification of
O/P expression A0
A0=Y3+Y2′Y1

32. Priority Encoder Design
• K-map for simplification of O/P expression A1
A1=Y3+Y2

33. From the truth table, Boolean function of output
‘V’ as
V=Y3+Y2+Y1+Y0
Simplified output expressions for circuit design:
A0=Y3+Y2′Y1
A1=Y3+Y2
V=Y3+Y2+Y1+Y0
Priority Encoder Design

34. Logic circuit of 4 by 2 priority encoder
Priority Encoder Design

35. Code converters-Gray code converter
• The gray code is a non weighted code. It is a unit
distance code because, the successive gray code
differs in one bit position only . It is also referred
as cyclic code.
• It is a reflective code. An n-bit Gray code can be
obtained by reflecting an n-1 bit code about an axis
after 2n-1 rows, and putting the MSB of 0 above the
axis and the MSB of 1 below the axis.

36. 4-bit binary and Gray code truth table

37. 4-bit binary to Gray code converter Design
• A 4-bit binary to Gray code converter has 4-
inputs in binary(A,B,C,D) and 4-outputs in
gray(G1,G2,G3,G4).
• Simplified output expressions for G1,G2,G3,G4
can be obtained form K-map based simplification.
• Logic circuit for 4-bit binary to gray converter
can be designed using simplified output
expressions.

38. • Simplification of output G1 using K-map
4-bit binary to Gray code converter Design

39. • Simplification of output G2 using K-map
4-bit binary to Gray code converter Design

40. • Simplification of output G3 using K-map
4-bit binary to Gray code converter Design

41. 4-bit binary to Gray code converter Design
• Simplification of output G4 using K-map

42. Logic circuit for 4-bit binary to gray code converter
4-bit binary to Gray code converter Design