structural modeling, hazards, simulation, trireg net, switch level modeling, cmos switch, mos, verilog, hdl

1. Hanbat
Hanbat
National
National
University
University
Structural ModelingStructural Modeling
Gookyi Dennis A. N.Gookyi Dennis A. N.
SoC Design Lab.SoC Design Lab.
June.03.2014

2. ContentsContents
 Hazards
 Static Hazards
 Dynamic Hazards
 Switch Primitives
 Signal Strengths
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3. HazardsHazards
 Outputs of combinational logic consists of many
signals propagated from different paths
 Due to propagation delays of these paths, the
output signal must experience an amount of time
during which fluctuations occurs
 This duration is called transient time of the
output signal and it results in several short
pulses called glitches
 A hazard is raised when fluctuation occur during
the transient time
 Hazards can be divided into:
Static hazards
Dynamic hazards
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4. Static HazardsStatic Hazards
 This is a situation when the output produces a “0”
when its stable value is “1” and a “1” glitch when
its stable value is “0”
 Static hazard can be divided into:
static-0 hazard
Static-1 hazard
 Consider the logic circuit shown below
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5. Static HazardStatic Hazard
 code
 Testbench
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6. Waveform of Static HazardWaveform of Static Hazard
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7. Eliminating Static HazardsEliminating Static Hazards
 Consider the K-map shown below:
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8. WaveformWaveform
 Waveform
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9. Dynamic HazardDynamic Hazard
 Dynamic hazard is a situation where the output of a
circuit changes from 0 to 1 and to 0 (or 1 to 0 and
then to 1)
 The output changes three or more times
 Because three or more signal changes are required
for dynamic hazard, a signal must arrive at the
output at three different times
 Consider the logic circuit shown below:
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10. Dynamic HazardDynamic Hazard
 Code
 Testbench
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11. Waveform of Dynamic HazardWaveform of Dynamic Hazard
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12. Switch-Level ModelingSwitch-Level Modeling
 All MOS transistors in switch level modeling can be
grouped into two groups:
 Ideal switches
 Non-ideal switches
 In ideal switches, there is no signal degradation
when turned on
 In non-ideal switches, there is a finite amount of
signal degradation
 All non-ideal switches are prefix with the letter
“r” in Verilog
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13. MOS SwitchesMOS Switches
 There are two MOS switches:
 nmos/rnmos
 pmos/rpmos
 The figure show nmos and pmos and their truth table
 To instantiate switch elements
switch_name [instance_name] (output, input, 13

14. CMOS inverterCMOS inverter
 Circuit and logic symbol
 Code
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15. NOT WaveformNOT Waveform
 Testbench
 Waveform
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16. CMOS NAND GateCMOS NAND Gate
 Circuit diagram and code
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17. NAND WaveformNAND Waveform
 Testbench
 Waveform
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18. CMOS SwitchCMOS Switch
 The cmos and rcmos switches consists of a data
input, a data output and two control inputs
 Truth table and block diagram:
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19. CMOS SwitchCMOS Switch
 To instantiate CMOS switches
cmos [instance_name] (output, input, ncontrol,
pcontrol);
 This is actually equivalent to:
nmos (output, input, ncontrol);
pmos (output, input, pcontrol);
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20. CMOS SwitchesCMOS Switches
 Below is he block diagram and code for 2-to-1
multiplexer constructed by using CMOS switches
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21. WaveformWaveform
 Testbench
 Waveform
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22. Signal StrengthSignal Strength
 Signal strength represents the ability of the
source device to supply energy to drive the signal
 There are two kinds of signal strength:
Driving strength
Charge storage strength
 Signals with driving strengths propagate from gate
outputs and continuous assignment outputs
 There are four driving strengths: supply, strong,
pull and weak
 Signals with charge strength originates from trireg
nets
 There are three charge storage strengths: large,
medium, small
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23. Signal StrengthSignal Strength
 Strength level for scalar signal values
 Scale of strengths
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24. Signal StrengthSignal Strength
 A strength specification has two components:
(strength0, strength1) or (strength1, strength0)
 The default strength specification is:
(strong0, strong1)
 An output port of a gate primitive with drive
strength has the syntax below:
gate_name (strength1,strength0) [delay]
[instance_name]
(port_list);
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25. Signal ContentionSignal Contention
 When multiple drivers drive a net at the same time,
contention occurs on the net
 Some of the rules for resolving contention is as
below:
 If two signals of unequal strength combine, the
stronger signal is the results
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26. Signal ContentionSignal Contention
 When two signals of equal strength and opposite
value combine, the result has a value of x and the
strength level of both signals and all smaller
strength levels
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27. Signal ContentionSignal Contention
 Block diagram, code and testbench:
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y
a
b

28. WaveformWaveform
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29. Trireg NetTrireg Net
 The trireg net stores a value and it is used to
model charge storage nodes
 It can be in one of the two states below:
 Driven state: At least one driver drives a value of
1, 0 or x on the net. The value is retained on the
net. It takes the strength of the driver. The
strength could be supply, strong, pull or weak
 Capacitive state: When all the drivers to a trireg
net are at the high-impedance (z), the net retains
its last driven value. The strength could be small,
medium (default) or large
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30. Trireg NetsTrireg Nets
 Block diagram and code:
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31. Simulation ResultsSimulation Results
 run
#0 a=St1 b=St1 c=St1 x=St0 y=St0 z=St0
#10 a=St1 b=St0 c=St1 x=St0 y=HiZ z=Me0
#40 a=St1 b=St1 c=St1 x=St0 y=St0 z=St0
#50 a=St1 b=St0 c=St1 x=St0 y=HiZ z=Me0
 Waveform
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