Verilog operators

Digital Design Using Verilog
- For Absolute Beginners
LECTURE6 : VERILOG OPERATORS

Introduction
• Normally the operators work on any specific data
types or operands to give expected results.
• As Verilog is mainly used to describe the hardware
behavior and functioning, it supports a variety of
pre-defined operators .
• But it should be always remembered that not all the
operands are synthesizable.
•Some of these operators are similar to the operators
used in the C programming language.
•Each operator type is denoted by a symbol

contd
• The different types of Operators supported are
• Assignment operator
• Arithmetic operators
• Logical operators
• relational, equality operators
• Bitwise operators
• Reduction operators
• Shift operators
• Concatenation and Conditional etc.

ASSIGNMENT OPERATOR
• Verilog uses the equal sign (=) to denote an
assignment.
• The left-hand side (LHS) of the assignment is the
target signal. The right-hand side (RHS) contains the
input arguments and can contain both signals,
constants, and operators.
• Ex: Y = a & b;
• F2 = 8’hAA;
• F1 = A ;
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• The most fundamental operators are Arithmetic
operators.
• Broadly there are two types of arithmetic operators.
(i).Unary and (ii).Binary
Unary Operators: A unary operator is an operator that
takes a single operand in an expression or a statement.
+ : addition % : modulus
- : subtraction ** : exponentiaion
* : multiplication / : divide
ARITHMETIC OPERATORS

contd
Ex: +A ; - Y ; - (A+B) ; ** D Exponential D etc.
• Binary Operators : A binary operator is an operator
that operates on two operands and manipulates them
to return a result.
• Y = (A+B) * (B+C)
• X = (A+B) / (C-D)
• D =A + D : Addition operator surrounded by two
operands

Illustration
• module Arithmetic (A, B, Y1, Y2, Y3, Y4, Y5);
input [2:0] A, B;
output [3:0] Y1;
output [4:0] Y3;
output [2:0] Y2, Y4, Y5;
reg [3:0] Y1;
reg [4:0] Y3;
reg [2:0] Y2, Y4, Y5;
always @(A or B)
begin
Y1=A+B; //addition operation
Y2=A-B; //subtraction operation
Y3=A*B; //multiplication operation
Y4=A/B; //division operation
Y5=A%B; //modulus of A divided by B
end
endmodule
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% Modulus operator
• The modulus operator is denoted by the symbol %.
• For example A % B, gives the remainder when the first operand is
divided by the second, and thus is zero when B divides A exactly.
• The result of a modulus operation shall take the sign of the first
operand.

Logical Operator
• These operators deals with true or false logic . i.e
the logical operators return either 0 or 1.
• Logical comparison operators are used in conjuction
with relational and equality operators .
• These operators are widely used in if ; While
statements. And, provide a means to perform
multiple comparisons within a single expression.
• ! : Logical negation. Ex : ! (A && B)
&& : Logical AND
|| : Logical OR Ex : A || B

contd
• Logical operators produce 1-bit results.
• The result of && is one if none of the operands is 0.
• The result of || is 1 if at least one of the operands is
non-zero.
• The ! Operator complements its operand and
produces 1 or a 0. If X or Z appears in an operand
of the logical operand ,an X will be the result.The !
Operator has the highest precedence, followed by
&& and || .

Examples
• Let A = 3’b101 ; B = 3’b000; C = 3’B01X
• !A = 1b0 ;
• !B = 1’b1 ;
• !C = 1’Bx
• A && B => 1’b 0 ; // since one operand is zero
• B&&C=> 1’bX;// one operand is unknown
• A || B => 1’b1 // one of the operands is non-zero
• B || C => 1’bX

Example-2
• module ex_logical (A, B, C, D, E, F, Y);
input [2:0] A, B, C, D, E, F;
output Y;
reg Y;
always @ (A or B or C or D or E or F)
begin
if ((A= =B) && ((C>D) || !(E<F)))
Y=1;
else
Y=0;
end
endmodule

Relational & Equality Operators
• These operators are mainly used to compare data
values.
• = = Equality ; != Not equal(Inequality)
• = = = : Case equality ; ! = = Case inequality.
• >= Greater or equal ; <= Less than or equal
• > Greater ; < Less
• Here = = ; ! = ; = = = are the equality operators
• Case equality is used to compare the values with x
or z.

Example for Case Equality
• Let A = 1011; B = 1011
A = =B ; The result is true;
• Let A = 0110 ; B = 1011;
A == B ; The result is false ,as they are not equal.
• Suppose A= 101X ; B = 101X ;
• A ==B ; The result is unknown x
So, One has to use case Equality operator. In a case equality
A = = = B ; The result is 1 (true).
• Suppose A=101X & B= 011X.The the result will be False
i.e 0.

Illustration
• module ex_relational (A, B, Y1, Y2, Y3, Y4);
input [2:0] A, B;
output Y1, Y2, Y3, Y4;
reg Y1, Y2, Y3, Y4;
always @(A or B)
begin
Y1=A<B;//less than
Y2=A<=B;//less than or equal to
Y3=A>B;//greater than
if (A>B)
Y4=1;
else
Y4=0;
end
endmodule

Illustration-Equality operators
• module ex_equality (a, b, y1, y2, y3);
input [2:0] a,b;
output y1,y2;
output [2:0] y3;
reg y1,y2;
reg [2:0] y3;
always @(a or b)
begin
y1= a= =b;// y1=1 if a equivalent to b
y2=a!=b;//y2=1 if a not equivalent to b
if (a= =b) //
y3= a;
else
y3= b;
end
endmodule

Bitwise Operators
• Verilog bitwise operators can be either unary or
binary. Result is always the size of largest operand.
• i.e the meaning is , logical bit-wise operators take
two single or multiple operands on either side of the
operator and return a single bit result.
• The only exception is the NOT operator, which
negates the single operand that follows.
• Verilog does not have the equivalent of NAND or
NOR operator, their function is implemented by
negating the AND and OR operators.

contd
• ~ : bitwise NOT(Invert)
• & : bit wise AND
• | : bitwise OR
• ^ : bitwise Exclusive OR
• ~ ^ : bitwise exclusive NOR
• Bit wise operators operate on each bit and returns a
value that is also a bit.

Bitwise Operators contd
• If two operands are unequal ,the smaller one is left
extended by adding zeros.
• Ex : a = 4’b1001 and b = 3’b 101.
To find a & b , the second operand is taken as
b = 4’b0101 and then logical & operation is
performed.
a & b => 4’b0001
The size of the result is 4 bits .

Examples
• assign a => 4’b1011 ; b=> 4’b1101 ; c => 4’b0111;
• ~ a => 4’b 0100 ; ~b=> 4’b0010 ; ~c => 4’b1000;
• a & b => 4’b1001 ; b & c => 4’b 0101
• a | b => 4’b1111 ; b | c => 4’b1111
• a ^ b => 4’b 0110 ; b ^ c => 4’b 1010
• a ^ ~b => 4’b 1001 ; b ^ ~ c => 4’b 0101

Example-2
• module ex_Bitwise (A, B, Y);
input [6:0] A;
input [5:0] B;
output [6:0] Y;
reg [6:0] Y;
always @(A or B)
begin
Y(0)=A(0)&B(0); // binary AND
Y(1)=A(1)|B(1); // binary OR
Y(2)=!(A(2)&B(2)); // negated AND (NAND)
Y(3)=!(A(3)|B(3)); // negated OR (NOR)
Y(4)=A(4)^B(4); // binary XOR
Y(5)=A(5)~^B(5); // binary XNOR
Y(6)=!A(6); // unary negation
end
endmodule

Reduction Operators
• Reduces a vector to a single bit value. i.e a multibit
value is reduced to a single bit value.
• Majority of the times this is a unary operator.
• To say in terms of hardware , This reduction
operator works like a multiple input bits logic
gate,which accepts a single word operand and
produces a single bit as output.
• The operators are
• & and ; ~ & not and(nand) ; | or ; ~ | not or (nor)
• ^ x-or ; ~ ^ not or (x-nor)

Examples
• For ex, in the ‘and’ gate for
the Inputs 1011 the output is 0.
• Similarly let us consider or gate as shown below.
• So, these reduction operands are reducing a multibit
operands into single bit operands.
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Examples contd
• Let us consider the x-or gate .
• y = ^ A where A = 4’b0110
i.e y = 0 ^1^1^0 = 1

Example for Reduction Operator
• module red_ex(a,b,c,y1,y2,y3);
input a, b, c ;
output y1,y2,y3 ;
wire[7:0] a,b,c ;
wire [7:0]y1,y2,y3 ;
assign a=4’b0111;
assign b=4’b0111;
assign c=4’b0100;
assign y1 = ^a // gives y1 = 1
assign y2 = &(a^b); //gives y2=0
assign y3 = ^a&^b; //gives y3 = 1

SHIFT OPERATORS
• Generally ,the shift operators are used to shift the
operand bits either left or right.
• Shift operators require two operands. The operand
before the operator contains data to be shifted and
the operand after the operator contains the
number of single bit shift operations to be
performed.
• Verilog has two types of shift operators .
• i. Logical Shift and ii.Arithmetic shift operators.

• This shifting is done in two ways. Either Left shift
or Right shift.
• Logical Right shift operator is denoted by >>
• Logical Left shift operator is <<.
• In logical shift vacated positions are always filled
with zero(0).
• In terms of the operation right shift means divide by
2 also.
• Similarly Left shift operation will result in multiply
of the operand by 2.
contd

Arithmetic Shift Operators
• Right arithmetic shift is denoted by the symbol >>>
• Left arithmetic shift is denoted by <<<.
• In arithmetic shift: For signed numbers , the vacated
position is filled with sign bit value(MSB bit)
• For unsigned ,the vacated positions are filled with
zero.

Code-Example
• module ex_shift (a, y1, y2);
input [7:0] a;
output [7:0] y1, y2;
parameter b=3; reg [7:0] y1, y2;
always @(a)
begin
y1=a<<b; //logical shift left
y2=a>>b; //logical shift right
end
• endmodule

Concatenation Operator{,}
• The concatenation operator "{ , }" combines or
(concatenates) the bits of two or more data objects.
• The objects may be scalar (single bit) or vectored (muliple
bit).
• Mutiple concatenations may be performed with a constant
prefix and is known as replication.
• For ex: By concatenating two 4-bit operands, an 8-bit
operand is formed.
• Remember it is not direct arithmetic addition.
• Ex: Let A= 4’b1011; B=4’b 1010;
assign y = {a,b} gives y=> 8b’10111010

Replicate Operator
• It replicates the operand for a specified number of
times.( or copied specified number of times).
• For ex: assign y = {3{3’b110}} results in
• y = 9’b110110110

Conditional Operator(?)
• An expression using conditional operator evaluates
the logical expression before the "?".
• If the expression is true then the expression before
the colon (:) is evaluated and assigned to the output.
• If the logical expression is false then the expression
after the colon is evaluated and assigned to the
output.

Example code
• To understand the Conditional operator lets consider
the 2:1 Mux example.
Ex: module mymux2_1(A,B,S,Y);
output Y;
input A,B,S;
assign Y= S ? B:A;
endmodule
Note: In the above ,first the ‘S’ is tested .If it is
true,then Y= B else Y = A

The Conclusion

Verilog operators

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