This document discusses decoders, which are circuits that take a binary input and activate one of multiple outputs. It provides examples of 2-to-4 and 3-to-8 decoders and their truth tables. Decoders are constructed using AND gates, with the number of gates equal to the number of outputs. Larger decoders can be built in parallel, balanced, or tree configurations, with balanced decoders requiring the fewest components.

1. DECODERS
PRESENTED BY
GHOLAMREZA KAKAMANSHADI
PANJAB UNIVERSITY, CHD, INDIA
JUL,2013

2. Definition:
• An important part of the system which selects
the cells to be read from and written into is the
decoder.
– Accepts a value and decodes it
• Output corresponds to value of n inputs
• It also is called many-to-one decoder, a
decoder matrix or simply a decoder.

3. A decoder consists of:
• Inputs (n)
• Outputs (2n , numbered from 0  2n - 1)
• Selectors / Enable (active high or active low)
• The decoder has the characteristic that for each
of the possible 2 𝑛
binary input numbers which
can be taken by the n input cells, the matrix
will have a unique one of its 2 𝑛
output lines
selected.
Input
n=2
Output
22=4
Input
n=3
Output
23
=8

4. n
Input
𝟐 𝒏
Out putDecoder
n is the number of input flip-flop
being decoded.
Number of AND gates is equal to
number of output lines

5. Q0 = S1 S0
Q1 = S1 S0
Q2 = S1 S0
Q3 = S1 S0
Input
n=2
Output
22
=4

6. What a decoder does
• A n-to-2
n
decoder takes an n-bit input and produces 2
n
outputs. The
n inputs represent a binary number that determines which of the 2
n
outputs is uniquely true.
• A 2-to-4 decoder operates according to the following truth table.
– The 2-bit input is called S1S0, and the four outputs are Q0-Q3.
– If the input is the binary number i, then output Qi is uniquely true.
• For example, if the input S1 S0 = 10, then output Q2 is true, and Q0,
Q1, Q3 are all false.
• This circuit “decodes” a binary number into a “one-of-four” code.
S1 S0 Q0 Q1 Q2 Q3
0 0 1 0 0 0
0 1 0 1 0 0
1 0 0 0 1 0
1 1 0 0 0 1

7. How can you build a 2-to-4 decoder?
• Follow the design procedures from last time! We have a truth
table, so we can write equations for each of the four outputs
(Q0-Q3), based on the two inputs (S0-S1).
• Here are the equations:
S1 S0 Q0 Q1 Q2 Q3
0 0 1 0 0 0
0 1 0 1 0 0
1 0 0 0 1 0
1 1 0 0 0 1
Q0 = S1 S0
Q1 = S1 S0
Q2 = S1 S0
Q3 = S1 S0

8. A picture of a 2-to-4 decoder
S1 S0 Q0 Q1 Q2 Q3
0 0 1 0 0 0
0 1 0 1 0 0
1 0 0 0 1 0
1 1 0 0 0 1

9. 2-to-4 Decoder

10. Enable inputs
• Many devices have an additional enable input, which is used to
“activate” or “deactivate” the device.
• For a decoder,
– EN=1 activates the decoder, so it behaves as specified earlier. Exactly
one of the outputs will be 1.
– EN=0 “deactivates” the decoder. By convention, that means all of the
decoder’s outputs are 0.
• We can include this additional input in the decoder’s truth table:
EN S1 S0 Q0 Q1 Q2 Q3
0 0 0 0 0 0 0
0 0 1 0 0 0 0
0 1 0 0 0 0 0
0 1 1 0 0 0 0
1 0 0 1 0 0 0
1 0 1 0 1 0 0
1 1 0 0 0 1 0
1 1 1 0 0 0 1

11. • In this table, note that whenever
EN=0, the outputs are always 0,
regardless of inputs S1 and S0.
• We can abbreviate the table by
writing x’s in the input columns
for S1 and S0.
EN S1 S0 Q0 Q1 Q2 Q3
0 0 0 0 0 0 0
0 0 1 0 0 0 0
0 1 0 0 0 0 0
0 1 1 0 0 0 0
1 0 0 1 0 0 0
1 0 1 0 1 0 0
1 1 0 0 0 1 0
1 1 1 0 0 0 1
EN S1 S0 Q0 Q1 Q2 Q3
0 x x 0 0 0 0
1 0 0 1 0 0 0
1 0 1 0 1 0 0
1 1 0 0 0 1 0
1 1 1 0 0 0 1

12. A 3-to-8 decoder
• Larger decoders are similar. Here is a 3-to-8
decoder.
– The block symbol is on the right.
– A truth table (without EN) is below.
– Output equations are at the bottom right.
• Again, only one output is true for any input
combination.
S2 S1 S0 Q0 Q1 Q2 Q3 Q4 Q5 Q6 Q7
0 0 0 1 0 0 0 0 0 0 0
0 0 1 0 1 0 0 0 0 0 0
0 1 0 0 0 1 0 0 0 0 0
0 1 1 0 0 0 1 0 0 0 0
1 0 0 0 0 0 0 1 0 0 0
1 0 1 0 0 0 0 0 1 0 0
1 1 0 0 0 0 0 0 0 1 0
1 1 1 0 0 0 0 0 0 0 1
Q0 = S2’ S1’ S0’
Q1 = S2’ S1’ S0
Q2 = S2’ S1 S0’
Q3 = S2’ S1 S0
Q4 = S2 S1’ S0’
Q5 = S2 S1’ S0
Q6 = S2 S1 S0’
Q7 = S2 S1 S0
Design a 3-to-8 decoderAssignment

13. • The decoder is often constructed by using
diodes or transistors in the AND gates.
• The number of diodes used in each AND gate
is equal to the number of input to each and
gate. The number of AND gates is equal to
number of output (2 𝑛
).
So total number of diodes is: n* 2 𝑛

14. • Number of diodes required increases sharply
with number of inputs to the network.
Example: To decode an eight flip-flop register we would
require 8*28
= 2048 diodes if the decoder were constructed
in this manner.

15. • Several types of structures are often used in
building of decoder networks.
Example:
 Parallel decoder
 Balanced decoder
 Tree decoder

16. Parallel decoder
X2 X2 X3 X3
X1
X1
X1 X2 X3
X1 X2 X3
X1 X2 X3
0 0 0
0 0 1
1 1 1
23
*3=24 diodes would be require to build the parallel decoder

17. • In tree network decoders there is four flip-
flops and so has 24
=16 output lines.
An examination will show that 56 diodes are
required to build it. There is another type of
decoder which is called a balanced decoder
network. This network requires only 48 diodes.
And it shown that this type of decoder network
requires the minimum number of diodes.

18. Tree Decoder

19. Balanced decoder

20. • The difference in the number of diodes or
decoding elements to build a network such as
balance decoders compared with parallel or
tree decoders becomes more significant as the
number of flip-flops to decoded increases.
• Parallel decoder network has the advantage of
being fastest and most regular in construction
of the three types.

21. The End