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2 when to_test_role_of_testing

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Usha Mehta
Usha Mehta

This document provides an overview of VLSI design and testing processes. It discusses various stages in the design flow from behavioral to physical design. It describes the importance of verification, validation, and testing at each stage to detect errors and ensure quality. These include simulation, emulation, formal methods, probe testing, and burn-in testing. Factors like process variations that affect speed are addressed through speed binning. The document emphasizes that testing is crucial throughout the design and manufacturing cycles to find faults and prevent defective chips from reaching customers.

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Dr Usha Mehta usha.mehta@ieee.org usha.mehta@nirmauni.ac.in 1 Dr Usha Mehta 25-01-2022
Acknowledgement….. This presentation has been summarized from various books, papers, websites and presentations on VLSI Design and its various topics all over the world. I couldn’t item-wise mention from where these large pull of hints and work come. However, I’d like to thank all professors and scientists who created such a good work on this emerging field. Without those efforts in this very emerging technology, these notes and slides can’t be finished. 2 Dr Usha Mehta 25-01-2022
25- 01- 202 2 Dr Usha Mehta 3
Once they grow…… 25- 01- 202 2 Dr Usha Mehta 4 Cost – Rule of 10 It costs 10 times more to test a device as we move to higher level in the product manufacturing process
25- 01- 202 2 Dr Usha Mehta 5
• Design Errors • Misinterpretation of specification • Fabrication Errors • Wrong component • Incorrect Wiring • Fabrication Defects • Imperfect Process Variations • Physical Failure • During life time of a system 25- 01- 202 2 Dr Usha Mehta 6
ASIC Design Flow 25- 01- 202 2 Dr Usha Mehta 7
Architectural Behavioural RTL Gate Transistor Physical Unpacked Chip 25- 01- 202 2 Dr Usha Mehta 8 Circuit Chip, Components, Interconnects… System System on Chip Network on Chip Prototype Testing Mass Production Testing System @ Field
Role of Testing in General • Verification • will any fault occur? • Validation • will fault occur during mass production? • Detection • Is there any fault? Yes or no? • Diagnosis • Where is the fault? • Device Characterization • Why the fault occurred? (Is design wrong or test process wrong?) • Failure Mode Analysis (FMA) • How that fault can be prevented? (Is manufacturing process wrong?) • Burn-In • Will it work for longer life? • Speed Binning • What is the speed of device? • Acceptance Testing/Incoming Inspection • Should I use it in my system? 9 Dr Usha Mehta 25-01-2022
Verification • Verifies the correctness of Design • Performed once prior to manufacturing process • Performed by simulation, hardware emulation or formal methods • Responsible for quality of design • Like sonography used for unborn baby during pregnancy 10 Dr Usha Mehta 25-01-2022
Validation Verification Testing/Characterization / Design Debug • After the first lot of prototypes are manufactured, IC goes through, design validation/pilot-run stage. • It checks that either the fabrication process was correct and fabricated IC is correct. ( Here it is assumed that design was error free) • Also verifies the correctness of test procedure. • AC, DC, Functional Test • Probing internal chip nodes also • Special tools like scanning electron Microscope, electron beam scanner, artificial intelligent technique etc, are used • Like Newborn sreening tests for baby 11 Dr Usha Mehta 25-01-2022
Diagnosis • Identify the fault that exists in system. • Which fault is there (type of fault)? • Where is that fault (fault location)? • Like after a set of pathological test, the doctor diagnosis your disease. 12 Dr Usha Mehta 25-01-2022
Device Characterization • Determination and correction of errors in device and/or test procedure • So that the next lot of IC will be error free. • Like doctor writes a prescription of medicine to cure your disease. • Here there is a difference between man and IC!!!!!!!!! 13 Dr Usha Mehta 25-01-2022
Failure Mode Analysis • Why/How/when the fault had occurred? • Determine the manufacturing process errors that may have caused the fault. • Like determining why that disease occurred and find the preventive actions (bad health /food habits) which created disease 14 Dr Usha Mehta 25-01-2022
Detection (testing in general…) • Does any of the fault exists? • Which, why, how, where, when is out of scope here. • Only YES/NO. Go/No Go test for IC to be shipped to market or not. • At fabrication unit • For all fabricated IC • Less comprehensive than characterization • Test should have high fault coverage, low cost and minimum test time • Are you completely fit? Does any of the disease there? • Like medical test for army ( if fit then go, otherwise no go) 15 Dr Usha Mehta 25-01-2022
Burn-In/Stress Test • To stress the chip to accelerate the failure mechanism • Some chip passes the production test but will fail very quickly thereafter • To increase temp and/or voltage while applying test patterns • Infant Mortality Failures: 10-30 Hrs • Freak Failure: 100-1000Hrs 16 Dr Usha Mehta 25-01-2022
Acceptance Testing/ Incoming Inspection • Customer performs this test • Like universal tester to test the IC at our Digital Electronics Labs 17 Dr Usha Mehta 25-01-2022
Place of Verification in Design Flow • Specification • Finalization of specification • Behavioural Description/RTL code • Functional Verification • Gate level netlist • Static timing analysis • Circuit level • Propagation delay • Physical Domain • Layout vs Schematic (LVS) • During Fabrication • Wafer testing • Pilot lot production • Validation • Mass production • Testing • Burn-In • Speed Binning • Yield loss • Diagnosis • Failure Mode Analysis • Before use • Acceptance/Incomin g Testing • In-System 18 Dr Usha Mehta 25-01-2022
Speed Binning • CMOS is made of pMOS and nMOS. • Generally, the design is such a way that both of them have same speed • But the performance can vary because of PVT • Process variations (P), Supply Voltage (V), Temperature (T) • But during fabrication process, due to process variations speed may be degraded 19 Dr Usha Mehta 25-01-2022
Speed Binning…… Process Variations • Variations in the process parameters can be impurity concentration densities, oxide thicknesses and diffusion depths. • This introduces variations in the sheet resistance and transistor parameters such as threshold voltage. • Dimension variations of the devices, are mainly resulted from the limited resolution of the photolithographic process. • This causes (W/L) variations in MOS transistors 20 Dr Usha Mehta 25-01-2022
Speed Binning….. Process Corners • There are five possible corners of an n vs. p mobility graph: • typical-typical (TT) (not really a corner !), fast- fast (FF), slow-slow (SS), fast-slow (FS), and slow-fast (SF). • TT, FF and SS (even corners) • Both types of devices are affected evenly, and generally do not adversely affect the logical correctness of the circuit. • FS, SF ("skewed" corners) • one type of FET will switch much faster than the other, and this form of imbalanced switching can cause one edge of the output to have much less slew than the other edge. 21 Dr Usha Mehta 25-01-2022
Verification • On Design (functionality, estimated speed) • Pre-silicon • One time • Methods: • Simulation • Emulation • formal methods • A Design Bug • Makes all Fabricated IC useless Detection/Testing • On Device (manufactured hardware) • Post-Silicon • On each and every IC being fabricated • Methods: • Test Generation • Test Application • A fabrication defect • May cause all ICs or Some of the ICs useless. 22 Dr Usha Mehta 25-01-2022
TTM : Time-to-MONEY 23 Dr Usha Mehta 25-01-2022 Validation Test
Failure Rate vs Product Life Time 24 Dr Usha Mehta 25-01-2022
Thanks……

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2 when to_test_role_of_testing

  • 2. Acknowledgement….. This presentation has been summarized from various books, papers, websites and presentations on VLSI Design and its various topics all over the world. I couldn’t item-wise mention from where these large pull of hints and work come. However, I’d like to thank all professors and scientists who created such a good work on this emerging field. Without those efforts in this very emerging technology, these notes and slides can’t be finished. 2 Dr Usha Mehta 25-01-2022
  • 4. Once they grow…… 25- 01- 202 2 Dr Usha Mehta 4 Cost – Rule of 10 It costs 10 times more to test a device as we move to higher level in the product manufacturing process
  • 6. • Design Errors • Misinterpretation of specification • Fabrication Errors • Wrong component • Incorrect Wiring • Fabrication Defects • Imperfect Process Variations • Physical Failure • During life time of a system 25- 01- 202 2 Dr Usha Mehta 6
  • 8. Architectural Behavioural RTL Gate Transistor Physical Unpacked Chip 25- 01- 202 2 Dr Usha Mehta 8 Circuit Chip, Components, Interconnects… System System on Chip Network on Chip Prototype Testing Mass Production Testing System @ Field
  • 9. Role of Testing in General • Verification • will any fault occur? • Validation • will fault occur during mass production? • Detection • Is there any fault? Yes or no? • Diagnosis • Where is the fault? • Device Characterization • Why the fault occurred? (Is design wrong or test process wrong?) • Failure Mode Analysis (FMA) • How that fault can be prevented? (Is manufacturing process wrong?) • Burn-In • Will it work for longer life? • Speed Binning • What is the speed of device? • Acceptance Testing/Incoming Inspection • Should I use it in my system? 9 Dr Usha Mehta 25-01-2022
  • 10. Verification • Verifies the correctness of Design • Performed once prior to manufacturing process • Performed by simulation, hardware emulation or formal methods • Responsible for quality of design • Like sonography used for unborn baby during pregnancy 10 Dr Usha Mehta 25-01-2022
  • 11. Validation Verification Testing/Characterization / Design Debug • After the first lot of prototypes are manufactured, IC goes through, design validation/pilot-run stage. • It checks that either the fabrication process was correct and fabricated IC is correct. ( Here it is assumed that design was error free) • Also verifies the correctness of test procedure. • AC, DC, Functional Test • Probing internal chip nodes also • Special tools like scanning electron Microscope, electron beam scanner, artificial intelligent technique etc, are used • Like Newborn sreening tests for baby 11 Dr Usha Mehta 25-01-2022
  • 12. Diagnosis • Identify the fault that exists in system. • Which fault is there (type of fault)? • Where is that fault (fault location)? • Like after a set of pathological test, the doctor diagnosis your disease. 12 Dr Usha Mehta 25-01-2022
  • 13. Device Characterization • Determination and correction of errors in device and/or test procedure • So that the next lot of IC will be error free. • Like doctor writes a prescription of medicine to cure your disease. • Here there is a difference between man and IC!!!!!!!!! 13 Dr Usha Mehta 25-01-2022
  • 14. Failure Mode Analysis • Why/How/when the fault had occurred? • Determine the manufacturing process errors that may have caused the fault. • Like determining why that disease occurred and find the preventive actions (bad health /food habits) which created disease 14 Dr Usha Mehta 25-01-2022
  • 15. Detection (testing in general…) • Does any of the fault exists? • Which, why, how, where, when is out of scope here. • Only YES/NO. Go/No Go test for IC to be shipped to market or not. • At fabrication unit • For all fabricated IC • Less comprehensive than characterization • Test should have high fault coverage, low cost and minimum test time • Are you completely fit? Does any of the disease there? • Like medical test for army ( if fit then go, otherwise no go) 15 Dr Usha Mehta 25-01-2022
  • 16. Burn-In/Stress Test • To stress the chip to accelerate the failure mechanism • Some chip passes the production test but will fail very quickly thereafter • To increase temp and/or voltage while applying test patterns • Infant Mortality Failures: 10-30 Hrs • Freak Failure: 100-1000Hrs 16 Dr Usha Mehta 25-01-2022
  • 17. Acceptance Testing/ Incoming Inspection • Customer performs this test • Like universal tester to test the IC at our Digital Electronics Labs 17 Dr Usha Mehta 25-01-2022
  • 18. Place of Verification in Design Flow • Specification • Finalization of specification • Behavioural Description/RTL code • Functional Verification • Gate level netlist • Static timing analysis • Circuit level • Propagation delay • Physical Domain • Layout vs Schematic (LVS) • During Fabrication • Wafer testing • Pilot lot production • Validation • Mass production • Testing • Burn-In • Speed Binning • Yield loss • Diagnosis • Failure Mode Analysis • Before use • Acceptance/Incomin g Testing • In-System 18 Dr Usha Mehta 25-01-2022
  • 19. Speed Binning • CMOS is made of pMOS and nMOS. • Generally, the design is such a way that both of them have same speed • But the performance can vary because of PVT • Process variations (P), Supply Voltage (V), Temperature (T) • But during fabrication process, due to process variations speed may be degraded 19 Dr Usha Mehta 25-01-2022
  • 20. Speed Binning…… Process Variations • Variations in the process parameters can be impurity concentration densities, oxide thicknesses and diffusion depths. • This introduces variations in the sheet resistance and transistor parameters such as threshold voltage. • Dimension variations of the devices, are mainly resulted from the limited resolution of the photolithographic process. • This causes (W/L) variations in MOS transistors 20 Dr Usha Mehta 25-01-2022
  • 21. Speed Binning….. Process Corners • There are five possible corners of an n vs. p mobility graph: • typical-typical (TT) (not really a corner !), fast- fast (FF), slow-slow (SS), fast-slow (FS), and slow-fast (SF). • TT, FF and SS (even corners) • Both types of devices are affected evenly, and generally do not adversely affect the logical correctness of the circuit. • FS, SF ("skewed" corners) • one type of FET will switch much faster than the other, and this form of imbalanced switching can cause one edge of the output to have much less slew than the other edge. 21 Dr Usha Mehta 25-01-2022
  • 22. Verification • On Design (functionality, estimated speed) • Pre-silicon • One time • Methods: • Simulation • Emulation • formal methods • A Design Bug • Makes all Fabricated IC useless Detection/Testing • On Device (manufactured hardware) • Post-Silicon • On each and every IC being fabricated • Methods: • Test Generation • Test Application • A fabrication defect • May cause all ICs or Some of the ICs useless. 22 Dr Usha Mehta 25-01-2022
  • 24. Failure Rate vs Product Life Time 24 Dr Usha Mehta 25-01-2022
  • 25.