VLSI Static Timing Analysis, STA

1. Concept of
Timing Analysis
Prof. Usha Mehta
Professor,
PG-VLSI Design,
EC, Institute of Technology,
Nirma University, Ahmedabad
usha.mehta@nirmauni.ac.in
usha.mehta@ieee.org
◼ Does the design
meet a given
timing
requirement?!!
◼ How fast can I run
the design?!!!

2. 3/3/2023
Static
Timing
Analysis
Acknowledgement
This presentation has been summarized
from various books, papers, websites and
presentations and so on …. all over the
world. I couldn’t remember where these
large pull of hints and work come from.
However, I’d like to thank all professors and
scientists who create such a good work on
this emerging field. Without those efforts in
this very emerging technology, these notes
and slides can’t be finished. I am thankful
to them to make my teaching process more
effective.

3. 3/3/2023
Static
Timing
Analysis
Agenda
• ASIC Design Flow : with timing
considerations
• Objective of Timing Analysis
• Types of Timing Analysis
• Static Timing Analysis : Introduction
• STA in ASIC Flow
• Gate Delay Models
• Net Delay Models

4. 3/3/2023
Static
Timing
Analysis
• What you know
• Logic synthesis
• How to simulate the design to verify what it does
• What you don’t know
• Verify the timing behaviour of given synthesized design
• Timing Analysis
• We have gate level netlist
• Some timing information of gates and wires are
given
• We need to tell
• When signal arrives in various points in the
network
• Shortest and longest delays through network
• Does netlist meets timing requirements?

5. 3/3/2023
Static
Timing
Analysis
Objective of Timing Analysis
Timing verification
• Verifies whether a design meets a given timing
constraint
• Verifies that the design work properly for all possible
combination “EVERY TIME”
Timing optimization
• Needs to identify critical portion of a design for
further optimization
• Critical path identification
• Like component selection
• A slow memory can degrade processor
performance
In both applications, the more accurate, the better

6. 3/3/2023
Static
Timing
Analysis
Types of Timing Analysis
• Dynamic Timing Analysis
• Verifies the functionality of design by
applying input vectors and checking the
correctness and timing of output vectors
• Static Timing Analysis
• Checks static delay requirements without
applying any vectors
• It does not check functionality

7. 3/3/2023
Static
Timing
Analysis
Dynamic Timing Analysis
• Requires too many patterns, exponential in
the number of design inputs
• Even worse, if we consider the sequence need
to initialize the latches
• It does not find all the errors, because it is
pattern dependent. It can only check the
timing paths sensitized by the input pattern.
If the patterns do not cause an error to occur,
the error is not detected.
• Can be very accurate (spice-level)
• Analysis quality depends on stimulus vectors
• Non-exhaustive, slow

8. 3/3/2023
Static
Timing
Analysis
Then What to do?
• Separate function from timing
• Determine when transition occurred
without worrying about how?
• Instead of considering infinite long
simulation sequence, fold all possible
transitions back into a single clock cycles
• Assume that signal gets stable at latest
possible time and unstable at earliest
possible time.
• If the design works at these extremes, it can
be guaranteed that it will always work safely
• Do it static means do not simulate.

9. 3/3/2023
Static
Timing
Analysis
Static Timing Analysis
• It is a method of validating the timing
performance of a design by checking all
possible paths from timing violations under
worst case conditions
• It considers worst logical delay through each
logic element but not the logical operation of
the circuit.
• Input independent method So no vector
generation is required.
• It does not check the functionality

10. 3/3/2023
Static
Timing
Analysis
Static Time Analysis
What it typically does:
• Calculate latest and earliest possible switching
times for each node in the design
• Determine the arrival time of signals for the
worst case (latest or earliest) of all possible
paths leading to a given node in the design
• Compare calculated signal arrival times with
expected (required) arrival times at storage
elements, other clock meets data points (such
as dynamic circuits) and primary outputs in
the design.

11. 3/3/2023
Static
Timing
Analysis
STA….
• Much faster than timing driven gate level simulation
(dynamic).
• There are huge number of logic paths inside a chip of
complex design and STA calculates delay for all possible
paths whether they are real or potential false path. So it
is exhaustive in nature.
• False paths need to be handled separately.
• It is not suitable for all design styles. Proven efficient for
synchronous design only but most of the designs are
synchronous so it is there in mainstream. Asynchronous
designs need separate attention.
• It is pessimistic and hence less accurate
• Conservative analysis. Calculates upper bound on
frequency but guarantees that the design will function
at least as fast as predicted.

12. 3/3/2023
Static
Timing
Analysis
Static Timing Analysis
• Consider all paths
• Does not checks
circuit functionality
• Reports False Paths
• Pessimism by
considering false paths
which are never
exercised
• Not so accurate
• Fast
Dynamic Timing
Analysis
• Depends on input
stimulus vectors
• Checks circuit
functionality
• Does not report
timing on false paths
• By large number of
testing vectors
• Accurate
• Slow

13. 3/3/2023
Static
Timing
Analysis
• Multiple clocks
• False paths: Proper circuit functionality is not checked
• Latches
• Multicycle paths
◼ Works best with synchronous (not asynchronous) logic
◼ Complex to learn
◼ Must define timing requirements / exceptions
◼ Difficulty in handling:
Limitations of STA

14. 3/3/2023
Static
Timing
Analysis
Delay/Time Calculation for a design
• The total delay of a path is the sum of all
• Gate/Cell Delays in the path
• Net /Path Delays in the path

15. 3/3/2023
Static
Timing
Analysis
Gate/Cell Delays
• Timing Delay between input pin and output pin of a
logic gate/cell in a path
• The cell delay information is contained in the library of
the cell e.g. .lef file
• In ASICs, the delay of a cell is affected by:
• The input transition time (or slew rate)
• The total load “seen” by the output transistors
• Net capacitance and “downstream” pin
capacitances
• These will affect how quickly the input and output
transistors can “switch”
• Inherent transistor delays and “internal” net delays

16. 3/3/2023
Static
Timing
Analysis
Definition of Delays for Cell

17. 3/3/2023
Static
Timing
Analysis
Gate Delay Models
Unit Delay Model
• Simplest
• Each gate with unit delay
• Longest path delay = 2
Arbitrary but Fixed Delay
Model
• Simple
• Each gate with some
constant delay which does
not depend on circuit or
netlist

18. 3/3/2023
Static
Timing
Analysis
Limitations of Fixed Delay Model
• Fanouts
• Loading effect on transistors inside gates
• Gates with more fanouts are slower than gates with
less fanouts

19. 3/3/2023
Static
Timing
Analysis
Limitation of Fixed Delay Model
Input Waveform
• Slop of the input waveform also affects delay (RC
affects)
• Rising signal vs Falling signal also affects

20. 3/3/2023
Static
Timing
Analysis
Limitations of Fixed Delay Model
• Location of pins
• Delay is not actually
through a gate
• but it is actually from
individual input pin to
output
•

21. 3/3/2023
Static
Timing
Analysis
Limitation of Fixed Delay Model
• Rising and Falling
Waveforms
• pMOS has larger delay
compared to nMOS.
• Rising and falling delay for
output may be different
• More complicated for Non-
Monotonic functions

22. 3/3/2023
Static
Timing
Analysis
Limitation of Fixed Delay Model
• Process Variation
• Delay in its real sense, is a probability distribution function.
• Simplest way to express is in [min, max]

23. 3/3/2023
Static
Timing
Analysis
Limitation :
Voltage and Temperature Dependency
• Example of 74 series NAND2

24. 3/3/2023
Static
Timing
Analysis
Net/ Wire Delays
• Net delay is the difference between the time
a signal is first applied to the net and the
time it reaches other devices connected to
that net.
Wire delay = function of (Rnet, Cnet+Cpin)
• Total net delays are affected by:
• Characteristics of driver cell and receiver cell
• net material, length and cross sectional are
• net fanout
• Number of vias traversed by the net
• Proximity to other nets (crosstalk)
• The effects of Interconnect Parasitic
• Interconnect parasites cause an increase in propagation
delay (i.e. it slows down working speed)

25. 3/3/2023
Static
Timing
Analysis
Lumped Capacitor Model
• As long as the resistive component of the
wire is small, and switching frequencies are
in the low to medium range, it is meaningful
to consider only the capacitive component of
the wire, and to lump the distributed
capacitance into a single capacitance.

26. 3/3/2023
Static
Timing
Analysis
Lumped RC Model
• If wire length is more than a few millimeters,
the lumped capacitance model is inadequate
and a resistive capacitive model has to be
adopted.
• In lumped RC model the total resistance of each
wire segment is lumped into one single R,
combines the global capacitive into single
capacitor C.
• Analysis of network with larger number of R
and C becomes complex as network contains
many time constants (zeroes and poles).

27. 3/3/2023
Static
Timing
Analysis
Distributed RC Model
• Lumped RC model is always pessimistic and
distributed RC model provides better accuracy
over lumped RC model.
But distributed RC model is complex and no
closed form solution exists. Hence distributed
RC line model is not suitable for Computer
Aided Design Tools.
The behavior of the distributed RC line can be
approximated by a lumped RC ladder network
such as Elmore Delay model hence these are
extensively used in EDA tools.

28. 3/3/2023
Static
Timing
Analysis
Elmore Delay Model
• Resistance Oriented Formula
,
T R C
delay i downstream i
=

Tdelay,4=R1(C1+C2+C3+C4+C5)+R2(C2+C4+C5)+R4C4

29. STA for Combinational Circuit
Prof. Usha Mehta
Professor,
PG-VLSI Design,
EC, Institute of Technology,
Nirma University, Ahmedabad
usha.mehta@nirmauni.ac.in
usha.mehta@ieee.org

30. 3/3/2023
Static
Timing
Analysis
Timing in Combinational Circuit
• The combinational Circuit can be
characterized by:
• Propagation Delay tpd: Maximum Delay
• Contamination Delay tcd : Minimum Delay
• Glitches

31. 3/3/2023
Static
Timing
Analysis
Propagation Delay and
Contamination Delay

32. 3/3/2023
Static
Timing
Analysis
Calculation of Long/short paths
• For combinational circuit, we care about
both: longest and shortest delay path.
• (Why both? : we will understand it during set-up and hold
time violation.)

33. 3/3/2023
Static
Timing
Analysis
Two different implementation of 4X1 MUX

34. 3/3/2023
Static
Timing
Analysis
STA for Combinational Circuit
• Combinational circuits: Graph model:
• DAG: Directed Acyclic Graph
• Vertices:
• I/O pins of gates
• s and t ( start and stop points)
• Edges:
• Connect each input of a gate to its output
• Show maximum delay paths from the input pin
to the output pin
• Connects the output of each gate to the inputs of
its fanout gates
• Show interconnect delays
• In case of combinational loop:
• Many STA tools break the loop and analyze

35. 3/3/2023
Static
Timing
Analysis
Combinational Circuit Representation
: Gate delays only

36. 3/3/2023
Static
Timing
Analysis
Combinational Circuit Representation
: Gate delays and net delay

37. 3/3/2023
Static
Timing
Analysis
• Add one source to each PI and one sink
node to each PO with 0 – weight edge
• If arrival time of different inputs are different, then the weight
of source edge can represent that delay also.
• For network/algorithm has one clear entry
point and exit point.
• Search algorithms
• Depth First Search Algorithm is most suited to
list all the different possible paths
• Let’s try
Combinational Circuit Representation
: Gate delays, net delay and source & Sink node

38. 3/3/2023
Static
Timing
Analysis
STA for Combinational Circuits
Critical Path
➢ Critical path
➢Any logical path in the design that violates the timing constraints
➢The slowest path on the chip between flops or flops and pins.
The critical path limits the maximum clock speed.
➢The longest path on a DAG graph

39. 3/3/2023
Static
Timing
Analysis
Find the Critical path
Gate Delay
Not 2
AND 4
OR 4

40. 3/3/2023
Static
Timing
Analysis
Gate Delay
Not 2
AND 4
OR 4

41. 3/3/2023
Static
Timing
Analysis
Find the critical path ….

42. 3/3/2023
Static
Timing
Analysis
Find the critical Path…..
8
1
MUX
12
8
1
MUX
12

43. 3/3/2023
Static
Timing
Analysis
False Path
• Paths that physically exist in a design but are not
logic/functional paths
• These paths never get sensitized under any input
conditions

44. 3/3/2023
Static
Timing
Analysis
Logically Impossible Example
Mux 1
C C1 C2
A
B
Mux 2
S
B1 B2
OUT
•A path may exist in the circuit but no combination of input vectors may
ever exercise it
d = 10
d = 20
d = 10
d = 20

45. 3/3/2023
Static
Timing
Analysis
False Path Solutions
• Solutions:
• Automatic solutions: too complex to be practical
• E.g. if inverter delay > 0
• In practice:
• Designers knows functionalities best →
Designer specifies

46. 3/3/2023
Static
Timing
Analysis
Home work
• Algorithm to find the longest path in DAG
using tcl/tk

47. 3/3/2023
Static
Timing
Analysis
Glitch :
• For below circuit, draw the output waveform for
A moves 0 to 1 at 5 ns if no delays in gate?
• What if AND gate has 3ns delay and NOT gate
is 2 ns delay?

48. 3/3/2023
Static
Timing
Analysis
Glitches
• Glitch: one input transition causes multiple output transitions

49. 3/3/2023
Static
Timing
Analysis
Glitches

50. 3/3/2023
Static
Timing
Analysis
Avoiding glitches using K-map
• Glitches are visible in K map:

51. 3/3/2023
Static
Timing
Analysis
Fixing the Glitch
• The glitch can be fixed by adding the
consensus term.

52. 3/3/2023
Static
Timing
Analysis
Homework
• For the given circuit draw the output wave form
if A=1, D=1 and B moves from 1 to 0 at t=5ns
and again moves to 1 at t=10ns.
• What is the difference in waveform if you
assume all gates without any delay and if all
gates have delay of 3ns?
A
B
D
Q

53. 3/3/2023
Static
Timing
Analysis
Hazards in Combinational Networks
• Eg. Q = AB’ + BD if B & D are 1 then Q
should be 1 but because of propagation
delays, if B changes state then Q will
become unstable for a short time, as follows:
A
B
D
Q
(C)
A
D
B
(C)
Q
High
High
glitch

54. 3/3/2023
Static
Timing
Analysis
• What is the difference in waveform if the tPLH
= 1ns and tPHL=2ns ?

55. 3/3/2023
Static
Timing
Analysis
Hazards/Glitches
• Hazards/glitches: unwanted switching at
the outputs
• Occur when different paths through circuit have different
propagation delays
• Dangerous if logic causes an action while output is unstable
• May need to guarantee absence of glitches

56. 3/3/2023
Static
Timing
Analysis
Types of Hazards
• Static 1-hazard
• Input change causes output to go from 1 to 0 to 1
• Static 0-hazard
• Input change causes output to go from 0 to 1 to 0
• Dynamic hazards
• Input change causes a double change
from 0 to 1 to 0 to 1 OR from 1 to 0 to 1 to 0
1
0 0
1 1
0 0
1 1
0 0
0
1 1

57. 3/3/2023
Static
Timing
Analysis
Static Hazards
STATIC-0
Output unnecessary
goes to 1
In Product-of-Sum
functions
In two level OR-AND
circuit
Every pair of adjacent
0 should be covered by
a 0-term
STATIC-1
Output unnecessary
goes to 0
In Sum-of-Product
functions
In two level AND-OR
circuit
Every pair of adjacent 1
should be covered by a
1-term

58. 3/3/2023
Static
Timing
Analysis
Elimination of Static-1Hazard
• In two level AND-OR circuit only

59. 3/3/2023
Static
Timing
Analysis
Elimination of Static-0 Hazard
• In two level OR_AND circuit only

60. 3/3/2023
Static
Timing
Analysis
• Design a Hazard free combinational circuit
for following function
F=∏M((0,1,2,3,4,5,9,10,11,13)

61. 3/3/2023
Static
Timing
Analysis
• Design a hazard free combinational logic
circuit to implement the following logic
function
F = A’∙C’ +A∙D +B∙C∙D’

62. 3/3/2023
Static
Timing
Analysis
Dynamic Hazards
• Dynamic Hazards are the consequence of
multiple static hazards caused by multiple
reconvergent paths in a multilevel circuit.
• Dynamic hazards are not easy to eliminate
• Elimination of each individual static hazard
will eliminate dynamic hazard.
• Approach: Transform a multilevel circuit
into a two level circuit and eliminate all
hazards

63. 3/3/2023
Static
Timing
Analysis
Dynamic Hazard

64. 3/3/2023
Static
Timing
Analysis
Eliminating Dynamic Hazards

65. 3/3/2023
Static
Timing
Analysis
Functional Hazard
• Function hazards are non-solvable hazards
which occurs when more than one input
variable changes at the same time.
• Hazards such as function hazards can not be
logically eliminated as the problem lies with
actual specification of the circuit.
• The only real way to avoid such problems is to
restrict the changing of input variables so that
only one input should change at any given time.
• Restrictions are not always possible,
• E.g.One input is used for a clock signal, and the other is
connected to a random noise source that we wish to measure.

66. 3/3/2023
Static
Timing
Analysis
Example of Function Hazard
• let us imagine that some circuit designer
has split this function across different chips
(i.e. one NOT gate on one chip and the other
NOT gate is implemented on another chip
across the PCB somewhere)

67. 3/3/2023
Static
Timing
Analysis
Solutions for Hazards
• Usual solutions
• 1) Wait until signals are stable (by using a clock): preferable
(easiest to design when there is a clock – synchronous design)
• 2) Design hazard-free circuits

68. 3/3/2023
Static
Timing
Analysis
Why do we care about Hazards?
• Combinational Networks
• Don’t care, the network will function properly
• Synchronous Sequential Networks
• Don’t care, the input signals must be stable within set-up
and hold time
• Asynchronous Sequential Networks
• Hazards can cause networks to enter in incorrect state
• Power Consumption

69. 3/3/2023
Static
Timing
Analysis
• Do we always care about glitches?
•Fixing glitches:
• More chip area
• More power consumption
• More design efforts
• If the application needs long term steady
state output, glitches can be safely ignored.

70. STA for Clocked Design
Concepts of Timing Path, Clock Skew and Slack
Prof. Usha Mehta
Professor,
PG-VLSI Design,
EC, Institute of Technology,
Nirma University, Ahmedabad
usha.mehta@nirmauni.ac.in
usha.mehta@ieee.org

71. 3/3/2023
Static
Timing
Analysis
STA for Clocked Design
• Consider an arbitrary signal in clocked
design
• Takes on a value every cycle either one or zero
• Specific time of change depends on pattern causing it
• May not change at all in some cycle
• May make multiple changes before settling to a value.

72. 3/3/2023
Static
Timing
Analysis
STA for Clocked Design
• Sequential circuit is Represented as: a set of combinational
blocks that lie between latches/flipflops.
• Transparent Latch, Level Sensitive
• data passes through when clock high, latched when clock low
• D-Type Register or Flip-Flop, Edge-Triggered
• data captured on rising edge of clock, held for rest of cycle

73. 3/3/2023
Static
Timing
Analysis
• For Flipflop,
• there is only one propagation delay,
clock to Q delay
• tclk->Q
• But do remember, for the
latch,
• there are two propagation delays
• tclk->Q and tD->Q
STA for Clocked Design

74. 3/3/2023
Static
Timing
Analysis
Three steps in STA
1. Circuit is broken down into sets of timing
paths
2. Delay of each path is calculated
3. Path delays are checked to see if timing
constraints have been met

75. 3/3/2023
Static
Timing
Analysis
What is Timing Paths?
A Timing paths is a point-to-point path in a design which can propagate data
from one flip to another
• STA tool checks all paths from each and every start point to each and every
end point and compares it against the constrains that should exist for the
path.
• Most of the paths are constrained by the definition of the period of the clock
and the timing characteristics of the input and outputs of the circuit.
❑ Each path has a Startpoint , Combinational logic network and Endpoint
➢Startpoint : Start of a Timing path where data is launch by clock edge. It
must be input port or register clock pin.
➢Combinational logic network : Element that have no memory or internal
state.
➢Endpoint : End of a Timing path where data is capture by clock edge. It
must be a register input data pin or an output port.

76. 3/3/2023
Static
Timing
Analysis
Types of Path
• Data Path
• Clock Path
• Clock Gating Path
• Asynchronous Path
• Exceptions in STA:
• False Path
• Multicycle Path

77. 3/3/2023
Static
Timing
Analysis
Data path
• Start Point :
• input port of the design
• clock pin of the flipflop
• End Point:
• outport of the design
• data input pin of the flipflop

78. 3/3/2023
Static
Timing
Analysis
Clock Path
• Start Point
• Clock input port
• End Point
• Clock pin of the flipflop/latch/memory

79. 3/3/2023
Static
Timing
Analysis
Asynchronous Path
• Start Point
• Input port of the design
• End Point
• Set/reset/clear pin of the flipflop/latch/memory

80. 3/3/2023
Static
Timing
Analysis
Clock Gating Path
• Start Point
• Input port of the design
• End Point
• Input port of the clock gating element

81. 3/3/2023
Static
Timing
Analysis
Single Cycle and Multicycle Paths
• Single Cycle Path : It is a timing path that is
designed to take only one clock cycle for the
data to propagate from the start point to
end point.
• Multi Cycle Path

82. 3/3/2023
Static
Timing
Analysis
Launch Path and Capture Path
• Launch flipflop and Capture flipflop
• Launch Path : It is part of clock path which is responsible foe launching the data
at launch flipflop
• Capture Path : It is part of clock path which is responsible foe launching the data
at capture flipflop
• Launch path and data path together constitute arrival time of data at the input of
capture flipflop
• Capture clock period and its path delay together constitute required time of data
at the input of the capture register.

83. 3/3/2023
Static
Timing
Analysis
Specifying Clocks
•Standard clock
•Inverted clock
•Derived clock
•A design might include clock dividers or other
structures that produce a new clock from a
master source clock.
•Gated clock
•Clock gating reduces power consumption by
switching off the clock to flip-flops when the
value of those flip-flops does not change.
•Virtual clock
•A clock that is not physically present, do not
require any source
•Can be initiated by commands in STA Tools

84. 3/3/2023
Static
Timing
Analysis
What is Virtual Clock? Why it is
required?
• A imaginary clock created by syntax. Do not
require any generator
• For paths going through a primary input
port, the tool needs to know the frequency of
the clock driving the signal in order to
create a proper timing path. Similarly for
output ports, the tool needs to know the
frequency of the flop capturing the signal.
The virtual clock defines the relationship to
paths going through IO ports.

85. 3/3/2023
Static
Timing
Analysis
Why virtual clock?
• To check the timing of OUT, we create virtual
clock which represent FF2.
• We can not use clk_real for this as there is no
next/capture FF for output path otherwise the
analysis will be pessimistic for setup time and
optimistic for hold time since the capture clock
delay is not there at all.

86. 3/3/2023
Static
Timing
Analysis
Maximum Clock Frequency
• A clock is defined by its period, waveform and slew time.
• The clock frequency for a synchronous sequential circuit is
limited by the timing parameters of its flip-flops and gates.
• The critical path/worst path having the maximum delay
defines the clock frequency of the circuit.
• The minimum clock time period ( reciprocal of maximum clock
frequency) should be equal to or more than maximum time
delay of the longest path of the circuit.

87. 3/3/2023
Static
Timing
Analysis
Your chip
clock input
Flip
Flop
Time from clock input (at pin) to
clock input at a given flip flop
Absolute Clock Skew / Latency

88. 3/3/2023
Static
Timing
Analysis
Relative Clock Skew
Your chip
clock input
Flip
Flop
Time between 2 flip flops receiving
the clock signal
Flip
Flop
delay

89. 3/3/2023
Static
Timing
Analysis
Clock Skew
➢ Ideally clock skew should be zero. i.e. clock should reach to
each flipflop at the same instant.
➢ Clock Skew is a measure of the difference in latency between
any two leaf pins in a clock tree.
Clock arrival
time at 1.1ns
Clock arrival
time at 1.3ns
Skew = 1.3ns - 1.1ns = .2ns

90. 3/3/2023
Static
Timing
Analysis
Clock Skew and Clock Latency
• The arrival time of a flip-flop's clock pin is its clock latency. The clock
skew between two flip-flops is the difference of their clock latency.
Chip
D Q D Q D Q D Q
network latency
(on-chip)
source latency
(off-chip)
Clock
IO
latency
IO
latency

91. 3/3/2023
Static
Timing
Analysis
Clock Latency
• Difference between the reference (source )
clock skew to the clock tree endpoint signal
skew values.
• Rise latency and Fall latency are specified.
INV
Rise=7
Fall=4
Rise=7
Fall=4
Rise=7
Fall=4
Rise=7
Fall=4
Rise=7
Fall=4
Rise=7
Fall=4
Rise=7
Fall=4
CLK
CLKA
CLKB
CLKC
I
N
V
I
N
V
I
N
V
I
N
V
I
N
V
B
U
F
B
U
F
CLK to CLKA :
Min Latency rise
= 4+7+4+7 = 22 (Max)
Min Latency fall
=7+4+7+4 = 22
CLK to CLKB :
Min Latency rise = 4+4
= 8
Min Latency fall = 7+7 =
14
CLK to CLKC :
Min Latency rise = 7
Min Latency fall = 4 (min)
Average = (22+22+8+14+7+4) / 6 = 12.83

92. 3/3/2023
Static
Timing
Analysis
Clock Skew
• Clock skew is a measure of the difference in latency
between any two leaf pin in a clock tree.
➢Between CLKA and CLKB
rise = 22 - 8 = 14
fall = 22 -14 = 8
➢Between CLKB and CLKC
rise = 8 -7 = 1
fall = 14 - 4 = 10
➢Between CLKC and CLKA
rise = 22 - 7 = 15
fall = 22 - 4 = 18
It is also defined as the difference in time that a single
clock signal takes to reach two different registers

93. 3/3/2023
Static
Timing
Analysis
Arrival time (w.r.t input) and Required
time ( w.r.t. output)/Capturing moment
• An arrival time defines the time interval
during which a data signal can arrive at an
input pin in relation to the nearest edge of
the clock signal that triggers the data
transition.
• A required time specifies the data required
time on output ports

94. 3/3/2023
Static
Timing
Analysis
Slack
• It is difference between required time and arrival time.
• If required time > arrival time
• Positive slack
• indicates that constraints have been met.
• If required time < arrival time
• Negative slack
• indicates that constraints have not been met
• Set up/Hold violation
• Slack analysis is used to identify timing critical paths in a design
by static timing analysis tool.

95. 3/3/2023
Static
Timing
Analysis
Sequential False Path example:
• The change in D1-Q never reaches to D4-D.
The value of D4 is always governed by D2.
So clk-D1-AND-OR-D4 is false path.

96. 3/3/2023
Static
Timing
Analysis
Slack
• It is difference between required time and arrival time.
• If required time > arrival time
• Positive slack
• indicates that constraints have been met.
• If required time < arrival time
• Negative slack
• indicates that constraints have not been met
• Set up/Hold violation
• Slack analysis is used to identify timing critical paths in a design
by static timing analysis tool.
96

97. 3/3/2023
Static
Timing
Analysis
Sequential False Path example:
97
• The change in D1-Q never reaches to D4-D.
The value of D4 is always governed by D2.
So clk-D1-AND-OR-D4 is false path.

98. Set-up and Hold Time
Violation
Prof. Usha Mehta
Professor,
PG-VLSI Design,
EC, Institute of Technology,
Nirma University, Ahmedabad
usha.mehta@nirmauni.ac.in
usha.mehta@ieee.org

99. 3/3/2023
Static
Timing
Analysis
Considering the delays….
1. Ideal Condition no delay in any path.
2. Data and Clock path have fixed delays but
no set-up/Hold time for FFs
3. Data and Clock path have fixed delays and
FFs are with set-up/Hold time
4. Data and Clock path have delays, FFs are
with set-up/Hold time ( all delays with min-
max range, not fixed)
99

100. 3/3/2023
Static
Timing
Analysis
Ideal Condition: No delays
100

101. 3/3/2023
Static
Timing
Analysis
Ideal Condition:
Launching,
arrival and
capture moments
101

102. 3/3/2023
Static
Timing
Analysis
Delays in Data and Clock Path
102
• Clock path delay tB2 is time difference of clock
reaching at D1 and D2. It is also know as clock
skew
• The interview questions mostly refer clock path
delay as clock skew.

103. 3/3/2023
Static
Timing
Analysis
Delays in Data Path and Clock Path
contd…
103

104. 3/3/2023
Static
Timing
Analysis
Conditions for
Timings
104

105. 3/3/2023
Static
Timing
Analysis
Positive and Negative Clock Skew
• While all discussion, don’t forget that the
clock skew can be positive as well as
negative also.
105

106. 3/3/2023
Static
Timing
Analysis
Set up Time and Hold Time
• Set up Time
• For an edge triggered sequential element, the setup time is
the time interval before the active clock edge during which
the data should remain unchanged.
• This is so that the data can be stored successfully in storage
device
• Because of Long path
• Hold Time
• Time interval after the active clock edge during which the
data should remain unchanged. This is so that the data can
be stored successfully in storage device
• Because of Short Path
106

107. 3/3/2023
Static
Timing
Analysis
Setup Time and Hold Time Consideration
107

108. 3/3/2023
Static
Timing
Analysis
Setup and Hold
Time consideration
contd….
108

109. 3/3/2023
Static
Timing
Analysis
When delays are given in min-max
limits
109

110. 3/3/2023
Static
Timing
Analysis
Set-up Time Violation
110

111. 3/3/2023
Static
Timing
Analysis
Hold Time Violation
111

112. 3/3/2023
Static
Timing
Analysis
Relation between data path delay, clock
path delay, Set-up/Hold and Clock Time
Period…
1. The circuit is given with all delays ( net,
cell, Set-up, hold etc..)
• you are required to calculate the
minimum time period (maximum
frequency) of clock.
2. The circuit is given with all delays ( net,
cell, Set-up, hold etc..) and minimum time
period (maximum frequency) of clock at
which circuit will operate.
• You are required to verify whether any timing
violation exists or not.
112

113. 3/3/2023
Static
Timing
Analysis
Clock Skew and Set-up and Hold
Time Violations
• Positive clock skews are good for fixing setup
violations, but can cause hold violations.
• Negative clock skew can guard against a hold
violation, but can cause a setup violation 113

114. 3/3/2023
Static
Timing
Analysis
Race Hazards
• Race hazard is where data arrives too early at the D
input of a flip-flop allowing the data to pass through one
cycle too early.
• For given waveform, the data D2 sampled at F1 @1
should reach to F2 after @2 and before @4 but if the
delay of combinational path is less than it reaches
before @2 causing the loss of D1. This is called Race
Hazard
114

115. 3/3/2023
Static
Timing
Analysis
Clock Skew and Racing Hazards
• Increase in clock skew means more difference
between @1 and @2.
• Increase in clock skew increases the chances
of racing hazards.
• Also note that reduction in clock frequency
will not solve racing hazards
115

116. 3/3/2023
Static
Timing
Analysis
Calculate the max. clock frequency
for given circuit…
• Minimum Time Period = tclk-q + tpd + ts = 10 + 5 +2 =
17ns
116

117. 3/3/2023
Static
Timing
Analysis
117
TAB = 11ns, TAC = 15ns , TBC = 16ns.
Minimum clock period =16ns
Calculate the max. clock frequency
for given circuit…

118. 3/3/2023
Static
Timing
Analysis
118
Tclk-Q = 10 ns, NOR/OR = 4 ns, NAND/AND =3 ns,
INV/BUF = 2ns, Ts = 2 ns, Th = 3ns
Calculate the max. clock frequency
for given circuit…

119. 3/3/2023
Static
Timing
Analysis
119
For a minimum clock period, we just want that the data reach ts time
before the clock reach there.
Data path
• Max delay = 26ns
• Min delay = 18ns
Clock Path
• Max delay = 15ns
• Min delay=9ns
Minimum Clock Period = 26 -9 +4 = 21 ns
Calculate the max. clock frequency
for given circuit…

120. 3/3/2023
Static
Timing
Analysis
Find out any set-up violation ?
• For set-up path
• Set-up is checked at next clock cycle
• Maximum delay along the data path
• Minimum delay along the clock path
• Data path is
• CLK->FF1/CLK->FF1/Q->INV->FF2/D
• TD =2ns +11ns+2ns+9ns+2ns = 26ns ( max. delay in data path)
• Clock Path is
• CLK-> BUFF->FF2/CLK
• TCLK= 15 ns + 2ns+5ns+2ns-4ns = 20ns (max. delay in clock
path)
• SET-UP SLACK = TCLK-TD
• 20-26= -6ns < 0 so Set-Up Violation
120
CLK Period = 15ns

121. 3/3/2023
Static
Timing
Analysis
Find out any hold violation?
• For hold path
• Hold is checked at Same clock cycle
• Minimum delay along the data path
• Maximum delay along the clock path
• Data path is
• CLK->FF1/CLK->FF1/Q->INV->FF2/D
• TD =1ns +9ns+1ns+6ns+1ns = 18ns ( min. delay in data path)
• Clock Path is
• CLK-> BUFF->FF2/CLK
• TCLK= 3ns+9ns+3ns+2ns = 17ns (max. delay in clock path)
• SLACK = TD-TCLK
• 18-17=1ns > 0 so No Hold Violation 121

122. 3/3/2023
Static
Timing
Analysis
Fixing Set-up /Hold Violation
:Combinational Delay
• Check for violations
• Data1 reaches to FF2 at 0.5 ns. It should reach before 10 ns – 2ns i.e
8ns Hence, NO set-up violation
• Data2 launched at 10 ns, reaches to FF2 at 10.5 ns. It disturbs the
data1 which should be there upto 11ns. So hold violation.
• To remove hold violation, let’s increase the combinational delay.
Let’s say by 3ns. Then data1 reaches at 3ns which is before 8ns so
still no problem with set-up time and data2 reaches at 13ns so hold
time violation is also solved.
• But what if we increase combination delay to 9ns? Here, while
solving for hold-time, we have violated setup time.
122

123. 3/3/2023
Static
Timing
Analysis
123
Fixing Set-up /Hold Violation
• Check for violations

124. 3/3/2023
Static
Timing
Analysis
Timing Closure
• It is the process of satisfying timing constraints
through layout optimizations and netlist
modifications
• Timing-driven placement: minimizes signal
delays when assigning locations to circuit
elements
• Timing-driven routing : minimizes signal delays
when selecting routing topologies and specific
routes
• Physical synthesis: improves timing by
changing the netlist
• Sizing transistors or gates: increasing the width:length ratio of
transistors to decrease the delay or increase the drive strength
of a gate
• Inserting buffers into nets to decrease propagation delays
• Restructuring the circuit along its critical paths
124

125. 3/3/2023
Static
Timing
Analysis
Ways to fix set-up Violation
(Tdata <= Tclk-Tsetup)
1. Reduce the amount of buffering in the path.
✓ It will reduce the cell delay but increase the wire delay. So if effective
delay is reduced than, set-up time violation can be fixed.
2. Replace buffer with two inverters place farther apart
✓ Delay of one buffer is equal to delay of two inverter but because of two
inverters, the transition delays are reduced.
3. Change HVT cells to SVT/LVT to reduce delay
✓ HVT/SVT/LVT has the same size and pin position so this change will
reduce delay without affecting layout.
4. Increase driver size i.e. driver strength
✓ It reduces delay
5. Insert Buffer/repeaters
✓ In case of long wire, the buffer decreases the transition time which
decreases wire delay. If decrease in wire delay is more compared to buffer
delay, overall delay reduces.
125

126. 3/3/2023
Static
Timing
Analysis
Ways to fix set-up Violation
(Tdata <= Tclk-Tsetup) cont…..
6. Adjust Cell position in layout
7. Clock Skew
✓ By delaying clock to the end point.
126

127. 3/3/2023
Static
Timing
Analysis
Ways to fix hold time violation…
Tdata >= Thold
1. By adding delay
✓ The hold violation path may have its start or stop point in
other setup violation path
2. Decreasing the size of cells in data path
127

128. 3/3/2023
Static
Timing
Analysis
Negative Set-up and Hold Time
• For a Pure flop(containing no extra gates) setup
and hold time always will be a positive number.
• Now, A flop can be a part of a bigger
component. There are many components
available in stranded cell library that embed a
flop inside. These components will be a part of
our design.
• Setup and hold time can be negative depending
on where you measure the setup and hold time,
if you measure setup and hold time at
component level. These can be negative also.
128

129. 3/3/2023
Static
Timing
Analysis
Negative Set-up and Hold Time
• For pure flipflop
• Tdata < Tclk-Tsetup
• Tdata > Thold
129
Flipflop
(Pure)
Tdata
Tclk
Tsetup Thold

130. 3/3/2023
Static
Timing
Analysis
Negative Set-up and Hold Time
130
Flipflop
(Embedded)
Tdata
Tclk_comp
Tsetup
Thold
Tdata_delay
Tclk_delay
Tcomp_setup Tcomp_hold

131. 3/3/2023
Static
Timing
Analysis
Negative Set-Up Time
• The time when data reaches to flipflop = Tdataflipflop = Tdata+Tdata_delay
• The time when clock reaches to flipflop = Tclkflipflop = Tclk_comp+Tclk_delay
• Considering flipflop, Tdata+Tdata_delay < Tclk_comp+Tclock_delay-Tsetup
• If Tdata_delay= 700, Tclk_delay = 800 and Tsetup=200
• Tdata+700 <= Tclk_comp + 800-200
• Tdata <= Tclk_comp-100
• Tcomp_setup is 100
• But If Tdata_delay= 500, Tclk_delay = 800 and Tffsetup=200
• Tdata+500 <= Tclk_comp+800-200
• Tdata <= Tclk_comp + 100
• Tcomp_setup is negative i.e. -100
131
For Component, Tdata < Tclk_comp-Tcomp_setup

132. 3/3/2023
Static
Timing
Analysis
Negative Hold Time
• The time when data reaches to flipflop = Tdataflipflop = Tdata+Tdata_delay
• The time when clock reaches to flipflop = Tclkflipflop = Tclk_comp+Tclk_delay
• Tdata+Tdata_delay >= Thold
• If Tdata_delay= 100, and Thold=200
• Tdata+100 >= 200
• Tdata >= 100
• Tcomp_hold is 100
• If Tdata_delay= 300 and Thold=200
• Tdata+300 >= 200
• Tdata >= -100
• Tcomp_hold is negative i.e. -100
132
For Component Tdata > Tcomp_hold

133. 3/3/2023
Static
Timing
Analysis
Can Pipelining help?
• Delay of Adder + Absolute + log
133

134. 3/3/2023
Static
Timing
Analysis
Clock Frequency for Pipeline Design
• 𝑇min 𝑝𝑖𝑝𝑒 = 𝑇𝑟𝑒𝑔 + 𝑚𝑎𝑥 𝑇𝑝_𝑎𝑑𝑑𝑒𝑟, 𝑇𝑝_𝑎𝑏𝑠, 𝑇𝑝_𝑙𝑜𝑔 +
𝑆𝑒𝑡_𝑢𝑝𝑟𝑒𝑔
• Pipelining is used to implement high-
performance data-paths
• # Adding extra pipeline stages only makes
sense up to a certain point 134

135. 3/3/2023
Static
Timing
Analysis
Time Borrowing/ Cycle Stealing
• Technique of borrowing the time from shorter
path of the logic stage to the longer path
• Do remember:
• Edge triggered flipflop changes the stage at the clock edges So
the delay of a combination logic path in a design using such FFs
can not be longer than the clock period of the design ( except for
false or multicycle path)
• While the latch can change the stage as long as clock pin is
enabled. Here, the delay of the longest path can be compensated
by the delay of the shortest path in subsequent logic design
• Hence latch based design can be faster.
135

136. 3/3/2023
Static
Timing
Analysis
Example of Time Borrowing
136

137. 3/3/2023
Static
Timing
Analysis
STA in ASIC Design Flow – Pre layout
137
Logic Synthesis
Design For test
Floor planning
Constraints
(clocks, input drive,
output load)
Static Timing Analysis
Static Timing Analysis
(estimated parasitics)

138. 3/3/2023
Static
Timing
Analysis
STA in ASIC Design Flow – Post Layout
138
Floor planning
Clock Tree Synthesis
Place and Route
Parasitic Extraction
SDF
(extracted parasitics)
Constraints
(clocks, input drive,
output load)
Static Timing Analysis
(estimated parasitics)
Static Timing Analysis
(extracted parasitics)

139. 3/3/2023
Static
Timing
Analysis
Required Inputs
139

140. 3/3/2023
Static
Timing
Analysis
Back Annotation – A process
1. Designer writes the RTL and performs functional simulation
considering delay as zero or some unit value as in simulator’s
library file.
2. The RTL description is converted to gate level netlist by a logic
synthesis tool.
3. The designer estimates the prelayout estimates of delays in the chip
using a delay calculator and information about the IC fabrication
process (.sdf)
4. The designer does timing simulation or static timing verification of
the gate level netlist using this preliminary values to check that the
gate level netlist meets timing constraint
5. The gate level netlist is then converted into layout by place and
route tool
6. The postlayout delays are now calculated from the R and C
information in the layout. This R and C depends on technology and
geometry of IC
7. The post layout delay values are back annotated to modify the delay
estimates of the gate level netlist
8. Again timing simulation or STA to check the timings are still
satisfied.
9. If needed, design changes 140

141. 3/3/2023
Static
Timing
Analysis
Back Annotation
141

142. 3/3/2023
Static
Timing
Analysis
Standard Delay Format
• IEEE standard for the representation and interpretation of
timing data for use at any stage of an electronic design
process.
• It has usually two sections: one for interconnect delays and
the other for cell delays.
• SDF format can be used for back-annotation as well as
forward-annotation.
142

143. Thanks!