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STA for Combinational Circuit
Prof. Usha Mehta
Professor,
PG-VLSI Design,
EC, Institute of Technology,
Nirma University, Ahmedabad
usha.mehta@nirmauni.ac.in
usha.mehta@ieee.org
1/25/2022
Static
Timing
Analysis
Acknowledgement
2
This presentation has been summarized
from various books, papers, websites and
presentations and so on …. all over the
world. I couldn’t remember where these
large pull of hints and work come from.
However, I’d like to thank all professors and
scientists who create such a good work on
this emerging field. Without those efforts in
this very emerging technology, these notes
and slides can’t be finished. I am thankful
to them to make my teaching process more
effective.
1/25/2022
Static
Timing
Analysis
STA for Combinational Circuit
• Combinational circuits: Graph model:
• DAG: Directed Acyclic Graph
• Vertices:
• I/O pins of gates
• s and t ( start and stop points)
• Edges:
• Connect each input of a gate to its output
• Show maximum delay paths from the input pin
to the output pin
• Connects the output of each gate to the inputs of
its fanout gates
• Show interconnect delays
• In case of combinational loop:
• Many STA tools break the loop and analyze
3
1/25/2022
Static
Timing
Analysis
Combinational Circuit Representation
: Gate delays only
4
1/25/2022
Static
Timing
Analysis
5
Combinational Circuit Representation
: Gate delays and net delay
1/25/2022
Static
Timing
Analysis
• Add one source to each PI and one sink
node to each PO with 0 – weight edge
• If arrival time of different inputs are different, then the weight
of source edge can represent that delay also.
• For network/algorithm has one clear entry
point and exit point.
• Search algorithms
• Depth First Search Algorithm is most suited to
list all the different possible paths
• Let’s try
6
Combinational Circuit Representation
: Gate delays, net delay and source & Sink node
1/25/2022
Static
Timing
Analysis
STA for Combinational Circuits
Critical Path
 Critical path
Any logical path in the design that violates the timing constraints
The slowest path on the chip between flops or flops and pins.
The critical path limits the maximum clock speed.
The longest path on a DAG graph
7
1/25/2022
Static
Timing
Analysis
Find the Critical path
8
Gate Delay
Not 2
AND 4
OR 4
1/25/2022
Static
Timing
Analysis
Gate Delay
Not 2
AND 4
OR 4
9
1/25/2022
Static
Timing
Analysis
Find the critical path ….
10
1/25/2022
Static
Timing
Analysis
Find the critical Path…..
11
8
1
MUX
12
8
1
MUX
12
1/25/2022
Static
Timing
Analysis
False Path
12
• Paths that physically exist in a design but are not
logic/functional paths
• These paths never get sensitized under any input
conditions
1/25/2022
Static
Timing
Analysis
Logically Impossible Example
13
Mux 1
C C1 C2
A
B
Mux 2
S
B1 B2
OUT
•A path may exist in the circuit but no combination of input vectors may
ever exercise it
d = 10
d = 20
d = 10
d = 20
1/25/2022
Static
Timing
Analysis
False Path Solutions
• Solutions:
• Automatic solutions: too complex to be practical
• E.g. if inverter delay > 0
• In practice:
• Designers knows functionalities best 
Designer specifies
14
1/25/2022
Static
Timing
Analysis
Home work
• Algorithm to find the longest path in DAG
using tcl/tk
15
Thanks!
16

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