This document discusses combinational logic design and CMOS transistor implementation. It covers topics such as logic analysis techniques like loop and cut-set analysis, primitive logic gates, transistor-level implementations, and layout considerations. Primitive gates like NAND and NOR are shown along with complex functions. Optimization techniques for transistor count and layout area are presented, including Euler path analysis and ensuring a continuous diffusion path. Design rules for lambda-based layout and considerations for transistor sizing are also outlined.
2. Before we start……
• Logic with Switching Circuits….
• Logic can be done with switches
as well as gates.
• A parallel connection implements OR. A series connection
implements AND. Series and parallel combinations can do
complex logic.
• Loop Analysis
• Construct all paths between a logic “1” and the output.
Each path is a string of ANDs. which are ORed together. The
expression comes out as a Sum-of-Products (Σ of Π)
• Cut-Set Analysis
• Make all the cuts that completely separate the output and
Vcc. The cuts must only pass through switches. The
switches in the cut are ORed together. The expression
comes out as a Product-of-Sums (Π of Σ)
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3. In case you forgot…..
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9. Pull Up / Pull Down…..
• For nMOS
• Vgs >= Vt
• 5-Vs>=1
• Vs = [0,4) i.e. ( 0 to Vg-Vt only, never Vg full is
coming to Vs)
• For pMOS
• Vgs =< Vt
• Vg-Vs =< Vt
• 0-Vs =< -1
• Vs = (1,5] i.e. ( 0 to Vg-Vt only, never Vg full is
coming to Vs)
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18. Which is better?
NAND or NOR? Why?
• Considering propagation delay….
• Do remember
• For pMOS and nMOS :
• Hence nMOS is speedier than pMOS.
• So overall delay of CMOS is delay of pMOS
• So to reduce the delay of pMOS, reduce the Ron
of pMOS and hence widen the pMOS i.e. double
size.
• R 1/IDD , IDD W/L => R 1/(W/L)
• Now using inverter model,
• Delay
• For nMOS,
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19. Which is better?
NAND or NOR? Why?
• Now using inverter model,
• Delay
• For NAND
• Worst case rise time delay is
• Worst case ( and only) fall time delay is
• For NOR
• Worst case (and only) rise time delay is :
• Worst case fall time delay is:
• Consider Rn = 1 Unit, analyse delay for NOR
and NAND
• in case of pMOS and nMOS of equal size
• Consider widening of pMOS
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20. Gates with large Fan-ins
• The earlier slide’s analysis draws the attentions
towards the deficiency of CMOS for large Fan-
in gates
• Larger Fan-ins means
• Either the series connected pMOSes or nMOSes
• Large difference in rise time and fall time
• Need to find out solutions..
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29. Complimentary Static CMOS
Gates
• At any time, the output is connected to either
power supply or ground with low resistance
path.
• Conduction of Pull-up network (PUN)and Pull-
down network (PDN) should be mutually
exclusive. (Why?)
• PDN and PUN are dual.
• Complimentary static CMOS are inverting.
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37. DO REMEBER
• Find and simplify F’
• Make sure that complements are down to the
literal level.
• Implement F’ as nMOS net and connect it
between ground and output
• OR operations by parallel connected nMOS
• AND operations are series connected nMOS
• Find dual of F’, implement it as pMOS net and
connect it between output and power supply.
• AND operations by parallel connected pMOS
• OR operations are series connected pMOS
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38. Optimize the transistor level
schematic for # of transistor
• F’
• F
• Literals are available in normal form only
• Literals are available in normal form and
complement form.
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39. STICK DIAGRAM FOR TRANSISTOR
LEVEL SCHEMATIC OF COMPLEX
BOOLEAN FUNCTION ( SIZE IS NO
BAR HERE!)
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42. Stick Diagram
• Stick diagrams help plan layout quickly
• Need not be to scale
• Draw with color pencils or dry-erase markers
• Estimate area by counting wiring tracks and
other areas
Vin
Vout
VDD
GND
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43. Stick Diagram Colour Notation
Silicon layers are typically colour coded as follows :
This colour representation is used during mask layer definition
Translation from circuit format to a mask layout (and vice-versa) is relatively straightforward
diffusion (device well, local interconnect)
polysilicon (gate electrode, interconnect)
metal (contact, interconnect)
contact windows
depletion implant
P well (CMOS devices)
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44. Layer contact mask layout representation
A transistor is formed when device well is crossed by polysilicon.
Device well oxide : thin gate oxide
Metal contacting diffusion
Metal contacting polysilicon
Metal contacting diffusion (no contact, electricall
isolated
with thick oxide)
Metal crossing polysilicon (no contact, electrically
isolated
with thick oxide and so can carry separate voltages)
diffusion
polysilicon
metal
contact windows
depletion implant
P well
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45. Transistor Mask Layout Preparation
A transistor is formed when device well is crossed by polysilicon.
Device well oxide : thin gate oxide
Depletion mode transistor (extra well implant to
provide Vth -0.6Vdd )
Enhancement mode transistor (Vth 0.2Vdd )
diffusion
polysilicon
metal
contact windows
depletion implant
P well
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51. Static CMOS Design Example Layout
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52. Layout 2 (Different layout style to previous but same function being
implemented)
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53. Two Stick Diagrams of F =
(C*(A+B))’
A B C
X
VDD
GND
X
CA B
VDD
GND
uninterrupted diffusion strip
crossover requiring vias
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54. To construct a minimum area
layout…
• For a complex logic function, if we choose
arbitrary ordering of polysilicon gates column:
• The separation between the polysilicon columns
must allow
• Diffusion to diffusion separation
• Diffusion to metal separation
• Hence, to reduce the number of diffusion area
break, the ordering of gate column should be
properly planned.
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57. Euler Path
• Find a common Euler path for both p and n
graphs
• Euler Path:
• Uninterrupted path which traverse each edge of
the graph exactly once.
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63. Let’s have one magic!!!!!
• Pl. find the Euler path for x = !(a + bc + de)
• Ok…..
• Now try x = !(bc + a + de)
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64. Duality of Function
• Pl. find Euler’s path for
• F=!(AB+BC+CA)
• Now try with duality concept….
• F = dual of F
• Now pl. check the n and p graph and find the
Euler’s path
• So easy to draw the stick diagram…
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66. LAYOUT
(W/L IS A BIG CONCERN HERE!)
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67. CMOS Inverter Mask Layout (using Microwind)
diffusion
polysilicon
metal
contact windows
depletion implant
P well
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70. CMOS NAND2 Mask Layout
diffusion
polysilicon
metal
contact windows
depletion implant
P well
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71. Layout Design rules & Lambda ()
• Lambda () : distance by which a geometrical feature or
any one layer may stay from any other geometrical feature
on the same layer or any other layer.
• All processing factors are included plus a safety margin.
• used to prevent IC manufacturing problems due to mask
misalignment
• or exposure & development variations on every feature,
which otherwise could lead to :
• over-diffusion
• over-etching
• inadvertent transistor creation etc
• is the minimum dimension which can be accurately re-
produced on the silicon wafer for a particular technology.
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72. Layout Design rules & Lambda ()
• Minimum photolithographic dimension (width, not
separation) is 2.
• Hence, the minimum channel length dimension is 2.
• Where a 0.25m gate length is quoted, is 0.125 microns
(m).
• Minimum distance rules between device layers are used,
e.g.,
• polysilicon metal
• metal metal
• diffusion diffusion and
• minimum layer overlaps
• Layout design rule checker (DRC) automatically verifies
that no design rules have been broken
• Note however, the use of Lambda is not optimal but supports
design reuse
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73. Layout Design rules &
Lambda ()
Lambda based design: half of technology since 1985. As technology
changes with smaller dimensions, a simple change in the value of can
be used to produce a new mask set.
6
2
6
4
Hcmos6 technology : =0.2µm
Hcmos8 technology : =0.1µm
All device mask dimensions are based on multiples of , e.g., polysilicon
minimum width = 2. Minimum metal to metal spacing = 3
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75. Basic Design Rules
• Same N and P alters symmetry • L min
• Wpmos=2 Wnmos
Width of pMOS
should be twice the
width of nMOS
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76. CALCULATION OF SIZE
BASICALLY CALCULATION OF
W/L……..
ALL OTHER SIZE IS WITH
REFERENCE TO W/L
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77. Design Strategy
• Fan-out, Rise time, Fall time…
• Load Current, VOL, VOH..…
• Depends on W/L and other parameters…
• Designable parameter is (W/L).
• Find the worst case of above parameters and
design for that (W/L)
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78. • Performing a manual analysis of the dynamic
behavior of complex gates is only tractable via
a switch model.
• Here, the transistor is modelled as a switch
with an infinite off-resistance and a finite on
resistance, Ron.
• Ron is chosen so that the equivalent RC-circuit
has a propagation delay identical to the
original transistor-capacitor model.
• Ron is inversely proportional to the W/L ratio
but varies during the switching transient.
• Deriving propagation delay can be done by
analysing the RC network.
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84. To calculate W/L….
• Specify maximum allowable VOL value
• Calculate equivalent (W/L)driver using for that
VOL
• Determine worst case path (class-1)
• Determine worst case path transistor size to
give the equivalent worst path VOL same as
equivalent (W/L)driver
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85. Layout Optimization
Device Folding / Fingering & Sharing
• When we have to make the devices for large
current (like drivers), the width of the devices
should be very high compared to the other
devices
• Large transistors can be split into smaller ones
and then shorting the corresponding terminals
making up the required W/L
• In such an arrangement we can share the
diffusion drain and source of adjacent
transistors and then we can short the
terminals
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86. Folding & Sharing (Cont...)
Why to have folding / fingering?
Poly resistance is reduced as single poly is
divided in multiple parts of poly
To maintain the uniformity in diffusion area
Process variations are less
Why to have sharing?
To save the diffusion area
To reduce the parasitic associated with the
devices
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87. Folding and Sharing
D SG
D S
D S
G
Equivalence of devices connected in parallel
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88. Folding and Sharing…..
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D SG D SD SG G
Equivalence of devices connected in series
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89. Folding and Sharing
S & D sharing in devices
G
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90. Static CMOS
Do remember…
• Every point in time, gate output is connected
to either supply or ground via low resistance
path
• Rail to rail output voltage
• Ratioless design
• Low output and Extremely High input
impedance
• No static power dissipation
• Good Noise Margin
• BUT what about Rise and Fall Time????
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97. Pseudo nMOS Gates
• Only single pMOS in load, permanently gate of
pMOS connected to ground
• Disadvantages:
• Always on load i.e. steady state current, static
power
• o/p voltage < Vdd
• Ratioed logic
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