Placement is the process of determining the locations of circuit devices on a chip. It is a critical step that affects performance, routability, heat distribution, and power consumption. There are different types of placement like standard cell placement and building block placement. Placement algorithms aim to optimize objectives like minimizing total area and wire length. Simulated annealing is a commonly used iterative placement algorithm that models the physical annealing process to arrive at a low-cost solution. Other algorithms include partitioning-based approaches and cluster growth.

1. PLACEMENT IN
PHYSICAL
DESIGN
(ASHISH KUMAR SINGH,PRIYANKA BRAHMA,SWEETY KUMARI)
M.TECH –VLSI
NIT SILCHAR,ASSAM
1

2. AGENDA
WHAT IS PLACEMENT AND ITS TYPES
BACK END PROCESS
PLACEMENT PROBLEM FORMULATION
ALGORITHMS
SIMULATED BASED PLACEMENT
PARTITIONING BASED PLACEMENT
2

3. PLACEMENT AND ITS TYPES
3

4. Placement is the process of determining the locations of
circuit devices on a die surface. It is an important stage
in the VLSI design flow, because it affects rout ability,
performance, heat distribution, and to a less extent,
power consumption of a design. Traditionally, it is
applied after the logic synthesis stage and before the
routing stage
PLACEMENT- 4

5. Cont- 5
Placement is a critical step in the VLSI design flow
mainly for the following four reasons. First, placement
is a key factor in determining the performance of a
circuit. Placement largely determines the length and,
hence, the delay of interconnect wires. As feature size
in advanced VLSI technology continues to reduce,
interconnect delay has become the determining factor of
circuit performance

6. Types of placement-
1. STANDARD CELL PLACEMENT –
STANDARD CELLS HAVE BEEN DESIGNED IN SUCH A WAY THAT
POWER AND CLOCK CONNECTIONS RUN HORIZONTALLY THROUGH
THE CELL AND OTHER I/O LEAVES THE CELL FROM THE TOP OR
BOTTOM SIDES.
6

7. 2. Building block placement
CELLS TO BE PLACED HAVE ARBITRARY SHAPE.
7

8. Placement is done in three steps:
1. Global placement
generate a rough placement that may violate
some placement constraints (e.g., there may be
overlaps among modules)
2. Legalization placement
makes the rough solution from global placement
legal (no placement constraint violation) by
moving modules around locally.
3. Detailed placement
further improves the legalized placement
solution in an iterative manner by rearranging a
small group of modules in a local region while
keeping all other modules fixed.
8

9. Out of the three steps important one is
global placement
Approaches for global placement are :
 Partitioning based approach (min cut partitioning)
 Simulated annealing approach
 Analytical approach (best)
9
Placement is the problem of automatically assigning correct positions to
predesigned cells on the chip with no overlapping such that some objective
function is optimized.
Placement is design state after logic synthesis and before routing.

10. 10

11. BACK END PROCESS
11

12. 1. PARTITIONING
GOAL: PARTITION OF A SYSTEM INTO NUMBER OF
ASIC’S(APPLICATION SPECIFIC INTEGRATED CHIP)
OBJECTIVE: MINIMISE THE NUMBER OF EXTERNAL
CONNECTIONS BETWEEN EACH ASIC. KEEP EACH ASIC
SMALLER THAN MAX SIZE.
2. FLOORPLANNING
GOAL: CALCULATE THE SIZE OF BLOCKS AND ASSIGN THEM
LOCATIONS.
OBJECTIVE: KEEP HIGHLY CONNECTED BLOCKS
PHYSICALLY CLOSE TO EACH OTHER.
12

13. 3. Placement
Goal: assign the interconnect areas and the locations
of all the logic cells within the flexible block
Objective: minimise the ASIC area and the
interconnects
4. Global routing
Goal: determine the location of all the interconnects
Objective: minimise the total interconnect area.
5. Detailed routing
Goal: completely route all the interconnects on the
chip
Objective: minimise the total interconnect length
used
13

14. PLACEMENT PROBLEM FORMULATION
14

15.  INPUT:
Placement region, a set of modules, and a set of nets. The
widths and heights of the placement region and all modules are
given. The locations of I/O pins on the placement region and
on all modules are fixed.
 OUTPUT:
A set of location on the chip : one location for each cell.
15

16. •OBJECTIVES:
Minimize the ASIC area and the interconnects
•GOAL:
Arrange all the logic cells within flexible blocks
The cells are placed to produce a routable chip that meets timing
and other constraints (e.g., low-power, noise, etc.)
•CHALLENGE:
The number of cells in a design is very large (> 1 million).
16

17. Global and Detailed Placement
IN GLOBAL PLACEMENT ,
THE APPROXIMATE
LOCATIONS FOR CELLS IS DECIDED
BY PLACING CELLS IN GLOBAL BINS.
IN DETAILED PLACEMENT, CELLS ARE
PLACED WITHOUT OVER LAPPING.
17

18. Good and bad placement
Good placement
 Minimize area (total wiring
area)
 Ensure routability
 Avoid signal interference
 Distribute heat
 Maximize performance
Bad placement
 Consumes large areas
 Results in performance
degradation
 Results in difficult and
sometimes impossible tasks
(Routing)
 An ill-placed layout cannot
be improved by high quality
routing.
18

19. 19

20. PLACEMENT ALGORITHMS
20

21. Optimisation of the following is done using
placement algorithm
•TOTAL AREA
•TOTAL WIRE LENGTH
•HEURISTICS ARE USED IN THE ALGORITHMS.
21

22. Estimation of Wirelength
The speed and quality of estimation has a drastic
effect on the performance of placement algorithms.
 For 2-terminal nets, we can use Manhattan distance as
an estimate.
 If the end co-ordinates are (x1,y1) and (x2,y2), then the
wire length
L = ⎥ x1 – x2 ⎥ + ⎥ y1 – y2⎥
22

23. Constructive
 Once the position of the
cell is fixed , it can not be
modified
 Constructive algorithms are
used to obtain an
initial placement.
Iterative
 Intermediate placements are
modified in an attempt to
improve the cost function.
 The initial placement is
followed by an iterative
improvement phase.
23

24. Techniques for initial placement
A TOP-DOWN METHOD:
MIN-CUT PARTITIONING AND PLACEMENT (BISECT THE CIRCUIT
RECURSIVELY)
MIN-CUT PLACEMENT METHOD:
1. CUT PLACEMENT AREA INTO TWO PIECES
2. SWAP LOGIC CELLS TO MINIMIZE CUT COST
3.REPEAT PROCESS FROM STEP 1, CUTTING SMALLER
PIECES UNTIL ALL LOGIC CELLS ARE PLACED
24

25. 25

26. A bottom-up method: cluster growth (select
cells with strongest connections one by one)
26

27. SIMULATED ANNEALING PLACEMENT
•INITIAL PLACEMENT IMPROVED THROUGH SWAPS AND MOVES
•ACCEPT A SWAP/MOVE IF IT IMPROVES THE COST
27

28. Classification of Algorithm
CLASSIFICATION OF ALGORITHM
Simulation based Partitioning based Other
Simulated Annealing
Simulated Evolution
Force Directed
Breuer’s Algorithm
Terminal Propagation
Cluster Growth
Force Directed
28

29. Simulation annealing placement-
 Various algorithms proposed for placement in circuits.
 Constructive placement vs Iterative improvement.
 Simulated Annealing – an iterative improvement
algorithm
29

30. Simulated Annealing
 Annealing in metals
 Heat the solid state metal to a high temperature
 Cool it down very slowly according to a specific
schedule.
 If the heating temperature is sufficiently high to
ensure random state and the cooling process is
slow enough to ensure thermal equilibrium, then
the atoms will place themselves in a pattern that
corresponds to the global energy minimum of a
perfect crystal.
30

31. Simulated Annealing and
VLSI Placement:
 Arrangement of atoms = a new configuration of cells (
a new solution)
 Total configurations = Total solution set
 Perturbation = small random movement of cells to get
new configuration (possible solution).
 Energy = Cost function
 Temperature = control parameter
 Cooling schedule = starting temperature and a rule
how to decrease the temperate or how to cool
31

32. Steps-
Step 1: Initialize – Start with a random initial placement.
Initialize a very high “temperature”.
Step 2: Move – Perturb the placement through a defined move.
Step 3: Calculate score – calculate the change in the score due
to the move made.
Step 4: Choose – Depending on the change in score, accept or
reject the move. The probability of acceptance depending on
the current “temperature”.
Step 5: Update and repeat– Update the temperature value by
lowering the temperature. Go back to Step 2.
The process is done until “Freezing Point” is reached.
32

33. Simulated Annealing Algorithm
Algorithm SA_Placement
begin
T = initial_temperature;
P = initial_placement;
while ( T > final_temperature) do
while (no_of_trials_at_each_temp not yet completed) do
new_P = PERTURB (P);
ΔC = COST (new_P) – COST (P);
if (ΔC < 0) then
P = new_P;
else if (random(0,1) > exp(-ΔC/T)) then
P = new_P;
T = SCHEDULE (T); /** Decrease temperature **/
end
33

34. Parameters 34
 INIT-TEMP = 4000000 C;
 INIT-PLACEMENT = Random;
 PERTURB(place)
1. Displacement of a block to a new
position.
2. Interchange blocks.
3. Orientation change for a block.
 SCHEDULE.

35. Timber Wolf
One of the most successful placement algorithms.
Developed by Sechen and Sangiovanni-Vincentelli.
Parameters used:
– Initial_temperature = 4,000,000 C
– Final_temperature = 0.1 C
– SCHEDULE(T) = α(T) x T
• α(T) specifies the cooling rate which depends on the
current temperature.
• α(T) is 0.8 when the cooling process just starts.
• α(T) is 0.95 in the medium range of temperature.
• α(T) is 0.8 again when temperature is low.
35

36. Simulated Evolution / Genetic
Algorithm
 The algorithm starts with an initial set of placement
configurations.
Called the population.
 The process is iterative, where each iteration is called a
generation.
The individuals of a population are evaluated to measure
their goodness.
 To move from one generation to the next, three genetic
operators are used:
 Crossover
 Mutation
 Selection
36

37. Breuer’s Algorithm
 Partitioning technique used to generate placement.
 The given circuit is repeatedly partitioned into two sub-
circuits
 At each level of partitioning, the available layout area is
partitioned into horizontal and vertical subsections
alternately.
 Each of the sub-circuits is assigned to a subsection.
 Process continues till each sub-circuit consists of a single
gate, and has a unique place on the layout area.
37

38. Cont-
 Different sequences of cut lines used:
1. Cut Oriented Min-Cut Placement
2. Quadrature Placement
3. Bisection Placement
4. Slice Bisection Placement
38

39. Terminal Propagation
Algorithm
 Partitioning algorithms merely reduce net cut.
 Direct use of partitioning algorithms would increase net
length.
 To prevent this, terminal propagation is used.
 When a net connecting two terminals is cut, a dummy
terminal is propagated to the nearest pin on the
boundary.
39

40. 40

41. Cluster Growth
 In this constructive placement algorithm, bottom-up
approach is used.
 Blocks are placed sequentially in a partially completed
layout.
 The first block (seed) is usually placed by the user.
 Other blocks are selected and placed one by one.
 Selection of blocks is usually based on connectivity with
placed blocks
41

42. Cont-
 Layouts produced are not usually good.
Does not take into account the interconnections and other
circuit features.
 Useful for generating initial placements.
For iterative placement algorithms
42

43. Algorithm Cluster_Growth
begin
B = set of blocks to be placed;
Select a seed block S from B;
Place S in the layout;
B = B – S;
while (B ≠ φ) do
begin
Select a block X from B;
Place X in the layout;
B = B – X;
end;
end
43

44. Performance Driven
Placement
 The delay at chip level plays an important role in
determining the performance of the chip.
- Depends on interconnecting wires.
 As the blocks in a circuit becomes smaller and
smaller:
-The size of the chip decreases.
-Interconnection delay becomes a major issue in
highperformance circuits.
 Placement algorithms for high-performance chips:
-Allow routing of nets within timing constraints.
44

45. Cont-
Two major categories of algorithms:
1. Net-based approach
 Try to route the nets to meet the timing constraints on the
individual nets instead of considering paths.
 The timing requirement for each net has to be decided by
the algorithm.
 Usually a pre-timing analysis generates the bounds on the
net-lengths which must be satisfied during placement.
2. Path-based approach
 Critical paths in the circuit are considered.
 Try to place the blocks in a manner that the path length is
within the timing constraint.
45

46. 46