Introduction to VLSI

By
Asilicon Design Team
Introduction to VLSI

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Contents Overview
 VLSI Introduction
 Scaling
 Moore’s Law
 IC Technologies
 Design Style (Approach)
 CMOS
 Process Technology
 ASIC Flow
 Technology Summary

VLSI Introduction
Shockley, Bardeen and Brattain at Bell Labs

The Integrated Circuit
 1959: Jack Kilby, working at Texas Instruments, invented a
monolithic “integrated circuit”
 Components connected by hand-soldered wiresand isolated by “shaping”,
PN-diodes used as resistors

Integrated Circuits
 1961: TI and Fairchild introduce the first logic ICs
 1962: RCA develops the first MOS transistor
Fairchild bipolar RTL Flip-Flop RCA 16-transistor MOSFET IC

Computer-Aided Design
 1967: Fairchild develops the “Micromosaic” IC using CAD
 Final Al layer of interconnect could be customized for different
applications
 1968: Noyce, Moore leave Fairchild, started Intel

RAMs
 1970: Fairchild introduces 256-bit Static RAMs
 1970: Intel starts selling1K-bit Dynamic RAMs
Fairchild 4100 256-bit SRAM Intel 1103 1K-bit DRAM

The Microprocessor
 1971: Intel introduces the 4004
 General purpose programmable computer instead of custom chip
for Japanese calculator company
Intel 4004 Microprocessor

VLSI: Very Large Scale Integration
 Integration: Integrated Circuits
 Multiple devices on one substrate
 Integrated Device
 SSI – Small Scale Integration
 7400 series, 10-100 transistors
 MSI – Medium Scale Integration
 74000 series, 100-1000 transistors
 LSI – Large Scale Integration
 1000-10,000 transistors
 VLSI – > 10,000 transistors
 ULSI/SLSI – (some disagreement)

CMOS Technology Trends

Scale Example
 Consider a chip size of 20mm X 20mm
 Consider a transistor size of 1um X 1um
(including area of wires etc.)
 Chip Area: 400sq.mm = 400,000,000sq.um
 Transistor Area: 1sq.um
 400M Transistor in 20mmX20mm Die
 Transistor vs. Gate vs. Instance
 Transistor – 1 MOS device
 Gate – OR, AND, INV [4 Transistor]
 Instance – Standard Cell [3 Gate]

Scale Example
 In latest technology node, transistors are few microns
wide and approximately 0.1 micron or less in length
 Human hair is 80-90 microns in diameter
 >1000 Times of Actual
Transistor Size

DesignAbstraction Level
n+n+
S
G
D
+
DEVICE
CIRCUIT
GATE
MODULE
SYSTEM

Moore’s Law
In 1965, Gordon Moore made a prediction that would set the
place for our modern digital revolution.
Moore extrapolated that computing would dramatically
increase in power, and decrease in relative cost, at an
exponential pace.
In simple form, it stated that number of transistors on
integrated circuits would double every two years.

Moore’s Law
The number of transistors on integrated circuits would
double every two years.
Play
Video
http://www.intel.com/content/www/us/e
n/silicon-innovations/moores-law-
technology.html

Technologies
 Bipolar (BJT)
 TTL, Schottky
 ECL
 I^2L
 Dual Junction, Current controlled devices
 MOS (FET unipolar)
 NMOS, PMOS
 CMOS
 Single Junction, voltage controlled devices
 GaAs (Typically JFET’s)
 OEIC’s – MQW’s, Integrated Lasers

What is “CMOS VLSI”?
 MOS = Metal Oxide Semiconductor (This used to mean
a Metal gate over Oxide insulation).
 Now we use polycrystalline silicon which is deposited
on the surface of the chip as a gate. We call this “poly”
or just “red stuff” to distinguish it from the body of the
chip, the substrate, which is a single crystal of silicon.
 We do use metal (aluminum) for interconnection wires
on the surface of the chip.

S DG
Poly crossed over Diffusion  Field effect transistor (FET)
Insulated Gate  Metal Oxide Semiconductor FET
Source and Drain are Interchangeable
D
S
G
MOSFET

N-Channel Enhancement mode MOS FET
 Four Terminal Device - substrate bias
–The “self aligned gate” - key to CMOS

CMOS: Complementary MOS
 CMOS using both N-channel and P-channel type
enhancement mode Field Effect Transistors (FETs).
 Field Effect- NO current from the controlling electrode
into the output
 FET is a voltage controlled current device
 BJT is a current controlled current device
 N/P Channel - doping of the substrate for increased
carriers (electrons or holes)

CMOS
Complementary Metal Oxide
Semiconductor
PMOS
NMOS
VSS
VDD
X X’
NMOS

Four Views
Logic Transistor Layout Physical

VLSI Design
 The real issue in VLSI is about designing systems on
chips.
 The designs are complex, and we need to use structured
design techniques and sophisticated design tools to
manage the complexity of the design.
 We also accept the fact that any technology we learn the
details of will be out of date soon.
 We are trying to develop and use techniques that will
transcend the technology, but still respect it.

Help from Computer Aided Design tools
 Tools
 Editors
 Simulators
 Libraries
 Module Synthesis
 Place/Route
 Chip Assemblers
 Silicon Compilers
 Experts
 Behavior model &
Circuit design
 Circuit Simulation
 Device physics[Library
Creation]
 Verilog to Gates Level
 Physical Implementation
 Architectures

Design Approach (Style)
 Full Custom
 Standard Cell Based
 Gate Array
 Macro Cell
 “FPGA”
 Combinations

Full Custom
 Hand drawn geometry
 All layers customized
 Digital and analog
 Simulation at transistor level (Analog)
 High density
 High performance
 Long design time

Standard Cells Based
 Standard cells organized in rows (and, or, flip-
flops etc.)
 Cells made as full custom by vendor (not user).
 Digital with possibility of special analog cells.
 Simulation at gate level (digital)
 Medium density
 Medium-high performance
 Reasonable design time

Standard Cells Based
Routing
Cell
IO cell

Gate Array
 Predefined transistors connected via metal
 Two types: Channel based
Channel less (sea of gates)
 Only metallization layers customized
 Fixed array sizes (normally 5-10 different)
 Digital cells in library (and, or, flip-flops etc.)
 Simulation at gate level (digital)
 Medium density
 Medium performance
 Reasonable design time

Gate Array
Oxide isolation
Gate isolation
PMOS
NMOS
Vdd
Gnd
B
A
Out
Vdd
Gnd
A
B
Out
Sea of gates Channel based
NAND gate using gate isolation
Can in principle be used by adjacent cell

Macro Cell
 Predefined macro blocks (Processors, RAM,etc)
 Macro blocks made as full custom by vendor
 Digital and some analog (ADC)
 Simulation at behavioral or gate level (digital)
 High density
 High performance
 Short design time
 Use standard on-chip busses
 “System on a chip”
DSP processor
LCD
cont.
RAM
ROMADC

FPGA = Field Programmable Gate Array
 Programmable logic blocks
 Programmable connections between logic blocks
 No layers customized (standard devices)
 Digital only
 Low - medium performance (<50 - 100MHz)
 Low - medium density (up to ~100k gates)
 Programmable by: SRAM, EEROM, Anti_fuse, etc
 Cheap design tools on PC’s
 Low development cost
 High device cost

Comparison
FPGA Gate array Standard cell Full custom Macro cell
Density Low Medium Medium High High
Flexibility Low (high) Low Medium High Medium
Analog No No No Yes Yes
Performance Low Medium High Very high Very high
Design time Low Medium Medium High Medium
Design costs Low Medium Medium High High
Tools Simple Complex Complex Very complex Complex
Volume Low Medium High High High

High Performance Devices
 Mixture of full custom, standard cells and macro’s
 Full custom for special blocks: ADC, DAC, DDR,
Serdes etc.
 Macro’s for standard blocks: RAM, ROM, etc.
 Standard cells for non critical digital blocks

Dual port RAM
Full custom
Standard cell
ASIC with mixture of full custom, RAM and standard cells
FIFO
Single port RAM

System-on-Chip

MOSFET Fundamental
 Process Node: Channel Length
 Example: 0.25um Process

ON/OFF Current Ratio

MOSFET: ON State (Vgs > Vth)
Channel

CMOS Technology Scaling

Technologies: Process Node

CMOS Scaling
 The Gap can be filled with DG-FETs [FinFET]
 Key Limitation of CMOS scaling addressed through
 Better control of channel from transistor gates
 Reduced short-channel effects
 Better Ion/Ioff
 Improved sub-threshold slope
 No discrete dopant fluctuations

Double-Gate MOSFET Structure [FinFET]

FinFET Structure

Technology [Process] Types
 BULK CMOS
 SOI
 FDSOI
 FinFET
 BiCMOS

Bulk vs. SOI

Bulk vs. FD-SOI

Bulk vs. FinFET

ASIC Design Flow

Design Flow

Technology Summary: 2015
 Today’s Massive Products getting build in 28nm Bulk
(CMOS) – > 90%
 < 10% Products getting build in 14/16nm FinFET [Huge
Fabrication Cost & Early Technology]
 < 1% Products getting build in 32SOI & 28FDSOI
 Technology in Progress: 10nm Geometry
 Dominant Market: IoT (Internet of Things) & Smart
Phones

Introduction to VLSI

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