The document describes the VLSI design flow with reference to the Xilinx FPGA tool. It involves modeling the system using a hardware description language like VHDL or Verilog. The synthesis tool then generates a netlist from this code. This netlist is mapped to the FPGA technology by inferring components. These components are placed on the chip and connecting signals are routed through the interconnection network to produce a bitstream that can configure the FPGA.

1. VLSI Design Flow
With Reference to Xilinx Tool
1

2. VLSI Design Flow with Reference to Xilinx EDA Tool

3. 3
HDL
(VHDL /
Verilog)
Synthesize
Netlist
Map
Place
Route
Bitstrea
m
 Hardware design is traditionally done by modeling the
system in a hardware description language
 An FPGA “compiler” (synthesis tool) generates a netlist,
 which is then mapped to the FPGA technology,
 the inferred components are placed on the chip,
 and the connecting signals are routed through the
interconnection network.
FPGAs  FPGA Tool Flow  System on Chip (SoC)  SoC Tool Flow  Demonstration
FPGA Tool Flow

4. 4

Register
a
b
output
clk
reset
clear
D Q
process(clk, reset)
begin
if reset = ‚1‘ then
output <= ‚0‘;
elsif rising_edge(clk) then
output <= a XOR b;
end if;
end process;
HDL
(VHDL /
Verilog)
Synthesize
Netlist
Map
Place
Route
Bitstrea
m
FPGAs  FPGA Tool Flow  System on Chip (SoC)  SoC Tool Flow  Demonstration
Synthesis Tool

5. 5
HDL
(VHDL /
Verilog)
Synthesize
Netlist
Map
Place
Route
Bitstrea
m

Register
a
b
output
clk
reset
clear
D Q
FPGAs  FPGA Tool Flow  System on Chip (SoC)  SoC Tool Flow  Demonstration
Technology Mapping

6. 6
HDL
(VHDL /
Verilog)
Synthesize
Netlist
Map
Place
Route
Bitstrea
m
FPGAs  FPGA Tool Flow  System on Chip (SoC)  SoC Tool Flow  Demonstration
Place & Route

7. Thank You
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