This course for someone with no previous experience with VHDL to learn VHDL language and write codes targeting hardware.
This course is focusing on syntax of VHDL, basic design circuits.
For all course videos and material visit YouTube channel
www.youtube.com/channel/UCcecv3gqLQCRT8MS3_aRn9Q
This course for someone with no previous experience with VHDL to learn VHDL language and write codes targeting hardware.
This course is focusing on syntax of VHDL, basic design circuits.
For all course videos and material visit YouTube channel
www.youtube.com/channel/UCcecv3gqLQCRT8MS3_aRn9Q
This course for someone with no previous experience with VHDL to learn VHDL language and write codes targeting hardware.
This course is focusing on syntax of VHDL, basic design circuits.
For all course videos and material visit YouTube channel
www.youtube.com/channel/UCcecv3gqLQCRT8MS3_aRn9Q
CETPA INFOTECH PVT LTD is one of the IT education and training service provider brands of India that is preferably working in 3 most important domains. It includes IT Training services, software and embedded product development and consulting services.
http://www.cetpainfotech.com
6 months/weeks training in Vlsi,jalandhardeepikakaler1
E2marix is leading Training & Certification Company offering Corporate Training Programs, IT Education Courses in diversified areas.Since its inception, E2matrix educational Services have trained and certified many students and professionals.
TECHNOLOGIES PROVIDED -
MATLAB
NS2
IMAGE PROCESSING
.NET
SOFTWARE TESTING
DATA MINING
NEURAL networks
HFSS
WEKA
ANDROID
CLOUD computing
COMPUTER NETWORKS
FUZZY LOGIC
ARTIFICIAL INTELLIGENCE
LABVIEW
EMBEDDED
VLSI
Address
Opp. Phagwara Bus Stand, Above Bella
Pizza, Handa City Center, Phagwara
email-e2matrixphagwara@gmail.com
jalandhare2matrix@gmail.com
Web site-www.e2matrix.com
CONTACT NUMBER --
07508509730
09041262727
7508509709
This course for someone with no previous experience with VHDL to learn VHDL language and write codes targeting hardware.
This course is focusing on syntax of VHDL, basic design circuits.
For all course videos and material visit YouTube channel
www.youtube.com/channel/UCcecv3gqLQCRT8MS3_aRn9Q
This course for someone with no previous experience with VHDL to learn VHDL language and write codes targeting hardware.
This course is focusing on syntax of VHDL, basic design circuits.
For all course videos and material visit YouTube channel
www.youtube.com/channel/UCcecv3gqLQCRT8MS3_aRn9Q
CETPA INFOTECH PVT LTD is one of the IT education and training service provider brands of India that is preferably working in 3 most important domains. It includes IT Training services, software and embedded product development and consulting services.
http://www.cetpainfotech.com
6 months/weeks training in Vlsi,jalandhardeepikakaler1
E2marix is leading Training & Certification Company offering Corporate Training Programs, IT Education Courses in diversified areas.Since its inception, E2matrix educational Services have trained and certified many students and professionals.
TECHNOLOGIES PROVIDED -
MATLAB
NS2
IMAGE PROCESSING
.NET
SOFTWARE TESTING
DATA MINING
NEURAL networks
HFSS
WEKA
ANDROID
CLOUD computing
COMPUTER NETWORKS
FUZZY LOGIC
ARTIFICIAL INTELLIGENCE
LABVIEW
EMBEDDED
VLSI
Address
Opp. Phagwara Bus Stand, Above Bella
Pizza, Handa City Center, Phagwara
email-e2matrixphagwara@gmail.com
jalandhare2matrix@gmail.com
Web site-www.e2matrix.com
CONTACT NUMBER --
07508509730
09041262727
7508509709
Very-large-scale integration (VLSI) is the process of creating an integrated circuit (IC) by combining thousands of transistors into a single chip. VLSI began in the 1970s when complex semiconductor and communication technologies were being developed. The microprocessor is a VLSI device. Before the introduction of VLSI technology most ICs had a limited set of functions they could perform. An electronic circuit might consist of a CPU, ROM, RAM and other glue logic. VLSI lets IC designers add all of these into one chip.
The History of the transistor dates to the mid-1920s when several inventors attempted devices that were intended to control current in solid-state diodes and convert them into triodes. Success came after World War II, when the use of silicon and germanium crystals as radar detectors led to improvements in fabrication and theory. Scientists who had worked on radar returned to solid-state device development. With the invention of transistors at Bell Labs in 1947, the field of electronics shifted from vacuum tubes to solid-state devices.
With the small transistor at their hands, electrical engineers of the 1950s saw the possibilities of constructing far more advanced circuits. However, as the complexity of circuits grew, problems arose.
One problem was the size of the circuit. A complex circuit like a computer was dependent on speed. If the components were large, the wires interconnecting them must be long. The electric signals took time to go through the circuit, thus slowing the computer.
The Invention of the integrated circuit by Jack Kilby and Robert Noyce solved this problem by making all the components and the chip out of the same block (monolith) of semiconductor material. The circuits could be made smaller, and the manufacturing process could be automated. This led to the idea of integrating all components on a single silicon wafer, which led to small-scale integration (SSI) in the early 1960s, medium-scale integration (MSI) in the late 1960s, and then large-scale integration (LSI) as well as VLSI in the 1970s and 1980s, with tens of thousands of transistors on a single chip (later hundreds of thousands, then millions, and now billions (109)).
Video and slides synchronized, mp3 and slide download available at URL http://bit.ly/2X8uz92.
Alex Bradbury gives an overview of the status and development of RISC-V as it relates to modern operating systems, highlighting major research strands, controversies, and opportunities to get involved. Filmed at qconlondon.com.
Alex Bradbury is co-founder of lowRISC CIC, aiming to bring the benefits of open source development to the hardware industry by producing a high quality, secure, and open source SoC and associated infrastructure. He is a well-known member of the LLVM community, and is code owner and primary author of the upstream RISC-V back-end.
Very-large-scale integration (VLSI) is the process of creating an integrated circuit (IC) by combining thousands of transistors into a single chip. VLSI began in the 1970s when complex semiconductor and communication technologies were being developed. The microprocessor is a VLSI device. Before the introduction of VLSI technology most ICs had a limited set of functions they could perform. An electronic circuit might consist of a CPU, ROM, RAM and other glue logic. VLSI lets IC designers add all of these into one chip.
The History of the transistor dates to the mid-1920s when several inventors attempted devices that were intended to control current in solid-state diodes and convert them into triodes. Success came after World War II, when the use of silicon and germanium crystals as radar detectors led to improvements in fabrication and theory. Scientists who had worked on radar returned to solid-state device development. With the invention of transistors at Bell Labs in 1947, the field of electronics shifted from vacuum tubes to solid-state devices.
With the small transistor at their hands, electrical engineers of the 1950s saw the possibilities of constructing far more advanced circuits. However, as the complexity of circuits grew, problems arose.
One problem was the size of the circuit. A complex circuit like a computer was dependent on speed. If the components were large, the wires interconnecting them must be long. The electric signals took time to go through the circuit, thus slowing the computer.
The Invention of the integrated circuit by Jack Kilby and Robert Noyce solved this problem by making all the components and the chip out of the same block (monolith) of semiconductor material. The circuits could be made smaller, and the manufacturing process could be automated. This led to the idea of integrating all components on a single silicon wafer, which led to small-scale integration (SSI) in the early 1960s, medium-scale integration (MSI) in the late 1960s, and then large-scale integration (LSI) as well as VLSI in the 1970s and 1980s, with tens of thousands of transistors on a single chip (later hundreds of thousands, then millions, and now billions (109)).
Video and slides synchronized, mp3 and slide download available at URL http://bit.ly/2X8uz92.
Alex Bradbury gives an overview of the status and development of RISC-V as it relates to modern operating systems, highlighting major research strands, controversies, and opportunities to get involved. Filmed at qconlondon.com.
Alex Bradbury is co-founder of lowRISC CIC, aiming to bring the benefits of open source development to the hardware industry by producing a high quality, secure, and open source SoC and associated infrastructure. He is a well-known member of the LLVM community, and is code owner and primary author of the upstream RISC-V back-end.
Visit https://www.vlsiuniverse.com/
https://www.vlsiuniverse.com/2020/05/complete-asic-design-flow.html
This is the standard VLSI design flow that every semiconductor company follows. The complete ASIC design flow is explained by considering each and every stage.
6 weeks/months summer training in vlsi,ludhianadeepikakaler1
E2matrix offer our assistance, writing and consulting services with your research assignments particularly in the areas of thesis, dissertations, journals, online forum discussions, FYP, and so on.
We also provide training for the different technologies and are involved in a wide diversity of subject areas ranging from management,engineering up to programming and designs; and our team of research experts and professional consultants are readily available to help you towards your successful completion of your assignments.
Engage us today at our e2matrixphagwara@gmail.com
jalandhare2matrix@gmail.com
and can visit our web site-www.e2matrix.com
contact us-7508509709
07508509730
CETPA INFOTECH PVT LTD is one of the IT education and training service provider brands of India that is preferably working in 3 most important domains. It includes IT Training services, software and embedded product development and consulting services.
http://www.cetpainfotech.com
CETPA INFOTECH PVT LTD is one of the IT education and training service provider brands of India that is preferably working in 3 most important domains. It includes IT Training services, software and embedded product development and consulting services.
A VLSI (Very Large Scale Integration) system integrates millions of “electronic components” in a small area (few mm2 few cm2).
design “efficient” VLSI systems that has:
Circuit Speed ( high )
Power consumption ( low )
Design Area ( low )
ASIC DESIGN OF MINI-STEREO DIGITAL AUDIO PROCESSOR UNDER SMIC 180NM TECHNOLOGYIlango Jeyasubramanian
- Designed and analyzed a complete MSDAP with optimized convolution computation by only shifts and adds using power-of-2 coefficients. Synthesized the chip through high level architecture design (C Program), Logic synthesis (Synopsys Design Compiler) and Physical Synthesis (Synopsys IC compiler).
- Achieved a low power consumption of 3.1438mW at 29.186Mhz clock frequency, with core utilization of 70% and chip area of 1.29mm2.
Similar to Session 01 _rtl_design_with_vhdl 101 (20)
Software Delivery At the Speed of AI: Inflectra Invests In AI-Powered QualityInflectra
In this insightful webinar, Inflectra explores how artificial intelligence (AI) is transforming software development and testing. Discover how AI-powered tools are revolutionizing every stage of the software development lifecycle (SDLC), from design and prototyping to testing, deployment, and monitoring.
Learn about:
• The Future of Testing: How AI is shifting testing towards verification, analysis, and higher-level skills, while reducing repetitive tasks.
• Test Automation: How AI-powered test case generation, optimization, and self-healing tests are making testing more efficient and effective.
• Visual Testing: Explore the emerging capabilities of AI in visual testing and how it's set to revolutionize UI verification.
• Inflectra's AI Solutions: See demonstrations of Inflectra's cutting-edge AI tools like the ChatGPT plugin and Azure Open AI platform, designed to streamline your testing process.
Whether you're a developer, tester, or QA professional, this webinar will give you valuable insights into how AI is shaping the future of software delivery.
The Art of the Pitch: WordPress Relationships and SalesLaura Byrne
Clients don’t know what they don’t know. What web solutions are right for them? How does WordPress come into the picture? How do you make sure you understand scope and timeline? What do you do if sometime changes?
All these questions and more will be explored as we talk about matching clients’ needs with what your agency offers without pulling teeth or pulling your hair out. Practical tips, and strategies for successful relationship building that leads to closing the deal.
Transcript: Selling digital books in 2024: Insights from industry leaders - T...BookNet Canada
The publishing industry has been selling digital audiobooks and ebooks for over a decade and has found its groove. What’s changed? What has stayed the same? Where do we go from here? Join a group of leading sales peers from across the industry for a conversation about the lessons learned since the popularization of digital books, best practices, digital book supply chain management, and more.
Link to video recording: https://bnctechforum.ca/sessions/selling-digital-books-in-2024-insights-from-industry-leaders/
Presented by BookNet Canada on May 28, 2024, with support from the Department of Canadian Heritage.
GraphRAG is All You need? LLM & Knowledge GraphGuy Korland
Guy Korland, CEO and Co-founder of FalkorDB, will review two articles on the integration of language models with knowledge graphs.
1. Unifying Large Language Models and Knowledge Graphs: A Roadmap.
https://arxiv.org/abs/2306.08302
2. Microsoft Research's GraphRAG paper and a review paper on various uses of knowledge graphs:
https://www.microsoft.com/en-us/research/blog/graphrag-unlocking-llm-discovery-on-narrative-private-data/
Essentials of Automations: Optimizing FME Workflows with ParametersSafe Software
Are you looking to streamline your workflows and boost your projects’ efficiency? Do you find yourself searching for ways to add flexibility and control over your FME workflows? If so, you’re in the right place.
Join us for an insightful dive into the world of FME parameters, a critical element in optimizing workflow efficiency. This webinar marks the beginning of our three-part “Essentials of Automation” series. This first webinar is designed to equip you with the knowledge and skills to utilize parameters effectively: enhancing the flexibility, maintainability, and user control of your FME projects.
Here’s what you’ll gain:
- Essentials of FME Parameters: Understand the pivotal role of parameters, including Reader/Writer, Transformer, User, and FME Flow categories. Discover how they are the key to unlocking automation and optimization within your workflows.
- Practical Applications in FME Form: Delve into key user parameter types including choice, connections, and file URLs. Allow users to control how a workflow runs, making your workflows more reusable. Learn to import values and deliver the best user experience for your workflows while enhancing accuracy.
- Optimization Strategies in FME Flow: Explore the creation and strategic deployment of parameters in FME Flow, including the use of deployment and geometry parameters, to maximize workflow efficiency.
- Pro Tips for Success: Gain insights on parameterizing connections and leveraging new features like Conditional Visibility for clarity and simplicity.
We’ll wrap up with a glimpse into future webinars, followed by a Q&A session to address your specific questions surrounding this topic.
Don’t miss this opportunity to elevate your FME expertise and drive your projects to new heights of efficiency.
Search and Society: Reimagining Information Access for Radical FuturesBhaskar Mitra
The field of Information retrieval (IR) is currently undergoing a transformative shift, at least partly due to the emerging applications of generative AI to information access. In this talk, we will deliberate on the sociotechnical implications of generative AI for information access. We will argue that there is both a critical necessity and an exciting opportunity for the IR community to re-center our research agendas on societal needs while dismantling the artificial separation between the work on fairness, accountability, transparency, and ethics in IR and the rest of IR research. Instead of adopting a reactionary strategy of trying to mitigate potential social harms from emerging technologies, the community should aim to proactively set the research agenda for the kinds of systems we should build inspired by diverse explicitly stated sociotechnical imaginaries. The sociotechnical imaginaries that underpin the design and development of information access technologies needs to be explicitly articulated, and we need to develop theories of change in context of these diverse perspectives. Our guiding future imaginaries must be informed by other academic fields, such as democratic theory and critical theory, and should be co-developed with social science scholars, legal scholars, civil rights and social justice activists, and artists, among others.
Neuro-symbolic is not enough, we need neuro-*semantic*Frank van Harmelen
Neuro-symbolic (NeSy) AI is on the rise. However, simply machine learning on just any symbolic structure is not sufficient to really harvest the gains of NeSy. These will only be gained when the symbolic structures have an actual semantics. I give an operational definition of semantics as “predictable inference”.
All of this illustrated with link prediction over knowledge graphs, but the argument is general.
LF Energy Webinar: Electrical Grid Modelling and Simulation Through PowSyBl -...DanBrown980551
Do you want to learn how to model and simulate an electrical network from scratch in under an hour?
Then welcome to this PowSyBl workshop, hosted by Rte, the French Transmission System Operator (TSO)!
During the webinar, you will discover the PowSyBl ecosystem as well as handle and study an electrical network through an interactive Python notebook.
PowSyBl is an open source project hosted by LF Energy, which offers a comprehensive set of features for electrical grid modelling and simulation. Among other advanced features, PowSyBl provides:
- A fully editable and extendable library for grid component modelling;
- Visualization tools to display your network;
- Grid simulation tools, such as power flows, security analyses (with or without remedial actions) and sensitivity analyses;
The framework is mostly written in Java, with a Python binding so that Python developers can access PowSyBl functionalities as well.
What you will learn during the webinar:
- For beginners: discover PowSyBl's functionalities through a quick general presentation and the notebook, without needing any expert coding skills;
- For advanced developers: master the skills to efficiently apply PowSyBl functionalities to your real-world scenarios.
DevOps and Testing slides at DASA ConnectKari Kakkonen
My and Rik Marselis slides at 30.5.2024 DASA Connect conference. We discuss about what is testing, then what is agile testing and finally what is Testing in DevOps. Finally we had lovely workshop with the participants trying to find out different ways to think about quality and testing in different parts of the DevOps infinity loop.
Accelerate your Kubernetes clusters with Varnish CachingThijs Feryn
A presentation about the usage and availability of Varnish on Kubernetes. This talk explores the capabilities of Varnish caching and shows how to use the Varnish Helm chart to deploy it to Kubernetes.
This presentation was delivered at K8SUG Singapore. See https://feryn.eu/presentations/accelerate-your-kubernetes-clusters-with-varnish-caching-k8sug-singapore-28-2024 for more details.
2. W W W . Y O U T U B E . C O M / C H A N N E L / U C C E C V 3 G Q L Q C R T 8 M S 3 _ A R N 9 Q
For all course videos and material visit YouTube channel
W W W . L I N K E D I N . C O M / I N / M A H M O U D A B D E L L A T I F
3. 3
What is VLSI, Why it is Important,
Digital ASIC Design Flow..
Digital VLSI
The first half of Digital ASIC
Design flow
Logical Design
The second half of Digital ASIC
Design flow
Physical Design
Hardware Description languages
HDL
OUTLINE
4. 4
D I G I T A L D E S I G N F L O W
Digital VLSI
5. S E S S I O N 0 1
VLSI Industry
5
V L S I
https://www.linkedin.com/pulse/vlsi-industry-orientation-session-undergrad-egypt-abdellatif/
U S E F U L L I N K S
We can now fabricate millions of
transistors in a unit square inch piece of
silicon
Very Large Scale Integration (VLSI).
To facilitate this complex design and
fabrication of an IC, various automatic
tools and machines are available for
design and verification of an IC
A Electronic Design Automation (EDA)
software tools.
6. S E S S I O N 0 1
Digital ASIC Design Flow
6
V L S I
Logical
Design
Physical
Design
DESIGN SYNTHESIS LAYOUT TAPEOUT
7. 7
D I G I T A L D E S I G N F L O W
Logical Design
8. S E S S I O N 0 1
Logical Design
8
V L S I
• The flow starts with High-Level design Specification.
• The designer defines Area, Speed and Power constraints under which the goal has to be achieved.
Design
Specification
Logical Design
…. Design
…….. Design Specification
9. S E S S I O N 0 1
Logical Design
9
V L S I
• The designer starts thinking about the architectural design
• The design functionality is broken down to small pieces with clear understanding about the block
implementation
• Each design has objectives and constraints
• Functionality • Speed at which a design can operate • Power consumed by the design
• Testability of the design • Area of chip package
System
Architecture
Logical Design
…. Design
…….. System Architecture
10. S E S S I O N 0 1
Logical Design
1 0
V L S I
RTL
Design
RTL, Register Transfer Level, describing the functional behavior using HDL, hardware description
languages, VHDL, Verilog or SystemVerilog .
Logical Design
…. Design
…….. RTL Design
11. S E S S I O N 0 1
Logical Design
1 1
V L S I
Functional Verification, verifying the functionality using simulation.
Functional
Verification
Logical Design
…. Design
…….. Functional Verification
12. S E S S I O N 0 1
Logical Design
1 2
V L S I
Logic
Synthesis
• The first step of converting the RTL to Gate Netlist.
• Synthesis tool takes a Standard Cell Library, Constraints, RTL codes and generate Gate Level
Netlist.
• Timing, Power and Area constraints are guiding synthesis tools to achieve design goals.
Logical Design
…. Synthesis
…….. Logic Synthesis
13. S E S S I O N 0 1
Logical Design
1 3
V L S I
Design
For Test
DFT, this step is for preparing the design for testability. Scan insertion is a common technique that
helps to make all registers in the design controllable and observable.
Logical Design
…. Synthesis
…….. Design for Testability
14. S E S S I O N 0 1
Logical Design
1 4
V L S I
This is used to verify the functionality of gate netlist against the RTL description using formal
verification techniques.
Equivalence
Checking
Logical Design
…. Synthesis
…….. Equivalence Checking
15. S E S S I O N 0 1
Logical Design
1 5
V L S I
Static
Timing
Analysis
STA, static timing analysis, a method of checking the ability of the design to meet the timing
requirements statically without simulation.
The designer is responsible of specifying 'Timing Constraints' to model how the design needs to be
constrained & the STA tools check that the design meets the timing requirements.
The designer uses an industry standard format 'SDC' Synopsys Design Constraints.
STA on this stage acts as the bridge between logical and physical design
Logical Design
…. Synthesis
…….. Static Timing Analysis
16. 1 6
D I G I T A L D E S I G N F L O W
Physical Design
17. S E S S I O N 0 1
Physical Design
1 7
V L S I
Floor
Planning
• Floor planning is the starting step in ASIC physical design
• The logical blocks locations are determined considering many optimization factors to account for Area,
Speed and Power
• These parameters are decided in this stage.
- Die size, core size of the chip - I/O pad’s location
- Plan for power
Physical Design
…. Layout
…….. Floor Planning
18. S E S S I O N 0 1
Physical Design
1 8
V L S I
Placement
• Assigning exact locations for the blocks within the chip core area
• A placement tool takes a given synthesized circuit netlist together with a technology library and
produces a valid placement layout
Physical Design
…. Layout
…….. Placement
19. S E S S I O N 0 1
Physical Design
1 9
V L S I
Clock
Tree
Synthesis
• Clock Tree Synthesis ‘CTS’ is the step which is responsible for distributing the clock and reduce
clock skew between different parts of the design by insertion of buffers or inverters along the
clock paths of ASIC design.
Physical Design
…. Layout
…….. Clock Tree Synthesis
20. S E S S I O N 0 1
Physical Design
2 0
V L S I
Routing
• Routing the design is the final step to generate the layout.
• During the physical design, STA may be done multiple times to perform a more accurate timing
analysis.
•
Physical Design
…. Layout
…….. Routing
21. S E S S I O N 0 1
Physical Design
2 1
V L S I
Signoff
LVS
Two steps are needed to verify the layout
• LVS, Layout versus Netlist, matching the layout with the gate level netlist generated after
synthesis.
Physical Design
…. Tapeout
…….. LVS
22. S E S S I O N 0 1
Physical Design
2 2
V L S I
Signoff
DRC
• DRC, Design Rule Checking, All rules laid out by the foundry where it will be fabricated into a chip
are adhered
• For Example
If two metal wires are too close together on the same layer, they may short during the
manufacturing process
Physical Design
…. Tapeout
…….. DRC
23. S E S S I O N 0 1
Physical Design
2 3
V L S I
Signoff
STA
• Signoff Static Timing Analysis is performed again at this phase.
Physical Design
…. Tapeout
…….. Signoff STA
24. S E S S I O N 0 1
Physical Design
2 4
V L S I
GDSII
Release
• Fabs manufacture ICs based on the GDSII
• GDSII stream format is the industry standard for data exchange of IC layout.
• This Digital ASIC design flow is referred to as RTL2GDSII flow & the process to generate GDSII is
termed as Tapeout.
Physical Design
…. Tapeout
…….. GDSII Release
25. 2 5
D I G I T A L D E S I G N F L O W
Hardware Description
Languages
26. S E S S I O N 0 1
Hardware Description Language
2 6
V L S I
There are two popular widely used HDL languages
• VHDL
- first version came in 1987 followed by versions 1993, 2000, 2002, 2006 and 2008
- more difficult to learn
- strongly typed
- 85% of FPGA designs done in VHDL
• Verilog
- first version in 1985 followed by versions 1995, 2001, 2005 and SystemVerilog
- easier and simpler to learn
- weakly typed
- 85% of ASIC designs done with Verilog
If you learn VHDL then you can learn Verilog in few weeks
If you learn Verilog then it may be hardware to accept learning VHDL
27. S E S S I O N 0 1
HDL Levels of Abstraction
2 7
V L S I
Used to describe algorithms of the
design.
This is the highest level of abstraction
possible using the HDL.
The top level function of the design is
described and it is useful mainly at
the system analysis, simulation and
partition stage.
Behavioral Design
RTL design comes in between behavioral.
It has detailed description of the circuit
with respect to the clocks and data flow.
RTL Design
This is closer to physical representation of
a circuit and has almost zero abstraction.
This form of HDL is generally the output of
a synthesis tool which takes RTL design
as input.
Gate Level Netlist
MODELING
RTL
Design
Netlist
28. S E S S I O N 0 1
HDL STRUCTURE
2 8
V L S I
PACKAGE
DECLARATION
____________
PACKAGE BODY
(used for functions,
constants,
components,…)
ENTITY
(Interface Description)
ARCHITECTURE
(Functionality)
Concurrency Nature
You have to think in Hardware when you write your
VHDL/Verilog code
In this code, both AND & OR gates works at the same
time and any update on x reflects on e at the same time
BEGIN
x <= A AND B;
e <= x OR y;
END;
X
y
e