The document outlines the ASIC and FPGA design flows, detailing the steps involved from design entry to post-layout simulation for ASICs and from design entry to implementation for FPGAs. It describes various stages including logic synthesis, system partitioning, floorplanning, and routing, as well as the architecture of FPGAs consisting of logic units and programmable interconnects. Additionally, it highlights the significance of proper simulation and implementation tools in ensuring design accuracy and efficiency.

2. ASIC Design Flow
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3. Contd..
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1. Design entry - Using a hardware description
language ( HDL ) or schematic entry
2. Logic synthesis - Produces a netlist - logic cells and
their connections
3. System partitioning - Divide a large system into
ASIC-sized pieces
4. Pre-layout simulation - Check to see if the design
functions correctly
5. Floorplanning - Arrange the blocks of the netlist on
the chip
6. Placement - Decide the locations of cells in a block
7. Routing - Make the connections between cells and
blocks
8. Extraction - Determine the resistance and
capacitance of the interconnect

4. 1.Design Entry
 The designer starts the design with a text description
or system specific language like HDL, C language etc.
Logic synthesis is the process of converting a high-
level description of design into an optimized gate-level
representation.
It generally helps to produce the netlist consisting the
description and interconnection of logic cells.
2.Logic Synthesis

5. 3.System Partitioning
Goal: Partition of a System into number of ASIC’s
Objective: Minimize the number of external connection
between each ASIC. Keep each ASIC smaller than max
size.
Partitioning of a large design into a small ASIC design
takes place.
This is done mainly to separate different functional
blocks and also to make placement and routing easier.

6. 4.Pre-Layout Simulation
Pre-layout Simulation allows checking whether the design functions correct
or not.
Gate level functionality and timing(Delay) details can be verified.
It is also called as Functional Verification.
5.Floorplanning
Goal: Calculate the size of blocks and assign them locations.
Objective: Keep highly connected blocks physically close to each other.
It is the first step in the physical design flow.
Arrange the blocks of the netlist on the chip.
It is the Tentative placement of its major functional blocks.

7. Slicing Floorplan:
One that can be obtained by
repetitively subdividing (slicing)
rectangles horizontally or vertically.
Non-Slicing Floorplan:
One that may not be obtained by
repetitively subdividing alone.

8. 6.Placement
Goal: Assign the interconnect areas and the
locations of all the logic cells with in the flexible
block.
Objective: Minimize the ASIC area and the
interconnects.
Allows the placement of cells present in the block.
Assigns exact locations for various circuit
components within the chip’s core area.
Placement is much more suited to automation
than Floorplanning.

9. 7.Routing
Make the connections between cells and blocks.
It is the process of creating physical connections based
on logical connectivity. signal pins are connected by
routing metal interconnects.
Global Routing:
Goal: Determine the location of all the interconnects.
Objective: Minimize the total interconnect area.
Wire segments are tentatively assigned (embedded)
within the chip layout .

10. Detailed Routing:
Goal: Completely route all the interconnects
on the chip.
Objective: Minimize the total interconnect
length used.
Find actual geometric layout of each net
within assigned routing regions.

11. 8.Circuit Extraction
Determine the resistance and capacitance of the
interconnect.
Basically it’s link between two domains.
1.Physical Domain
2.Electrical Domain
Physical domain -it’s uses the physical information like
shapes of the design.
Electrical domain-provide the electrical information's
(connectivity of C,R,L)
9.Postlayout simulation
Post-layout simulation you can extract the parasitic interconnect.
To verify that your functional stimulus still works with accurate timing.

12. FPGA Design Flow
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13. FPGA Design Flow
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• Design entry: The design is described in a formal hardware description
language (HDL). The most common HDLs are VHDL and Verilog. Test
environment design. This step involves writing of test environments and
behavioral models. They are later used to ensure that the HDL description of
a device is correct.
• RTL Design and Simulation: A digital circuit’s RTL design is an intermediate
representation that concentrates on the data flow between registers and the
operations carried out on that data. Before proceeding to the synthesis and
implementation phases, the functionality and performance of the design are
confirmed via RTL simulation.
• The RTL simulation tools ModelSim, XSIM, and VCS are commonly used.
Functional and timing simulations, made possible by these tools, aid in
the early detection and correction of design flaws and performance
bottlenecks.

14. FPGA Design Flow
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• Synthesis: This step involves translating the design from code, which has
been entered, into an actual circuit with components like gates, flip flops,
and multipliers, among others. In essence, your input HDL is transformed
into a netlist that enumerates the logic components and interconnects
required in the particular hierarchy for your project.
• As soon as you feed in your HDL-based design, the procedure starts with a
syntax check. Then, it is made faster to implement by reducing the amount
of logic, getting rid of unnecessary logic, and shrinking the design’s overall
size. The final stage involves mapping out the technology by integrating
the design with the logic, calculating the corresponding time, and creating
the design netlists, which are then saved.
• Specialized synthesis tools are used for FPGA synthesis. FPGA synthesis
tools are developed, marketed, and sold by EDA companies Cadence,
Synopsys, and Mentor Graphics.

15. FPGA Design Flow
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• Implementation: This stage, which consists of three steps translation
map, place & route—will determine the layout of your design. The FPGA
vendors supply the tools used in this step because they are the experts at
converting a synthesized netlist into an FPGA.
• The tools’ initial step is to compile all user-specified constraints along with
the netlist files. These limitations may relate to the pin assignments and
locations, timing specifications like the maximum delay, or the clock’s
input period.
• The implementation is then mapped out by the tool by contrasting the
resources that are actually available on the FPGA that are being used with
the resource requirements that are specified in the files. The circuit is
separated into sub-blocks, or logic blocks, or elements. Your entire design
is therefore “mapped out” into the FPGA and put into designated logic
blocks.
• The next stage involves connecting and routing each signal between each
logic block and each IO block in line with the user-specified constraints.

16. FPGA Design Flow
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• Implementation: This stage, which consists of three steps translation
map, place & route—will determine the layout of your design. The FPGA
vendors supply the tools used in this step because they are the experts at
converting a synthesized netlist into an FPGA.
• The tools’ initial step is to compile all user-specified constraints along with
the netlist files. These limitations may relate to the pin assignments and
locations, timing specifications like the maximum delay, or the clock’s
input period.
• The implementation is then mapped out by the tool by contrasting the
resources that are actually available on the FPGA that are being used with
the resource requirements that are specified in the files. The circuit is
separated into sub-blocks, or logic blocks, or elements. Your entire design
is therefore “mapped out” into the FPGA and put into designated logic
blocks.
• The next stage involves connecting and routing each signal between each
logic block and each IO block in line with the user-specified constraints.

17. FPGA Architecture
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• An FPGA’s basic structure consists of logic units, programmable
interconnects, and memory. The placement of these blocks is unique to
each manufacturer.
• Each FPGA includes three important features that can be found at the
heart of modern-day FPGA architecture:
A) Logic Blocks
B) Routing

18. FPGA Architecture
Logic Blocks
•An FPGA’s logic blocks can be designed to provide functionality as simple as that
of a transistor or as complicated as that of a microprocessor. It may be used to
implement a variety of sequential and combinational logic functions.
•Modern FPGAs are made up of a variety of distinct blocks, such as dedicated
memory blocks and multiplexers. To control the precise function of each piece,
configuration memory is used across the logic blocks. Any of the following can
be used to implement logic blocks in an FPGA:
•Transistor pairs
•combinational gates like basic NAND gates or XOR gates
•n-input Lookup tables
•Multiplexers
•Wide fan-in And-OR structure

19. FPGA Architecture
Routing
• In FPGAs, routing is made up of wire segments of variable lengths that are
joined by electrically programmable switches. The length and number of wire
segments utilized for routing determine the density of logic blocks used in an
FPGA.
• The number of connecting segments utilized is often a compromise between
the density of logic blocks employed and the amount of space taken up by
routing.
• To complete a user-defined design unit, programmable routing connects logic
blocks and input/output blocks. Multiplexers, pass transistors, and tri-state
buffers make up this circuit. In a logic cluster, pass transistors and
multiplexers are utilized to connect the logic units.
I/O blocks
• An input/output (I/O) block is a type of input/output device that can be used
for both input and output. Edge-triggered D flip flops are used in both the
input and output channels. The goal of the I/O blocks is to give a user
interface from the outside world to the internal architecture of the FPGA.
These cells take up a lot of space on the FPGA.
• The design of I/O programmable blocks is very difficult due to the large
variances in supply and reference voltages. In I/O architecture design, the

20. Applications
Field-Programmable Gate Arrays (FPGAs) are versatile integrated circuits that
can be configured and reconfigured to implement a wide range of digital circuits
and functions. Here are some common applications of FPGAs: