- A latch is the simplest memory element that can be constructed from standard logic gates and allows information to be stored. It has two stable states: SET and RESET. - NAND and NOR gates can be used to create SR (Set-Reset) latches that store a bit. The latches change state based on active-low or active-high signals on the SET and RESET inputs. - Mechanical switches bounce upon contact, which can cause errors. Debouncing circuits use latches to hold the switch state until bouncing stops to avoid erroneous signals. - Clocked flip-flops (FFs) add a clock input to synchronize state changes. D-type FFs sample the D

1. Sequential
Circuits
Memory Elements

2. Memory Element
• A latch is the simplest memory element that
can be constructed from standard logic gates.
• The manner in which the logic gates are
connected permit information to be stored.
Output Condition Output State
Q = 1; Q’ = 0 SET State
Q= 0; Q’ = 1 RESET or CLEAR
State
Q
Q (Q’)
LatchInputs
Normal
Output
Inverted
Output
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3. NAND SR Latch
• For the NAND SR Latch, the
SET and RESET inputs are
Active-LOW.
• When the SET input is 0, Q is
set to 1 i.e. SET state
• When the RESET input is 0, Q
is set to 0 i.e. RESET state
S
R Q’
Q
NAND Latch
R
S Q
Q’
Simplified
Block Symbol
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4. Waveform for NAND SR Latch
1
0
SET Input
1
0
RESET
1
0
Q Ouput
1
0
Q' output
Set Reset Hold Set Hold
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5. NOR SR Latch
R
S Q
Q’
Simplified
Block Symbol
• For the NOR SR latch, the
SET and RESET inputs are
Active-HIGH
• When the SET input is 1, Q is
set to 1 i.e. SET state
• When the RESET is 1, Q is
set to 0 i.e. RESET state
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6. Waveform for NOR SR Latch
1
0
SET Input
1
0
RESET
1
0
Q Ouput
1
0
Q' output
Set Reset Hold Set Hold
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7. Switch Bounce Problem
• Most mechanical switches generate some "bounce“. For normal
switches, this can last from as little as a fraction of a millisecond (ms),
to as long as 50 ms.
• This is usually not a problem if you are merely turning on a light.
However, for digital logic devices, random “bouncing” can create
problems. For instance, every time when a button is pressed to
increment a counter , instead of incrementing by one, several counts
could have been added causing counting errors.chandran Digital Electronics 8

8. De-bouncing a Mechanical Switch
• When the pole is at
position 1, The latch is in a
reset state (Q = ‘0’) with
Set = ‘1’ and Reset = ‘0’
• When the switch is toggled
and touches Position 2,
the Set becomes ‘0’ and
Reset becomes ‘1’
• Hence, Q = ‘1’
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9. De-bouncing a Mechanical Switch
• The pole will bounce off from Position 2.
• As the pole is now not touching either throw, both Set
and Clear became ‘1’. Therefore, Q remains
unchanged at ‘1’ during this time.
• When the pole swing back to Position 2 and bounce
off again, the output of the latch remains unchanged
at ‘1’.
• The latch will alternate between the set (Set = 0,
Clear =1) and memory (Set = 1, Clear = 1) states until
the bouncing stops.
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10. Experimental Results
Before:
Presence of Unwanted
Voltage Changes
After:
Unwanted Voltage
Changes Minimized
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11. D-Type Latch
Input Output
EN D Q
0 X Q0 (No change)
1 0 0
1 1 1
"X" indicates "don't care"
Q0 states Q just prior to EN going low
EN
D
Q
T2 T3 T4T1
“Latched”
at Q=0
“Transparent”
at Q=D
“Latched”
at Q=1
“Transparent”
at Q=D
“Latched”
at Q=0
EN
D Q
Q
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12. Clocked Flip-Flops (FFs)
Clock Input
• The clock signal is generally a regular rectangular
pulse train or square wave as shown below.
• Typically labeled as CLK, CK or CP
• Edge-triggered - It is activated by a signal transition .
This is indicated by the presence of a small triangle
on the CLK input.
CLK
Q
Q
CLK is activated by
Negative-going transition (NGT)
CLK is activated by
Positive-going transition (PGT)
CLK
Q
Q
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13. D Flip-flop
D CLK Q
0 0
1 1CLK
D Q
Q
D
CLK
0
Q
0
1
0
1
1
Note that CLK is activated
on the positive going
transition in this case
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14. EN
D
Q
EN
D
Latch
QD
Q
CLK
D
Q
Positive Edge
D Flip Flop
CLK
QD
Q
CLK
D
Q
Negative Edge
D Flip Flop
CLK
D Q
Q
D Latch vs. D Flip-flop
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15. Experimental Results
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16. Divide by 4 on single D Flip Flop IC
Vcc
Gnd
CLK
Output
D D
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