The document presents a detailed overview of flip-flops, which are bi-stable multivibrators used in digital circuits to store binary data (0 or 1). It outlines various types of flip-flops including SR, JK, and D flip-flops, and explains their functionalities, construction using NAND or NOR gates, and behaviors in relation to clock signals. The presentation emphasizes their applications in memory circuits, logic control devices, and counters.

1. WELCOME…

2. Daffodil Institute of IT
Presentation on Flip-Flops
Manimay Adhikary ;ID:180084
Asadullahil Galib ;ID:180094
Presented By:
MD Hasan Shemon ; ID:180088
Md Hasan Al Zabed; ID:180062
Nawshad Jaman ; ID:180066
Presented to
Tahmina Aktar Trisha
Lecturer
Department of Computer Science &
Engineering
Daffodil Institute of IT(DIIT)
64/3 & 64/4 Lake Circus (2nd-5th floor)
Mirpur Road Dhaka-1205, Bangladesh

3. What is Flip flop?
• In digital circuits, the flip-flop, is a kind of bi-stable
multivibrator.
• It is a Sequential Circuits / an electronic circuit which
has two stable states and thereby is capable of
serving as one bit of memory , bit 1 or bit 0

4. Introduction – Flip Flop
• They are 1 (HIGH) or 0 (LOW).
• Whenever we refer to the state
of flipflop, we refer to the state
of its normal output (Q).
• More complicated Flip flop use a
clock as the control input. These
clocked flip-flops are used
whenever the input and output
signals must occur within a
particular sequence
•They have two stable conditions
and can be switched from one to
the other by appropriate inputs.

5. Introduction: Types Of Flip Flop
• 1. SR Flip Flop
a.SR Flip Flop Active Low = NAND gate Latch
b. SR Flip Flop Active High = NOR gate Latch
• 2. Clocked SR Flip Flop
• 3. JK Flip Flop
• 4. JK Flip Flop With Pre-set And Clear
• 5. T Flip Flop
• 6. D Flip Flop
• 7. Master-Slave Edge-Triggered Flip-Flop
The Used of Flip Flop:
 For Memory circuits
 For Logic Control Devices
 For Counter Devices
 For Register Devices

6. SR Flip Flop
 The most basic Flip Flop is called SR Flip Flop
 These basic Flip Flop circuit can be constructed using two NAND
gates latch or two NOR gates latch.
 SR Flip FlopActive Low = NAND gate Latch
 SR FlipFlop Active High = NOR gate Latch
Reset
Set
The SR Flip Flop has two inputs,SET (S) and
RESET (R).
The SR Flip Flop has two outputs, Q and Q’
 The Q output is considered the normal output
and is the one most used.
 The other output Q’ is simply
the compliment of output Q.
R
S Q
Q’

7. SR Flip Flop - NAND GATE LATCH
 The NAND gate version has two inputs,
SET (S) and RESET (R).
 Two outputs, Q as normal output and Q’
as inverted output and feedback
mechanism.
 The circuit outputs depends on the inputs
and also on the outputs.
 Thee SET and RESET inputs are active LOW.
The SET input will set Q = 1 when SET is 0
(LOW).RESET input will reset Q = 0 when RESET is 0
(LOW)

8. SR Flip Flop - NOR GATE LATCH
• The latch circuit can also be constructed
using two NOR gates latch.
• The construction is similar to the NAND
latch except that the normal output Q and
inverted output Q’ have reversed
positions.
• The SET and RESET inputs are Active HIGH.
•The SET input will set Q = 1 when SET is 1 (HIGH).
RESET input will reset Q when RESET is 1 (HIGH).

9. The CLOCK
• When the clock changes from a LOW state to a HIGH state, this
is called the positive-going transition (PGT) or positive edge
triggered.
• When the clock changes from a HIGH state to a LOW state, it is
called negative going transition (NGT) or negative edge
triggered.
0
1
Rising (positive)
Edge
Falling (negative)
Edge
Positive Level
Negative Level

10. Clocked SR Flip Flop
• Adding two NAND gates to the
basic S - R NAND latch gives
the clocked
S – R latch.
• Has a time sequence behavior
similar to the basic S-R latch
except that the S and R inputs
are only observed when the
line C is high.
• C means “control” or “clock”.
S
R
Q
Q
C

11. Clocked S - R Flip Flop
S
R
Q
Q
C
• The Clocked S-R Latch can be described by a table:
• The table describes
what happens after the
clock [at time (t+1)]
based on:
– current inputs (S,R) and
– current state Q(t).
Q(t) S R Q(t+1) Comment
0 0 0 0 No change
0 0 1 0 Clear Q
0 1 0 1 Set Q
0 1 1 ??? Indeterminate
1 0 0 1 No change
1 0 1 0 Clear Q
1 1 0 1 Set Q
1 1 1 ??? Indeterminate

12. JK Flip Flop
● The JK Flip-Flop has three inputs –Clock(Ck)
---denoted by the small arrowhead – J and
K
● Similar to the SR Flip-Flop
– J corresponds to S: J = 1 Q+ = 1
– K corresponds to R: K = 1 Q+ = 0
● Different from the SR Flip-Flop in that the
input combination J = 1, K = 1 is allowed.
– J = K = 1 causes the Q output to toggle after
an active clock edge.
JK Flip Flop – Truth Table:

13. JK Flip Flop Timing Diagram with Preset and Clear:

14. D Flip Flop
• Also Known as Data Flip flop
• Can be constructed from RS Flip Flop or
JK Flip flop by addition of an inverter.
• Inverter is connected so that the R input
is always the inverse of S (or J input is
always complementary of K).
• The D flip flop will act as a storage
element for a single binary digit (Bit).
D Flip Flop – Symbol:

15. Truth Table of D Flip floop:

16. Thank you for your Attention