Reliability and yield

Reliability and yield

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  MEMORY ROM(READ ONLYMEMORY) PROM(PROGRAMMABLE ROM) EPROM(ERASABLE PROGRAMMABLE ROM) EEPROM (ELECTRICALLY ERASABLE PROM) FLASH ROM RAM(RANDOM ACCESS MEMORY) SRAM( STATIC RAM) DRAM(DYNAMIC RAM) Classification of memory-
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  There are twoconditions that must be satisfied in order for VLSI to be useful, growing technology i.e Yield & Reliability. Firstly , the fabricated circuits must be capable of being produced in large quantities at costs that are competitive with other alternative methods of achieving the circuit and systems function. Secondly, the circuits must be capable of performing their function throughout their intended life .
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   We defineYield, Y= (No. of Good chips on wafer)/(total no. of chips).It is denoted by Y. A chip with no manufacturing defects is called good chips Yield heavily drives the cost of the chip so we obviously want a high yield. However, yields can be very low initially (i.e., <10%). A mature process tries to hit ~90% yield.
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  VLSI Defects
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  The term reliabilityis defined as , the probability that an item will perform a required function under stated conditions for a stated period of time. The “required function” must include a definition of satisfactory operation and unsatisfactory operation or failure. The program’s output simply state “good” or “bad”. The “stated conditions” in the definition comprise with total physical environment including the mechanical, thermal, and electrical conditions of expected use. The “stated period of time” is the time during which satisfactory operation is required.
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  Memories ,both SRAMand DRAM, are operating under low signal-to-noise conditions. Maximizing the signals while minimizing the noise contributions to achieve stable memory operation .Another problem plaguing memory design is the low yield due to structural and intermittent defects. A tremendous effort is being made to produce memory cells that generate as large a signal as possible per unit area. Notwithstanding this effort ,the produced signal quality decreases gradually with an increase in density.  At the same time , the increased integration density raises the noise level, due to the intersignal coupling.
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  With increasing diesize and integration density, a reduction in yield is to be expected ,notwithstanding the improvements in the manufacturing process. Causes for malfunctioning of a part can be both material defects and process variations. Memory designers use two approaches to combat low yields and to reduce the cost of these complex components: redundancy and error correction. The latter technique has the advantage that it also addresses the occasional occurrence of a soft error.
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   Memories havethe advantage of being extremely regular structures. Providing redundant hardware is easily accomplished. Defective bit lines in a memory array can be replaced by redundant ones , and the same holds for word lines.  When a defective column is detected during testing of the memory part , it is replaced by a space one by programming the fuse bank connected to the column decoder. A typical way of doing so is to blow the fuse bank connected to the column decoder. Figure- Redundancy in memory array increases the yield
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   A typicalway of doing so is to blow the fuses using a programming laser or pulsed current. Laser programming has a minimal impact on memory performance and occupies small chip area. It does not require special equipment and increased wafer handling time. The pulsed current approach can be executed by a standard tester ,but bears larger overhead .A similar approach is followed for the defective word lines. Whenever a failing word line is addressed ,the word redundancy system enables a redundant word line.  In modern memories ,as many as over 100 defective elements can be replaced by spare ones for an additional overhead of less than 5. Even embedded SRAM memories, to be used in systems on-a-chip ,now come with redundancy.
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  Redundancy helps correctfaults that affect a large section of the memory such as defective bit lines or word lines. It is ineffective when dealing with scattered point errors such as local errors caused by material defects . Achieving a reasonable fault coverage requires too much redundancy under these circumstances and results in a large area overhead. A better approach to address these faults is to use error correction.  The idea behind this scheme is to use redundancy in the data representation so that an erroneous bit(s) can be detected and even corrected. Adding a parity bit to data word, for instance, provides a way of detecting(but not correcting) an error.
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   An importantobservation is that error correction not only combats technology-related faults, but is also an effective way of dealing with soft errors and time variant faults.