ROUGH DOC.437

MEMORYRELABILITY USINGDECIMALMATRIX CODE 2016
1 Dept. of E.C.E KHIT
CHAPTER - 1
INTRODUCTION
The general idea for achieving error detection and correction is to add some redundancy (i.e.,
some extra data) to a message, which receiver can use to check consistency of the delivered
message, and to pick up data determined to be corrupt. Error-detection and correction scheme
can be either systematic or non-systematic: In a systematic scheme, the transmitter sends the
unique data, and attaches a fixed number of check bits (or parity data), which are derived from
the data bits by some deterministic algorithm. If only the error detection is required, a receiver
can simple apply the same algorithm to the received data bits and compare its output with the
receive check bits; if the values do not match, an error has occurred at some point throughout the
transmission. Error-correcting codes are regularly used in lower-layer communication, as well as
for reliable storage in media such as CDs, DVDs, hard disks and RAM. In a system to uses a
non-systematic code, the unique message is transformed into an encoded message that has at
least as many bits as the unique message. The major challenges posed for future memory design
is the problem of soft errors and high power consumption. As process technology scales to small
nanometers, high-density, low cost, high performance integrated circuits, characterized by high
operating frequencies, low voltage levels and small noise margins will be increasingly
susceptible to temporary faults. In very deep sub-micron technologies single-event upsets like
atmospheric neutrons and alpha particles severely impact field-level product reliability, not only
for memory, but for logic also. When these particles hit the silicon bulk, they create minority
carriers which if collected by the source/drain diffusions, could change the voltage level of the
node. Transient faults are also a major concern in space applications, with potentially serious
consequences for the spacecraft, including loss of information, functional failure or loss of
control . Although SEU is the major concern in space and terrestrial applications, multiple bit
upsets (MBU) have also became important problems in designing memories because of the
following:
1) The error rate of memories increased due to the continuing technology shrinkage. Therefore
the probability of having multiple errors increases.

2) MBUs can be induced by direct ionization or nuclear recoil after passing a high-energy ion.
3) The experiments in memories under proton and heavy ions fluxes in show that the probability
of having multiple errors is increased when the size of memory is increased. Unfortunately,
packaging and shielding cannot effectively be used to shield against SEUs and MBUs since they
may be caused by neutrons which can be easily penetrate through packages. In order to maintain
a good level of reliability, it is necessary to protect memory cells with protection codes.
Hamming code and Odd Weight code are largely used to protect memories against SEU because
of their efficient ability to correct single upsets with a reduced area and performance overhead.
However, multiple upsets cause by a single charged particle can provoke errors in the system
protected by these single-error correcting codes. In the other hand, Reed-Muller is another error
correcting code able to cope with multiple upsets. It has a wide range of digital applications
including: storage systems, wireless or mobile communications and high speed modems.
LITERATURE REVIEW
Improved decoding algorithm for high reliable reed muller coding
C. Argyrides &D. K. Pradhan Sep 2007
The CMOS technology scaling to nm, low cost, high density, high speed integrated
circuits with low supply voltage has increased the probability of fault occurrence in the
memories. This lead to the major reliability concern especially increases SRAM memory failure
rate. Some commonly used mitigation techniques are triple modular redundancy, and error
correction codes (ECCs). Soft errors are the major issue in the reliability of memories. Soft error
will not damage the hardware, they only damage the data that is being processed. If detected, soft
errors are corrected by rewriting corrected data in the place of erroneous data. Highly reliable
system uses error correction approach, however in many systems it is difficult to correct data, or
even impossible to detect error. To prevent soft errors from causing corruption in the data stored
error correction codes are used such as matrix code, hamming etc. when ECC is used, data are
encoded when written in the memory and data are decoded when read from the memory. Thus
the encoding and decoding process possess a vital impact on the memory access time and

complexity. Multiple cell upsets have become the reliability concern in some application apart
from single cell upset. The BCH code,reed Solomon code etc are used to deal with MCUs,but the
area, power and delay overhead of these codes are high due to the complex encoding and
decoding architecture. The decimal matrix code uses encoder reuse technique which uses
encoder as a part of the decoder and thus reduces the area overhead and complexity.DMC
enhances the reliability of the memory by improving the error correction capability.
Parallel double error correcting code design to mitigate multi-bit upsets in srams
R.Naseerand J. Draper, Sep 2008
During transmission of information via communication networks data may get corrupted
due to physical/logical faults which would bring the whole system down to destructive failures.
So, every communication system has to be facilitated with testing and fault tolerance
equipments, to provide safe and sound communication streamlines. So far, many error detection
and error correction codes, for different purposes, have been developed. To name some, Parity
codes, Burger codes and Checksums for error detection, Cyclic Redundancy codes, Hamming
codes, Residue codes, Nordstrom-Robinson codes and Turbo codes for error correction, and
BCH codes and modified Residue codes for multi error correction were developed. These codes
may perform well in some cases, but not in all conditions and environments. However, due to
steady increase of size, speed and complexity of data transmission the total efficiency has been
reduced. Therefore, vital need for creation of new methods and revising the old techniques is
commonly sensed.
Generally, some of the faults are due to magnetic fields, electrical influences and climate
impacts, such as thunders, hurricane, solar rays and etc. They can appear in both internal (e.g.,
inter node computer communications) and external communications (e.g., satellite
communications, digital telecommunications or wireless networks). Traditionally memories
employ Single-Error Correcting and Double-Error Detecting (SEC-DED) methods. But in
telecommunications with large data-packets, systems need error correcting methods along with
multi-error detecting techniques. Hence the task of every receiver system is to check errors and
then fixing the problem by requesting for re transmission, correction or using other means.

In this regard, many methods have been developed by different designers, which were
good only in specific conditions and environments.
Content addressable memory (cam) circuits and architectures:
K. Pagiamtzis and A. Sheikholeslami, Mar 2003
This paper survey recent developments in the design of large-capacity content-
addressable memory (CAM). A CAM is a memory that implements the lookup-table function in
a single clock cycle using dedicated comparison circuitry. CAMs are especially popular in
network routers for packet forwarding and packet classification, but they are also beneficial in a
variety of other applications that require high-speed table lookup. The main CAM-design
challenge is to reduce power consumption associated with the large amount of parallel active
circuitry, without sacrificing speed or memory density. In this paper, we review CAM-design
techniques at the circuit level and at the architectural level. At the circuit level, we review low-
power match line sensing techniques and search line driving approaches. At the architectural
level we review three methods for reducing power consumption

Most memory devices store and retrieve data by addressing specific memory locations. As a result,
this path often becomes the limiting factor for systems that rely on fast memory accesses. The time required
to find an item stored in memory can be reduced considerably if the item can be identified for access by its
content rather than by its address. A memory that is accessed in this way is called content-addressable
memory or CAM. CAM provides a performance advantage over other memory search algorithms, such as
binary or tree-based searches or look-aside tag buffers, by comparing the desired information against the
entire list of pre-stored entries simultaneously, often resulting in an order-of-magnitude reduction in the
search time. CAM is ideally suited for several functions, including Ethernet address lookup, data
compression, pattern-recognition, cache tags, high-bandwidth address filtering, and fast lookup of routing,
user privilege, and security or encryption information on a packet-by-packet basis for high-performance data
switches, firewalls, bridges and routers. This article discusses several of these applications as well as
hardware options for using CAM.
Reliability analysis of h-tree random access memories implemented with built in current sensors and
parity codes for multiple bit upset correction
C. Argyrides, R. Chipana, F. Vargas, and D. K. Pradhan, Sep 2011
This paper presents an efficient technique for designing high defect tolerance Static Random Access
Memories (SRAMs) with significantly low power consumption. The new approach requires drastically lower
area overhead, simpler encoding and decoding algorithms, and zero fault-detection latency time for multiple
error detection when compared to conventional techniques. The approach is based on the use of Built-In-
Current-Sensors (BICS) to detect the abnormal current dissipation in the memory power-bus to improve the
reliability of H-Tree SRAM memories. This abnormal current is the result of a single-event upset (SEU) in
the memory, and it is generated during the inversion of the state of the memory cell being upset.
Furthermore, the basic infrastructure provided by this approach can also be used to dynamically reconfigure
the SRAM memory to save power, and to leverage fabrication yield.
A novel feature of neutron-induced multi-cell upsets in 130 and 180 nm SRAMs
Y. Yahagi, H. Yamaguchi, E. Ibe, H. Kameyama, M. Sato, T. Akioka, and S. Yamamoto, aug 2007
Due to reduction in device feature size and supply voltages the probability of soft-errors in Finite State
Machines’ (FSMs) states has increased dramatically, and the protection against both Single Event Upset

(SEU) and Multiple Bit Upsets (MBUs) soft-errors demand for design of fault tolerant FSMs that detect and
correct more than one error. Redundancy has been mostly preferred methodology for Error Detection and
Correction (EDAC), however selection of one EDAC method is a trade-off between performance and
hardware overhead. In this paper, we present an SEU/MEU hardening approach for FSMs’ states through
‘binary-gray’ code for state encoding and a self-checking process that can detect and correct the soft errors
in FSM states. Here 8 bit register is used to store the FSM states using ‘binary-gray’ code, this approach can
detect errors until the integer value of binary is not equal to integer value of gray for error state, which is a
sparse situation.

Organization of the Report:
This thesis is divided in to five chapters. The chapter wise out line is as follows
Chapter-1 deals with the motivation of error detection and correction and literature view of different
methods for error detection and correction.
Chapter-2 is concerned with challanges of memory cells and the existing codes.
Chapter-3 gives the Introduction of the software udes in the proposed code.
Chapter-4 Explains the way of Generating Decimal matrix code and the overall idea behind this project
with the aid of ERT for 32-bit word.
Chapter-5. Describes the Experimental Results of the Proposed 32-bit Decimal Matrix code.
Chapter-6 describes the future scope
Chapter-7 applications of the decimal matrix code
Chapter-8 gives the conclusion of the report
chapter-9 gives the references to the report

CHAPTER - 2
BACKGROUND OF REPORT
2.1 Error Detection and Existing Codes:
The aim of error detection and correction code is to provide against soft errors that manifest themselves as
bit-flips in memory. Several techniques are used present to midi gate upsets in memories. For example, the
Bose–Chaudhuri–Hocquenghem codes , Reed–Solomon codes , punctured difference set (PDS) codes , and
matrix codes has been used to contact with MCUs in memories. But the codes require more area, power, and
delay overheads since the encoding and decoding circuits are more complex in these complicated codes.
Reed-Muller code is another protection code that is able to detect and correct additional error than a
Hamming code. The main drawback of this protection code is its more area and power penalties.
Hamming Codes are more used to correct Single Error Upsets (SEU’s) in memory due to their ability to
correct single errors through reduced area and performance overhead. Though brilliant for correction of
single errors in a data word, they cannot correct double bit errors caused by single event upset. An extension
of the basic SEC-DED Hamming Code has been proposed to form a special class of codes known as Hsiao
Codes to increase the speed, cost and reliability of the decoding logic .
One more class of SEC-DED codes known as Single-error-correcting, Double-error-detecting Single-byte-
error-detecting SEC-DED-SBD codes be proposed to detect any number of errors disturbing a single byte.
These codes are additional suitable than the conventional SEC-DED codes for protecting the byte-organized
memories . Though they operate through lesser overhead and are good for multiple error detection, they
cannot correct multiple errors. There are additional codes such as the single-byte-error-correcting, double-
byte-error-detecting (SBC-DBD) codes, double-error-correcting, triple error-detecting (DEC-TED) codes
that can correct multiple errors as discussed.
The Single-error-correcting, Double-error-detecting and Double-adjacent-error-correcting (SEC-DED-
DAEC) code provides a low cost ECC methodology to correct adjacent errors as proposed . The only
drawback through this code is the possibility of miss-correction for a small subset of many errors.
2.2 Challenges Of Memory Cells:

AS CMOS technology scales down to nanoscale and memories are combined with an increasing
number of electronic systems, the soft error rate in memory cells is rapidly increasing, especially when
memories operate in space environments due to ionizing effects of atmospheric neutron, alpha-particle, and
cosmic rays.
Although single bit upset is a major concern about memory reliability, multiple cell upsets (MCUs)
have become a serious reliability concern in some memory applications. In order to make memory cells as
fault-tolerant as possible, some error correction codes (ECCs) have been widely used to protect memories
against soft errors for years. For example, the Bose–Chaudhuri–Hocquenghem codes, Reed–Solomon codes,
and punctured difference set (PDS) codes have been used to deal with MCUs in memories. But these codes
require more area, power, and delay overheads since the encoding and decoding circuits are more complex
in these complicated codes.
Interleaving technique has been used to restrain MCUs, which rearrange cells in the physical
arrangement to separate the bits in the same logical word into different physical words. However,
interleaving technique may not be practically used in content-addressable memory (CAM), because of the
tight coupling of hardware structures from both cells and comparison circuit structures.
Built-in current sensors (BICS) are proposed to assist with single-error correction and double-error
detection codes to provide protection against MCUs. However, this technique can only correct two errors in
a word.
More recently, in 2-D matrix codes (MCs) are proposed to efficiently correct MCUs per word with a
low decoding delay, in which one word is divided into multiple rows and multiple columns in logical. The
bits per row are protected by Hamming code, while parity code is added in each column. For the MC based
on Hamming, when two errors are detected by Hamming, the vertical syndrome bits are activated so that
these two errors can be corrected. As a result, MC is capable of correcting only two errors in all cases. In an
approach that combines decimal algorithm with Hamming code has been conceived to be applied at software
level. It uses addition of integer values to detect and correct soft errors. The results obtained have shown that
this approach have a lower delay overhead over other codes.
2.3 Proposed system Increment in Reliability Using DMC:
In this project, novel decimal matrix code (DMC) based on divide-symbol is proposed to provide
enhanced memory reliability. The proposed DMC utilizes decimal algorithm (decimal integer addition and
decimal integer subtraction) to detect errors. The advantage of using decimal algorithm is that the error

detection capability is maximized so that the reliability of memory is enhanced. Besides, the encoder-reuse
technique (ERT) is proposed to minimize the area overhead of extra circuits (encoder and decoder) without
disturbing the whole encoding and decoding processes, because ERT uses DMC encoder itself to be part of
the decoder.
Fig: 1.1 proposed schematic of fault-tolerant memory protected with DMC.
This Project is divided into the following sections. The proposed DMC is introduced and its encoder
and decoder circuits are present. This section also illustrates the limits of simple binary error detection and
the advantage of decimal error detection with some examples. The reliability and overheads analysis of the
proposed code are analyzed. In the implementation of decimal error detection together with BICS for error
correction in CAM is provided. Finally, some conclusions of this paper are discussed and shared.
Language and Tools Used:
Here the total project work is done by using ISE Simulator and XST Synthesis tool. The Xilinx
Software is a logic editor, synthesizer and simulator. Xilinx is used to validate the architecture of the logic
circuit before the microelectronics design is started. Xilinx provides a user friendly nature type environment
for hierarchical logic design, and simulation with delay analysis, which allows the design and validation of
complex logic structures. A key innovative feature is the possibility to estimate the power consumption of
the circuit. Some techniques for low power design are described in the manual.
The ISE Simulator tool allows the student to design and simulate an integrated circuit at physical description
level. The package contains a library of test bench requirements to view and simulate. You can gain access

to Circuit Simulation by pressing one single key. The electric extraction of your circuit is automatically
performed and the digital simulator produces logic level curves immediately.
ADVANTAGES:
• 1. More reliability
• 2 . More error correction rate
• 3. Less area
• 4.Hihg throughput
• 5.less delay

CHAPTER - 3
INTRODUCTION OF SOFTWARE USED
3.1 VHDL DESCRIPTION
In the search of a standard design and documentation for the Very High Speed Integrated Circuits
(VHSIC) program, the United States Department of Defense (DOD) in 1981sponsored a workshop on
Hardware Description Languages (HDL) at Woods Hole, Massachusetts. In 1983, the DOD established
requirements for a standard VHSIC Hardware Description Language VHDL, its environment and its
software was awarded to IBM, Texas Instruments and Intermetrics corporations.
VHDL 2.0 was released only after the project was begun. The language was significantly improved
correcting the shortcoming of the earlier versions; VHDL 6.0 was released in 1984. VHDL 1078/1164
formally became the IEEE standard Hardware Description Language in 1987.
VHDL design is defined as an ‘entity declaration’ and as an associated ‘architecture body’. The
declaration specifies its interface and is used by architecture bodies of design entities at upper levels of
hierarchy. The architecture body describes the operation of a design entity by specifying its interconnection
with other design entities –‘structural description,’ by its behavior –‘behavioral description’, or by a
mixture of both. The VHDL language groups, sub programs or design entities by use of packages.
For customizing generic descriptions of design entities, configurations are used. VHDL also
supports libraries and contains constructs for accessing packages, design entities or configurations from
various libraries.
3.1.2 Entities and Architectures
Entity Declaration:
The ENTITY declaration declares the name, direction and data type of each port of component.
Syntax: entity name is
Part ( );

End name:
Architecture Declaration:
The ARCHITECTURE portion of a VHDL description describes the behavior of the component.
Syntax: architecture [arch] <entity name > of <entity name> is
Begin
The ‘begin’ that follows the signal declaration marks the start of the architecture body. The follows a
process declaration, marked by the keyword PROCESS and an ensuring BEGIN.
The END statement ending the architecture must be accompanies by the name of the architecture
which must match the name shown in the first of the architecture.
3.1.3 SequentialProcessing
Sequential statements are statements that execute serially, one after other. In architecture for an
entity, all statement are concurrent, in VHDL, the process statements can exist in the architecture where all
statements are sequential.
Syntax:
[process-label:] process [(sensitivity list)]
Process-declarative-part;
Begin
Process-statement-part::=
Sequential statements};
End process [process-label];
A process statement has a declaration section and a statement part in declaration section types,
variables, constants, subprograms, etc., can be declared. Statements part contains only sequential statements
which consist of CASE statements, IF THEN ELSE statements, LOOP statements, etc.
Sensitivity list
This list defines the signals that will cause the statements inside the process statements to execute
whenever one or more elements of the list change value, i.e., list of signal that the process is sensitive to.
Changes in the values of these signals will cause to process to be invoked.
3.1.4 SequentialStatements

Sequential statements exist inside the boundaries of a process statement, as well as in sub programs. The
sequential statements that are generally used are:
IF,CASE,LOOP,ASSERT,WAIT
IF statement
Syntax: IF (condition) THEN
Sequence_of_statements;
[ELSE condition THEN
Sequence of_ statements ;}
[ELSE
Sequence_of_statements;]
END IF;
The IF statement start with the keyword IF and ends with the keywords END IF.
There are also two optional clauses: they are the ELSEIF clause and the ELSE clause. The conditional
construct in all cases is a Boolean expression. This is an expression that evaluates to either true or false.
Whenever the condition evaluates to a true value, the sequence of statements following are executed. IF
condition is true or false the sequence of statements for the ELSE clause is executed, if one exits. The IF
statement can have multiple ELSE IF statements parts, only one ELSE statement part, between each
statement part can exist more than one sequential statement.
CASE Statement
The CASE statement is used whenever a single expression value can be used to select between a numbers of
actions.
Syntax: CASE expression is
Case_statemant_alternative;
{Case_statemant_alternative ;}
END CASE;
Alternative:WHEN choice=>
Where choice::=
simple_expression
discrete_range
element_simple _name

OTHERS
A CASE statement consists of the keyboard CASE followed by an expression and the keyboard is. The
expression will either return a value that matches one of the choices in a WHEN statement part or a match an
others clause. After these statements are executed, control is transferred to the statements following the END
CASE clause
The CASE statement will execute the proper statement depending on the value of input instruction. If the
value of instruction is one of the choices listed in the WHEN clause is executed.
LOOP STATEMENT
The LOOP statement is used whenever an operation needs to be operated. LOOP statements are used when
powerful iteration capability is needed to implement a model.
Syntax: [Loop_label:][iteration_scheme]Loop
END LOOP [loop-label];
Where iteration_scheme:: =
WHILE condition
For loop_parametr_specification;
And Loop_parameter_specification::=
Identifier IN discrete_range
The loop statement has optional label, which can be used to identify the LOOP statement has an optional
iteration scheme that determines which kind of LOOP statement is being used. The iteration scheme
includes two types of LOOP statements, a ‘WHILE condition’ LOOP statement and a ‘FOR identifier IN
discrete range’ statement. The FOR loop will loop as many times as specified in the discrete range, unless
the loop is excited from the WHILE condition LOOP statement will loop as long as the condition expression
is TRUE.
In some languages, the loop index can be assigned value inside its loop to change its value. VHDL does not
allow any assignment to the index. This also precludes the loop index existing as the return value of a
function, or an out in out parameter of the procedure.
NEXT Statement

There are cases when it is necessary to stop executing the statements inside the loop for this iteration and go
to the next iteration. VHDL includes a construct that will accomplish this. The NEXT statement allows the
designer to stop processing this iteration and skip to the successor. When the NEXT statement is executed,
processing of the model stops at the current point and is transferred to the beginning of the loop statement.
Execution will begin with the first statement in the loop, but the loop variable will be incremented to the
next iteration value. If iteration limit has been reached, processing will stop else the execution will continue.
EXIT Statement
During the execution of the loop statement, it may be necessary to jump out of the loop. This can occur
because a significant error has occurred during the execution of the model or all if he processing has already
finished early. The VHDL EXIT statement allows the designer to exit or jump out of a LOOP statement
currently in execution. The EXIT statement causes execution of halt at the location of the EXIT statement.
Execution will continue at the following the LOOP statement.
The exit statement has three basic types of operations. The first involves an EXIT statement without a loop
label, or a WHEN condition. If these conditions are true, then the EXIT statement will behave as follows: the
EXIT statement will exit from the most current LOOP statement encounters. If an exit statement is inside
LOOP that is nested inside a LOOP statement, the EXIT statement will exit only the inner LOOP statement.
Execution will still remain in the outer LOOP statement.
ASSERT Statement
The ASSERT statement is a very useful statement for reporting textual strings to the designer. The ASSERT
statement checks the value of Boolean expression for true or false. If the value is true, the statement does
nothing. If the value is false, the ASSERT statement will output a user-defined string to the standard output
of the terminal.
The designer can also specify a severity level with which the text string. The four levels are, in increasing
level of severity: note, warning, error and failure. The severity level allows the designer the capability to
classify messages into proper categories.
The note category is full for relaying information to the user about what is currently happening in the
model. Assertions of category warning can be used to alert the designer of conditions that can cause
erroneous behavior. Assertions of severity level error are used to alert the designer of the conditions that will
cause the model to work incorrectly, or not work at all. Assertions of severity level failure are used to alert
the designer of the conditions within the model that have disastrous effects.
The ASSERT statement is currently ignored by synthesis tools. Since the ASSSERT statement is
mainly for exception handling while writing a model, no hardware is built.
Syntax: ASSERT condition

[REPORT expression]
[SEVERITY expression];
The keyword ‘ASSERT’ is followed by a Boolean-valued expression called a condition. The condition
determines whether the text expression specified by the REPORT clause is output or not. If false, the text
expression is output; the text expression is not output .
The REPORT and SEVERITY clauses are optional REPORT clause allows the designer the capability to
specify the value of a text expression to output. The SEVERITY clause allows the designer to specify the
severity level of the ASSERT statement. If the report clause is not specified, the default value for the
ASSERT statement is assertion violation. if the severity clause is not specified, the default value is error.
WAIT Statement
The WAIT statement allows the design the capability of suspending the execution of process of subprogram.
The conditions for resuming execution of the suspended process or subprogram can be specified by three
different means. These are:
WAIT on signal changes
WAIT UNTIL an expression is true
WAIT FOR a specific amount of time
WAIT statement can be used for number of different purposes. The most common use is for specifying clock
inputs to synthesize tools /the WAIT statement specifies the clock for a process statement that is read by
synthesis tool to create sequential logic such as register and flip-flops. Other uses of WAIT are to delay
process execution for an amount of tome or to modify the sensitivity list of the process dynamically.
WAIT ON signal
The WAIT ON signal clause specifies a list of one for more signals upon which the WAIT statement
will waits for events.
WAIT UNTIL expression
The WAIT UNTIL Boolean-expression clause will suspend execution of the process until the
expression returns a value of true.
WAIT FOR time-expression
The WAIT UNTIL time-expression clause will suspend execution of the process for the specified by
the time expression. After the time specified in the time expression has elapsed, execution will continue on
the statement following the WAIT statement.
Multiple WAIT statement
A single statement can include an ON signal, UNTIL expression and FOR time-expressions clauses.

3.1.5 Subprograms
In many programming languages, subprograms are used to simplify coding, modularity, and readability of
descriptions. VHDL uses subprograms for these applications for these applications as well as for those that
are more specific to hardware descriptions. Regardless of the application, behavior software–like constructs
are allowed in subprograms. VHDL allows two forms of subprograms, functions and procedures. Functions
return value cannot alter the values of the parameters. A procedure, on the other hand, is used as a statement,
and can after the values of the parameters.
Functions can be declared in VHDL by specifying:
1. The name of the function
2. The input parameters, if any
3. The type of returned value
4. Any declarations required by computation of the returned value.
Producers can also be written in VHDL. A procedure is declared by specifying:
1. The name of the procedure.
2. The input and output parameters, if any
3. Any declaration required by the procedure itself.
4. An algorithm
The main difference between a function and a procedure is that the procedure argument list will mostly
likely have a direction associated with each parameter, while the function argument list does not, in a
procedure, some of the arguments can be made IN, OUT or INOUT while in a function all arguments are of
mode IN by default can be default and can be of mode IN.
SIDE EFFECTS
Procedures have an interesting problem that is not shared by their functions counterparts. Procedures can
cause side effects to occur a side effect is the result of changing the value of an object inside a procedure
when that object was not an argument to the procedure.
3.1.6 Packages
The primary purpose of a package is to encapsulate elements that can be shared (globally) among
two or more decision units. A package is common storage area used to hold data to be shared among number

of entities. Declaring data inside of a package allows the data to be referenced by other entities; thus, the
data can be shared.
A package consists of two parts: a package declaration section and a package body. The package
declaration defines the interface for the package, much the way that the entity defines the interface for a
model. The body specifies the actual behavior of the package in the same method that the architecture
statement does for a mode.
The package declaration section can contain the following declarations:
#Subprogram declaration
#Type, subtype declaration
#Constant, deferred constant declaration
#Signal declaration, creates a global signal
#File declaration
#Alias declaration
#Component declaration
#Attribute declaration, a user-defined attribute
#Disconnection specification
#Use clause
All of the items declared in the package declaration section are visible to any design that uses the
package with a USE clause. The interface to a package consists of any subprograms or deferred constants
declared in the package declaration. The subprogram and deferred constant must have a corresponding
subprogram body and deferred constants value in the package body or an error will result.
3.2 XILINX
3.2.1 INTRODUCTION
Xilinx Tools is a suite of software tools used for the design of digital circuits implemented
using Xilinx Field Programmable Gate Array (FPGA) or Complex Programmable Logic
Device (CPLD). The design procedure consists of
(a) design entry
(b) synthesis and implementation of the design
(c) functional simulation and

(d) testing and verification
Digital designs can be entered in various ways using the above CAD tools: using a schematic
entry tool, using a hardware description language (HDL) – VHDL or VHDL or a combination
of both. In this lab we will only use the design flow that involves the use of VHDL HDL.
The CAD tools enable you to design combinational and sequential circuits starting with
VHDL HDL design specifications. The steps of this design procedure are listed below:
1. Create VHDL design input file(s) using template driven editor.
2. Compile and implement the VHDL design file(s).
3. Create the test-vectors and simulate the design (functional simulation) without using a PLD (FPGA or
CPLD).
4. Assign input/output pins to implement the design on a target device.
5. Download bitstream to an FPGA or CPLD device.
6. Test design on FPGA/CPLD device
A VHDL input file in the Xilinx software environment consists of the following segments:
Header: module name, list of input and output ports.
Declarations: input and output ports, registers and wires.
Logic Descriptions: equations, state machines and logic functions.
End: endmodule
All your designs for this lab must be specified in the above VHDL input format. Note that the state
diagram segment does not exist for combinational logic designs.
3.2.2 Programmable Logic Device:FPGA
In this lab digital designs will be implemented in the Basys2 board which has a Xilinx Spartan3E –
XC3S250E FPGA with CP132 package. This FPGA part belongs to the Spartan family of FPGAs. These
devices come in a variety of packages. We will be using devices that are packaged in 132 pin package with
the following part number: XC3S250E-CP132. This FPGA is a device with about 50K gates. Detailed
information on this device is available at the Xilinx website.
3.2.3 CREATING A NEW PROJECT:

Xilinx Tools can be started by clicking on the Project Navigator Icon on the Windows desktop. This
should open up the Project Navigator window on your screen. This window shows the last accessed project.
Xilinx Project Navigator window (snapshot from Xilinx ISE software)
3.2.4 OPENINGA PROJECT:
Select File->New Project to create a new project. This will bring up a new project window on the
desktop. Fill up the necessary entries as follows:

New Project Initiation window (snapshot from Xilinx ISE software)
Project Name: Write the name of your new project
Project Location: The directory where you want to store the new project (Note: DO NOT specify the project
location as a folder on Desktop or a folder in the Xilinxbin directory. Your H: drive is the best place to put
it. The project location path is NOT to have any spaces in it eg: C:NivashTAnew labsample
exerciseso_gate is NOT to be used)
Leave the top level module type as HDL.
Example: If the project name were “o_gate”, enter “o_gate” as the project name and then click “Next”.
Clicking on NEXT should bring up the following window:

Device and Design Flow of Project (snapshot from Xilinx ISE software)
For each of the properties given below, click on the ‘value’ area and select from the list of values that
appear.
1.Device Family: Family of the FPGA/CPLD used. In this laboratory we will be using the Spartan3E
FPGA’s.
2.Device: The number of the actual device. For this lab you may enter XC3S250E (this can be found on the
attached prototyping board)
3.Package: The type of package with the number of pins. The Spartan FPGA used in this lab is packaged in
CP132 package.
4.Speed Grade: The Speed grade is “-4”.
5.Synthesis Tool: XST [VHDL/VHDL]
6.Simulator: The tool used to simulate and verify the functionality of the design. Modelsim simulator is
integrated in the Xilinx ISE. Hence choose “Modelsim-XE VHDL” as the simulator or even Xilinx ISE
Simulator can be used.

7.Then click on NEXT to save the entries.
All project files such as schematics, netlists, VHDL files, VHDL files, etc., will be stored in a
subdirectory with the project name. A project can only have one top level HDL source file (or schematic).
Modules can be added to the project to create a modular, hierarchical design.
In order to open an existing project in Xilinx Tools, select File->Open Project to show the list of projects
on the machine. Choose the project you want and click OK.
Clicking on NEXT on the above window brings up the following window:
Create New source window (snapshot from Xilinx ISE software)
If creating a new source file, Click on the NEW SOURCE.In this lab we will enter a design using a
structural or RTL description using the VHDL HDL. You can create a VHDL HDL input file (.v file) using
the HDL Editor available in the Xilinx ISE Tools (or any text editor).
In the previous window, click on the NEW SOURCE
A window pops up as shown in Figure 4. (Note: “Add to project” option is selected by default. If you do
not select it then you will have to add the new source file to the project manually.)

Creating VHDL-HDL source file (snapshot from Xilinx ISE software)
Select VHDL Module and in the “File Name:” area, enter the name of the VHDL source file you are
going to create. Also make sure that the option Add to project is selected so that the source need not be
added to the project again. Then click on Next to accept the entries. This pops up the following window.

Define VHDL Source window (snapshot from Xilinx ISE software)
In the Port Name column, enter the names of all input and output pins and specify the Direction
accordingly. A Vector/Bus can be defined by entering appropriate bit numbers in the MSB/LSB columns.
Then click on Next> to get a window showing all the new source information. If any changes are to be
made, just click on <Back to go back and make changes. If everything is acceptable, click on Finish > Next
> Next > Finish to continue.

New Project Information window (snapshot from Xilinx ISE software)
Once you click on Finish, the source file will be displayed in the sources window in the Project
Navigator.
If a source has to be removed, just right click on the source file in the Sources in Project window in
the Project Navigator and select Remove in that. Then select Project -> Delete Implementation Data from the
Project Navigator menu bar to remove any related files.
3.2.5 EDITING THE VHDL SOURCE FILE:
The source file will now be displayed in the Project Navigator window. The source file window can be
used as a text editor to make any necessary changes to the source file. All the input/output pins will be
displayed. Save your VHDL program periodically by selecting the File->Save from the menu. You can also
edit VHDL programs in any text editor and add them to the project directory using “Add Copy Source

VHDL Source code editor window in the Project Navigator (from Xilinx ISE software)
Adding Logic in the generatedVHDL Source code template:
A brief VHDL Tutorial is available in Appendix-A. Hence, the language syntax and construction of
logic equations can be referred to Appendix-A.
The VHDL source code template generated shows the module name, the list of ports and also the
declarations (input/output) for each port. Combinational logic code can be added to the VHDL code after the
declarations and before the endmodule line.
For example, an output z in an OR gate with inputs a and b can be described as,
assign z = a | b;
Remember that the names are case sensitive.
Other constructs for modeling the logic function: A given logic function can be modeled in many
ways in VHDL. Here is another example in which the logic function, is implemented as a truth table using a
case statement:
module or_gate(a,b,z);
input a;
input b;

output z;
reg z;
always @(a or b)
begin
case ({a,b})
00: z = 1'b0;
01: z = 1'b1;
10: z = 1'b1;
11: z = 1'b1;
endcase
end
endmodule
Suppose we want to describe an OR gate. It can be done using the logic equation as shown in Figure 9a
or using the case statement as shown in Figure. These are just two example constructs to design a logic
function. VHDL offers numerous such constructs to efficiently model designs. A brief tutorial of VHDL is
available in Appendix-A.
OR gate description using assign statement (snapshot from Xilinx ISE software)

3.2.6Synthesisand Implementation of the Design
The design has to be synthesized and implemented before it can be checked for correctness, by running
functional simulation or downloaded onto the prototyping board. With the top-level VHDL file opened (can
be done by double-clicking that file) in the HDL editor window in the right half of the Project Navigator,
and the view of the project being in the Module view , the implement design option can be seen in the
process view. Design entry utilities and Generate Programming File options can also be seen in the process
view. The former can be used to include user constraints, if any and the latter will be discussed later.
To synthesize the design, double click on the Synthesize Design option in the Processes window.
To implement the design, double click the Implement design option in the Processes window. It will go
through steps like Translate, Map and Place & Route. If any of these steps could not be done or done with
errors, it will place a X mark in front of that, otherwise a tick mark will be placed after each of them to
indicate the successful completion. If everything is done successfully, a tick mark will be placed before the
Implement Design option. If there are warnings, one can see mark in front of the option indicating that
there are some warnings. One can look at the warnings or errors in the Console window present at the
bottom of the Navigator window. Every time the design file is saved; all these marks disappear asking for a
fresh compilation.

Implementing the Design (snapshot from Xilinx ISE software)
The schematic diagram of the synthesized VHDL code can be viewed by double clicking View RTL
Schematic under Synthesize-XST menu in the Process Window. This would be a handy way to debug the
code if the output is not meeting our specifications in the proto type board. By double clicking it opens the
top level module showing only input(s) and output(s)a
Realizedlogicbythe XilinxISEforthe VHDL code
Simulation of DMC is carried out successfully with model Xilinx simulator.
Simulation and synthesis has been carried out with XILINX ISE.
The design has to be synthesized and implemented before it can be checked for correctness,by running functional
simulation or downloaded onto the prototyping board. With the top-level Verilog file opened (can be done by double-
clicking that file) in the HDL editor window in the right half of the Project Navigator, and the view of the project
being in the Module view , the implement design option can be seen in the process view. Design entry utilities and
Generate Programming File options can also be seen in the process view.

To synthesize the design, double click on the Synthesize Design option in the Processes window.
To implement the design, double click the Implement design option in the Processes window. It will go
through steps like Translate, Map and Place & Route. If any of these steps could not be done or done with
errors, it will place a X mark in front of that, otherwise a tick mark will be placed after each of them to
indicate the successful completion. If everything is done successfully, a tick mark will be placed before the
Implement Design option.
If there are warnings, one can see ! mark in front of the option indicating that there are some warnings.
One can look at the warnings or errors in the Console window present at the bottom of the Navigator
window. Every time the design file is saved; all these marks disappear asking for a fresh compilation.
The schematic diagram of the synthesized Verilog code can be viewed by double clicking View RTL
Schematic under Synthesize-XST menu in the Process Window. This would be a handy way to debug the
code if the output is not meeting our specifications in the proto type board.
The Processes window (making sure that the test bench file in the Sources window is selected) expand
the Modelsim simulator Tab by clicking on the add sign next to it.
Double Click on Simulate Behavioral Model. You will probably receive a complier error. This is nothing
to worry about – answer “No” when asked if you wish to abort simulation. This should cause ModelSim to
open. Wait for it to complete execution. If you wish to not receive the compiler error, right click on Simulate
Behavioral Model and select process properties. Mark the checkbox next to “Ignore Pre-Complied Library

Warning Check”. To save the simulation results, go to the waveform window of the Modelsim simulator,
Click on File -> Print to Postscript -> give desired filename and location.
Note that by default, the waveform is “zoomed in” to the nanosecond level. Use the zoom controls to display
the entire waveform. Else a normal print screen option can be used on the waveform window and
subsequently stored in Paint.
3.2.7 RTL Schematic diagram
Fig: 5.1 RTL Schematic diagram of 32 bit DMC

3.2.8 Technology schematic
Fig: 5.3 Technology schematic of 32 bit DMC

CHAPTER - 4
IMPLEMENTATION OF WORK
This chapter explains the way of Generating Decimal matrix code and the overall idea behind this project
with the ERT for 32-bit word. ERT uses DMC encoder itself to be part of the decoder which reduces the
area of the circuit.
4.1 INTRODUCTION:
Transient multiple cell upsets (MCUs) are becoming major issues in the reliability of memories exposed to
radiation environment. To prevent MCUs from causing data corruption, more complex error correction
codes (ECCs) are widely used to protect memory, but the main problem is that they would require higher
delay overhead. Recently, matrix codes (MCs) based on Hamming codes have been proposed for memory
protection. The main issue is that they are double error correction codes and the error correction capabilities
are not improved in all cases. In this project, novel decimal matrix code (DMC) based on divide-symbol is
proposed to enhance memory reliability with lower delay overhead. The proposed DMC utilizes decimal
algorithm to obtain the maximum error detection capability. Moreover, the encoder-reuse technique (ERT)
is proposed to minimize the area overhead of extra circuits without disturbing the whole encoding and
decoding processes. ERT uses DMC encoder itself to be part of the decoder.
4.2 Schematic of Fault-Tolerant Memory:
The proposed schematic of fault-tolerant memory is depicted in Fig. First, during the encoding
(write) process, information bits D are fed to the DMC encoder, and then the horizontal redundant bits H and
vertical redundant bits V are obtained from the DMC encoder. When the encoding process is completed, the
obtained DMC codeword is stored in the memory. If MCUs occur in the memory, these errors can be
corrected in the decoding (read) process. Due to the advantage of decimal algorithm, the proposed DMC has
higher fault-tolerant capability with lower performance overheads. In the fault-tolerant memory, the ERT

technique is proposed to reduce the area overhead of extra circuits and will be introduced in the following
sections.
Fig: 3.1 schematic of 32 bit with DMC.
4.3 32- Bit DMC Encoder:
In the proposed DMC, first, the divide-symbol and arrange-matrix ideas are performed, i.e., the N-bit
word is divided into k symbols of m bits (N = k × m), and these symbols are arranged in a k1 × k2 2-D matrix
(k = k1 × k2, where the values of k1 and k2 represent the numbers of rows and columns in the logical matrix
respectively). Second, the horizontal redundant bits H are produced by performing decimal integer addition
of selected symbols per row. Here, each symbol is regarded as a decimal integer. Third, the vertical
redundant bits V are obtained by binary operation among the bits per column. It should be noted that both
divide-symbol and arrange-matrix are implemented in logical instead of in physical. Therefore, the proposed
DMC does not require changing the physical structure of the memory.
To explain the proposed DMC scheme, we take a 32-bit word as an example, as shown in Fig.4.2. The
cells from D0 to D31 are information bits. This 32-bit word has been divided into eight symbols of 4-bit. k1 =
2 and k2 = 4 have been chosen simultaneously. H0–H19 are horizontal check bits; V0 through V15 are vertical
check bits. However, it should be mentioned that the maximum correction capability (i.e., the maximum size
of MCUs can be corrected) and the number of redundant bits are different when the different values for k
and m are chosen. Therefore, k and m should be carefully adjusted to maximize the correction capability and
minimize the number of redundant bits.
For example, in this case, when k = 2×2 and m = 8, only 1-bit error can be corrected and the number of
redundant bits is 80. When k = 4 × 4 and m = 2, 3-bit errors can be corrected and the number of redundant
bits is reduced to 32. However, when k = 2 × 4 and m = 4, the maximum correction capability is up to 5 bits

and the number of redundant bits is 72. In this paper, in order to enhance the reliability of memory, the error
correction capability is first considered, so k = 2 × 8 and m = 4 are utilized to construct DMC.
Fig: 3.2 32 bit word can be divided as 8 symbols with k=2x4 and m=4.
Horizontal redundant bits are calculated as follows
H9 H8 H7 H6 H5 = D7 D6 D5 D4 + D15 D14 D13 D12 (1)
H4H3H2H1 H0 = D3 D2 D1 D0 +D11 D10 D9 D8
(2)
Similarly for the horizontal redundant bits H14 H13H12 H11 H10 and H19 H18H17H16 H15, where "+"
represents decimal integer addition.
Vertical redundant bits are calculated as follows
V0 = D0⊕ D16 (3)
V1 = D1⊕ D17 (4)
And similarly for the rest vertical redundant bits. The encoding can be performed by decimal and
binary addition operations from (1) to (4). The encoder that computes the redundant bits using multi bit
adders and XOR gates is shown in Fig. In this figure, H19 − H0 are horizontal redundant bits, V15 − V0 are
vertical redundant bits, and the remaining bits U31 − U0 are the information bits which are directly copied
from D31 to D0. The enable signal En will be explained in the next section.
The following fig shows the 32 Bit DMC Encoder which consists of adder circuits and EX-OR gates
to calculate horizontal and vertical redundant bits.

Fig: 3.3 32 -bit DMC encoder structure using multi bit adders and XOR gates
4.4 32 Bit DMC decoder:
To obtain a word being corrected, the decoding process is required. For example, first, the received
redundant bits H4H3H2H1H0’ and V0’-V3’ are generated by the received information bits D’. Second, the
horizontal syndrome bits ∆H4H3H2H1H0 and the vertical syndrome bits S3 − S0 can be calculated as follows:
∆H4H3H2H1H0 = H4H3H2H1H0’ − H4H3H2H1H0 (5)
S0 = V0’ ^ V0 (6)
and similarly for the rest vertical syndrome bits, where “−” represents decimal integer subtraction. When
∆H4H3H2H1H0 and S3 − S0 are equal to zero, the stored codeword has original information bits in symbol 0
where no errors occur. When ∆H4H3H2H1H0 and S3 − S0 are nonzero, the induced errors (the number of
errors is 4 in this case) are detected and located in symbol 0, and then these errors can be corrected by
D0correct = D0 ^ S0 (7)
The following figure shows the 32-bit DMC decoder. The DMC decoder is depicted in Fig,4.4 which is
made up of the following sub modules, and each executes a specific task in the decoding process: syndrome
calculator, error locator, and error corrector. It can be observed from this figure that the redundant bits must
be recomputed from the received information bits D’ and compared to the original set of redundant bits in
order to obtain the syndrome bits ∆H and S. Then error locator uses ∆H and S to detect and locate which bits
some errors occur in. Finally, in the error corrector, these errors can be corrected by inverting the values of
error bits.

Fig: 3.4 32 Bit DMC decoder
Fig: 3.5 Encoder Reuse Technique
In this scheme, the circuit area of DMC is minimized by reusing its encoder. This is called the ERT.
The ERT can reduce the area overhead of DMC without disturbing the whole encoding and decoding
processes.
From Fig, 4.5 it can be observed that the DMC encoder is also reused for obtaining the syndrome bits
in DMC decoder. Therefore, the whole circuit area of DMC can be minimized as a result of using the
existent circuits of encoder. Besides, figure5.3.2 also shows the proposed decoder with an enable signal En
for deciding whether the encoder needs to be a part of the decoder. In other words, the En signal is used for
distinguishing the encoder from the decoder, and it is under the control of the write and read signals in
memory. Therefore, in the encoding (write) process, the DMC encoder is only an encoder to execute
the encoding operations. However, in the decoding (read) process, this encoder is employed for
computing the syndrome bits in the decoder. These clearly show how the area overhead of extra circuits can
be substantially reduced.

4.5 Area, Delay, Power analysis of DMC:
The following figure represents area, delay, power analysis of DMC compared to other codes
Table: 1 Area, delay and power analysis of DMC
Table: 2 In 32-bit DMC 16 errors can be corrected
For 32-bit DMC 16 errors can be corrected as shown in below tabular form compared to remaining codes
ECC
CODES
1 2 3 4 5 6 7 8 9 10 1 1 1 1 1 1
1 2 3 4 5 6
5
DMC
100 100 10 10 10 92 84 76 66 60 4 4 4 3 2 1
0 0 0 7 0 1 2 1
PDS
100 100 10 8 0 0 0 0 0 0 0 0 0 0 0 0
0
MC
100 100 76 54 35 14 67 0 0 0 0 0 0 0 0 0
2 6
HAMMING
100 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
ECC
CODES
µm2
% mw % Ns %
DMC 41572.6 100 10.8 100 4.9 100
PDS 486778 1170.9 2211.1 2047.2 18.7 381.6
MC 77934 187.5 24.7 228.7 7.1 144.9
HAMMING 58409 140.5 20.5 189.8 6.7 136.7

4.6 Limits of Simple Binary Error Detection
For the proposed binary error detection technique, although it requires low redundant bits, its error
detection capability is limited. The main reason for this is that its error detection mechanism is based on
binary.
Fig: 4.4 Limits of binary error detection in simple binary operations
We illustrate the limits of this simple binary error detection using a simple example. Let us suppose that
the bits B3, B2, B1, and B0 are original information bits and the bits C0 and C1 are redundant bits shown in
Fig. The bits C0 and C1 are obtained using the binary algorithm.
C0 = B0 ^ B2 = 1 ^ 0 = 1 (8)
C1= B1 ^ B3 = 0 ^ 1 = 1 (9)
Then assume now that MCUs occur in bits B3, B2, and B0 (i.e., B3’= 0, B2’= 1, and B’0= 0). The
received redundant bits C0’ and C1’ are computed
C0’= B0’^ B2’= 0 ^ 1 = 1 (10)

C1’= B1’^ B3’= 0 ^ 0 = 0. (11)
In order to detect these errors, the syndrome bits S0 and S1 are obtained
S0 = C0’^ C0 = 1 ^ 1 = 0 (12)
S1 = C1’^ C1 = 0 ^ 1 = 1. (13)
These results mean that error bits B2 and B0 are wrongly regarded as the original bits so that these
two error bits are not corrected. This example illustrates that for this simple binary operation, the number of
even bit errors cannot be detected.
4.7 Advantage of Decimal Error Detection
In the previous discussion, it has been shown that error detection based on binary algorithm can only
detect a finite number of errors. However, when the decimal algorithm is used to detect errors, these errors
can be detected so that the decoding error can be avoided. The reason is that the operation mechanism of
decimal algorithm is different from that of binary. The detection procedure of decimal error detection using
the proposed structure shown in Fig below.
Fig. 3.5 Advantage of decimal error detection using decimal algorithm
. First of all, the horizontal redundant bits H4H3H2H1H0 are obtained from the original information bits in
symbols 0 and 2 according to (1)
H4H3H2H1H0 = D3D2D1D0 + D11D10D9D8
= 1100 + 0110

= 10010. (14)
When MCUs occur in symbol 0 and symbol 2, i.e., the bits in symbol 0 are upset to “1111” from “1100”
(D3D2D1D0’ = 1111) and the bits in symbol 2 are upset to “0111” from “0110” (D11D10D9D8’ = 0111).
During the decoding process, the received horizontal redundant bits H4H3H2H1H0’ are first computed, as
follows:
H4H3H2H1H0’ = D11D10D9D8’ + D3D2D1D0’
= 0111 + 1111
= 10110. (15)
Then, the horizontal syndrome bits _H4H3H2H1H0 can be obtained using decimal integer subtraction
∆H4H3H2H1H0 = H4H3H2H1H0’ − H4H3H2H1H0
= 10110 − 10010
= 00100. (16)
The decimal value of ∆H4H3H2H1H0 is not “0,” which represents that errors are detected and located
in symbol 0 or symbol 2. Subsequently, the precise location of the bits that were flipped can be located by
using the vertical syndrome bits S3 − S0 and S11 − S8. Finally, all these errors can be corrected by (7).
Therefore, based on decimal algorithm, the proposed technique has higher tolerance capability for protecting
memory against MCUs.
As a result, it is possible that all single and double errors and any types of multiple errors per row can
be corrected by the proposed technique no matter whether these errors are consecutive or inconsecutive in
Fig.6.5.2

Fig: 4.6 Types of MCUs can be corrected by our proposed DMC.
The proposed DMC can easily correct upsets of type 1, 2, and 3, because these are the essential property of
DMC: any types of single-error and multiple-error corrections in two consecutive symbols. Upsets of types 4
and 5 introduced in Figure3.6. Also corrected because the multiple errors per row can be detected by the
horizontal syndrome bits. These show that the proposed technique is an attractive option to protect memories
from large MCUs. However, for the upsets of type 4 and 5, it is important to recognize that it can result in
decoding error when the following prerequisite factors are achieved simultaneously (this error is typical of
its kind).
Fig: 4.7 Decoding error avoided using DMC
1) The decimal integer sum of information bits in symbols 0 and 2 is equal to 2m − 1.

2) All the bits in symbols 0 and 2 are upset.
The more detailed explanation is shown in Fig. Assuming that these two factors have been achieved,
according to the encoding and decoding processes of DMC, H4H3H2H1H0, and H4H3H2H1H0’ are computed,
as follows:
H4H3H2H1H0 = D3D2D1D0 + D11D10D9D8
= 0110 + 1001
= 01111 (17)
H4H3H2H1H0’ = D3D2D1D0’ + D11D10D9D8’
= 1001 + 0110
= 01111. (18)
Then the horizontal syndrome bits _H4H3H2H1H0 can be obtained
∆H4H3H2H1H0 = H4H3H2H1H0’ − H4H3H2H1H0
= 01111 − 01111
= 00000. (19)
This result means that no errors occur in symbols 0 and 2 and memory will suffer a failure. However,
this case is rare. For example, when m = 4, the probability of decoding errors is
PMCU8 represents the probability of eight upsets in a given word, and similarly for PMCU16.

Fig: 4.8 improved performance of DMC
4.8 ALGORITHM:
In programming algorithm are the set of well defined instructions in sequence to solve a problem. The
algorithm for 32 bit DMC will be as follows.
1. First the clock is given which is used for transmitting and receiving the data within a single clock of
positive edge.
2. Then the reset condition is defined for on/off conditions.
3. This approach mainly consist of 2 main blocks
i) Encoder
ii) Decoder
4. Give the 32 bit data to the DMC Encoder.

5. Encoder computes horizontal and vertical redundant bits.
6. Encoder adds the horizontal and vertical redundant bits to the actual data thus encoding of data can be
performed.
7. Decoder checks whether the error induced in the received information by calculating redundant bits for
the received information.
8. Decoder having three main blocks
i) Syndrome calculator
ii) Error locator
iii) Error corrector
8. Syndrome calculator computes the syndrome bits and checks these syndrome bits are zero or not. Non
zero syndrome bits represents errors in the received information.
9. Errors detected by Error locator and corrected by Error corrector using modulo-2 arithmetic operations
between syndrome bits and actual data.
11. Decoded data given as output by the decoder.
4.9 FLOW CHARTS:
A flowchart is a type of diagram that represents an algorithm workflow or process, showing the steps as
boxes of various kinds, and their order by connecting them with arrows. This diagrammatic representation
illustrates a solution model to a given problem. Flowcharts are used in analyzing, designing, documenting or
managing a process or program in Digital Design.
The Flow Chart diagrams for the 32 bit DMC are

Reset clock
32 bit data
1
0
Fig: 4.9 flowchart for 32 bit DMC
start
DMC Encoder
Memory
DMC Decoder
Syndrome calculator
syndrome bits
zero or
nonzero
stop
Error locator and
error corrector

Fig:4.11 flow chart for syndrome calculation
start
input [31:0 ]v,vd;
output [31:0]s;
assigns[0] = v[0] ^ vd[0];
assigns[1] = v[1] ^ vd[1];
assigns[2] = v[2] ^ vd[2];
assigns[30] = v[30] ^ vd[30];
assigns[31] = v[31] ^ vd[31];
stop

CHAPTER - 5
OUTPUT SCREENS
5.1 ENCODER:

5.2 MEMORY:

5.3 ERROR DETECTION:

5.4 ERROR CORRECTION:

CHAPTER - 6
FUTURE SCOPE
The future work will be conducted for the reduction of the redundant bits and the
maintenance of the reliability of the proposed technique.
In this design, the adder block is replaced with Hamming codeblock in the encoder structure
which in turn reduced the number of horizontal redundant bits. Even though it enhanced the
correction capability, it still uses a large amount of redundant bits. This thesis can further be
researched in the decoderstructure to reduce the vertical redundant bits keeping a higher
correction capability.

CHAPTER - 7
APPLICATIONS
Computer memories: the codes used are extended decimal matrix code the latter being perfect single-error-
correcting.
Photographs from spacecraft: the codes initially used were decimal matrix code, which can be constructed
as the orthogonal extended Hamming codes.
Compact discs: the codes used are decimal code, constructed using certain finite fields of large prime-power
order.

CHAPTER - 8
CONCLUSION
To prevent MCUs from causing data corruption, more complex error correction codes (ECCs) are widely
used to protect memory, but the main problem is that they would require higher delay overhead. Recently,
matrix codes (MCs) based on Hamming codes have been proposed for memory protection.
In this implemented project, novel per-word DMC was proposed to assure the reliability of memory.
The protection code utilized decimal algorithm to detect errors, so that more errors were detected and
corrected. The obtained results showed that the implemented scheme has a superior protection level against
large MCUs in memory.
In this thesis, modified-DMC was proposed to protect memories from radiation induced errors. The
proposed method uses a combination of Hamming encoder and decimal algorithm which allows detection
and correction of large MCUs. Also, the use of Encoder re-use technique reduced the area overhead of extra
circuits. The obtained results has reduced the number of redundant bits by 22.22%, reduced the area of the
design by 11.87 %, reduced power consumption by 18.44% and reduced the delay by 21.38%. These results
show that the proposed method has a superior protection level against multiple cell upsets in memory and
provides more reliable data than the existing method.

CHAPTER - 9
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