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Stick Diagram

The document discusses design rules and stick diagrams used in integrated circuit layout and design. Design rules define guidelines for constructing process masks and minimum feature sizes. Stick diagrams graphically represent the relative placement of transistors and components without exact dimensions, sizes, or compliance with design rules. They help visualize interconnects and plan preliminary layouts. Examples of stick diagrams are provided for basic gates and a 4-input NOR gate.

Engineering◦
Related topics:
VLSI Design Insights•
Design Rules • Interface between designer and process engineer • Guidelines for constructing process masks • Unit dimension: Minimum line width – scalable design rules: lambda parameter – absolute dimensions (micron rules)
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Stick Diagram • A stick diagram is a graphical view of a layout. • Does show all components/vias (except possibly tub ties), relative placement. • Does not show exact placement, transistor sizes, wire lengths, wire widths, tub boundaries.
Stick Diagram • Represents relative positions of transistors • Stick diagrams help plan layout quickly – Need not be to scale – Draw with color pencils or dry-erase markers In Out VDD GND Inverter A Out VDD GND B NAND2
Stick Diagram Metal (BLUE) Polysilicion (RED ) N-Diffusion (Green) P-Diffusion (Brown) Contact / Via Layers
Jhon P. U Stick Diagrams • Cartoon of a layout. • Shows all components. • Does not show exact placement, transistor sizes, wire lengths, wire widths, boundaries, or any other form of compliance with layout or design rules. • Useful for interconnect visualization, preliminary layout layout compaction, power/ground routing, etc.
Jhon P. U 5 V Dep Vout Enh 0V 5 v 0 V Vin 5 v
Parallel Connected MOS Patterning Jhon P. U x y A B x A B X X X y
Alternate Layout Strategy A B Jhon P. U x y x X X A B X X y
Designing MOS Arrays A B C x y Jhon P. U y x A B C
The CMOS NOT Gate Jhon P. U X X X X Vp Gnd x Gnd n-well Vp x x x Contact Cut
Alternate Layout of NOT Gate Jhon P. U Vp Gnd x x X x Vp Gnd X x X X
NAND2 Layout Jhon P. U Vp Gnd b a. a b X Vp Gnd X X X X a b b a.
NOR2 Layout Jhon P. U Vp Gnd b a  a b X X X Vp Gnd X X a b b a 
NAND2-NOR2 Comparison Jhon P. U X Vp Gnd X X X X X X X X X Vp Gnd MOS Layout Wiring
Activity 2 • Sketch a stick diagram for a 4-input NOR gate A VDD GND B C 2: MIPS Processor Example Slide 20 Y D
A Out C Jhon P. U Stick Diagram - Example II Power Ground B
Stick Diagram