This document discusses different types of flip-flops including SR, JK, D, and T flip-flops. It explains that flip-flops have two stable states (high and low) and can switch between these states under a control signal like a clock. The document provides truth tables and diagrams to illustrate the working of each flip-flop type and their applications in storing data and transferring data between registers.

1. FLIP FLOPS
ByUnsaShakir

2. INTRODUCTION:
• Flip – flops have two stable states and hence they are
bistable multivibrators. The two stable states are High
(logic 1) and Low (logic 0).
• They can switch between the states under the influence of
a control signal (clock or enable) i.e. they can ‘flip’ to one
state and ‘flop’ back to other state.
• They are binary storage devices because they can store
binary data (0 or 1).

3. INTRODUCTION:
• They are also known as signal change sensitive
devices which mean that the change in the level of
clock signal will bring change in output of the flip
flop.
• A Flip – flop works depending on clock pulses.
• Flip flops are also used to control the digital
circuit’s functionality. They can change the
operation of a digital circuit depending on the state

4. CONVENTIONS
• The two outputs are complementary to each
other.
• If Q is 1 that is set Q’ to 0.
• If Q is 0, reset Q’ to 1. (Q and Q’ can’t be at the
same state simultaneously. If it happens, it will
violate the definition of the flip-flop and hence is
called undefined condition).

5. • Q is called the state of the flip-flop whereas Q’
is called complementary state of the flip-flop.
• When the output Q is either 0 or 1, it remains
in that state unless one or more inputs are
excited to effect the change on the output.

6. FLIP-FLOPS
3 classes of flip-flops
• latches: outputs respond immediately while
enabled (no timing control)
• pulse-triggered flip-flops: outputs response to
the triggering pulse
• edge-triggered flip-flops: outputs responses to
the control input edge

7. TYPESOF FLIPFLOPS
• S-RFlip-flop
• J-KFlip-flop
• D Flip-flop
• TFlip-flop

8. S-R FLIP FLOP
• The S-R flip-flop is basic flip-flop among all the flip-
flops. All the other flip flops are developed after SR-flip-
flop.
• SR flip flop is represented as shown below

9. S-R FLIP FLOP
• Any flip flop can be build using logic gates. NAND and NOR
gates were used as they are universal gates.

10. The Basic SR Flip-flop
The Basic SR Flip-flop with clock

11. Working
From the diagram it is evident that the flip flop has
mainly four states. They are
S=1, R=0 — Q=1, Q’=0
This state is also called the SET state.
S=0, R=1— Q=0, Q’=1
This state is k nown as the RESET state.
In both the states ,the outputs are just compliments
of each other and that the value of Q follows the
value of S.

12. S=0, R=0 — Q & Q’= Remember
If both the values of S and R are switched to 0,
then the circuit remembers the value of S and R in
their previous state.
S=1, R=1—Q=0, Q’=0 [Invalid]
• This is an invalid state because the values of
both Q and Q’are 0.
• They are supposed to be compliments of each
other. Normally, this state must be avoided.

13. JK-FLIP FLOP
• The J-K flip-flop is operationally similar to the S-
R flip-flop.
• The J-K flip-flop is clock driven like the clocked
S-R flip-flop.
• The difference is that the J-K flip-flop will retain
its output status when two lows are present at
its inputs. Also, when both inputs are high, the
outputs will toggle on and off

14. WORKING
• Q and Q' are feedback to the pulse-steering
NAND gates.
• No invalid state.
• Include a toggle (switch) state.
• J=HIGH (and K=LOW) - a SET state
• K=HIGH (and J=LOW) - a RESET state
• both inputs LOW - a no change
• both inputs HIGH - a toggle

15. • Toggling means ‘Changing the next state output to
complement of the present state output’
• Toggling will cause the output to complement
again and again.
• This complement operation continues until the
Clock pulse goes back to 0. Since this condition is
undesirable, we have to find a way to eliminate this
condition.
• This undesirable behavior can be eliminated by
Edge triggering of JK flip-flop or by using master
slave JK Flip-flops.

16. JK-FLIP FLOP

17. J-K FLIP FLOP TRUTH TABLE
previous values present values
clk J K Q Q’ S R Q Q’
1 0 1 1 0 0 1 0 1
0 1 0 0 0 1
1 1 0 1 0 0 0 1 0
0 1 1 0 1 0
1 0 0 1 0 0 0 1 0 previous
values
0 1 0 0 0 1
1 1 1 1 0 0 1 0 1 compliment
of previous
values
0 1 1 0 1 0
S=J.Q’
R=K.Q

18. J-K FLIP FLOP TRUTH TABLE
summary

19. D-FLIP FLOP
• single input D (data)
• D=HIGH - a SET state
• D=LOW - a RESET state
By comparing R-S, J-K, and D flip-flops one can
see that the D flip-flop never has an unknown
state, unlike the R-S and J-K.
The D flip-flop is widely used. It is also known as a
"data" or "delay" flip-flop and negative edge
triggered flip flop.

20. D-FLIP FLOP

21. CLK D J K Q Q’
1 1 0 1 0 1
1 1 1 0 1 0
J=Q
D-FLIP FLOP TRUTH TABLE

22. T-FLIP FLOP
• A T flip flop is like JK flip-flop.
• These are basically a single input version of JK
flip flop.
• This modified form of JK flip-flop is obtained by
connecting both inputs J and K together.
•
• This flip-flop has only one input along with the
clock input.

23. clk T J K Q Q’ S R Q Q’
1 0 0 0 1 0 0 0 1 0 previous
values
0 1 0 0 0 1
1 1 1 1 1 0 0 1 0 1 compliment
of previous
values
0 1 1 0 1 0

24. THE USE OF FLIP FLOP
• For Register Devices:
Flip flops can store a single bit of data i.e. 1 or 0.
Registers are used to store multiple bits of data. So
flip flops are used to design Registers. According to
digital electronics, a Register is a device which is
used to store the information.
• Data Transfer
The process of transferring the data from one
register to another register