Manufacturing of Electronics

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Manufacturing of electronics
MIT 2.008 – Prof. John Hart
November 29, 2017

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LCD Touch
Screen
Front Case
Battery
Circuit board
Back Case

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Speaker
Back Camera
WiFi
Antenna
Headset Connector
Processor etc
(shielded)

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Flash memory
(8 GB)
CPU (Quad-core
ARM 1.3 GHz)

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11 W power, 815 lumens
25,000 hours
$5.99
2,000 hours
~$0.60
Light bulbs: old and new

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Key manufacturing technologies for electronic
products
§ Integrated circuit (IC) processing (i.e., ‘semiconductor
manufacturing) à often done on silicon wafers to achieve
high density circuits. This includes (with ~nm precision):
§ Thin film deposition
§ Photolithography (patterning, like each layer of SLA)
§ Etching
§ Planarization (polishing)
§ Circuit board manufacturing and soldering à to hold
the ICs and create custom electronic systems
§ Pick-and-place assembly à packaging ICs and other
components; placing components on circuit boards
§ Connectors (rigid and flexible) à connect rigid boards to
buttons, batteries, antennas, etc.
§ Emerging technologies including fully printed devices.

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Inside the integrated circuit (IC)
http://electronics.stackexchange.com/questions/56649/what-is-a-die-package
Gold wire connections to
the chip circuitry

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Inside the integrated circuit (IC)
Slide adapted from E. Pop

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Building block: MOSFET transistor
Image: E. Pop
Textbook: Prof. Chenming Hu, http://www.eecs.berkeley.edu/~hu/
Video on how transistors work: http://www.youtube.com/watch?v=IcrBqCFLHIY

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Approaching atomic resolution

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John Bardeen, William Shockley
and Walter Brattain at Bell Labs,
1948.
The first transistor
Gate
Book: “The Idea Factory: Bell Labs and the Great
Age of American Innovation”

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Platform: silicon wafers

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Moore’s law: number of transistors on a chip
~doubles every two years
http://en.wikipedia.org/wiki/Moore's_law; https://en.wikipedia.org/wiki/Transistor_count
2016: Apple A10
(iPhone 7) has 3.3
billion transistors over
an area of 125 mm2
.
à Effective cost of
one transistor is less
than one letter printed
in the newspaper!
($ ~0.1x10-6)

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A semiconductor manufacturing plant
http://www.samsung.com/global/business/semiconductor/foundry
/manufacturing/overview

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The semiconductor plant (‘fab’)
§ Worldwide, >170 major semiconductor manufacturing plants.
§ Cost per plant >$1 BILLION.…can easily reach $3-4 billion.
Samsung spent $14.7 billion USD on their new memory chip
plant (2014).
§ The central part of a semiconductor plant is the clean room
§ Eliminate ~all dust, temperature and humidity control to minimize static
electricity, dampened against vibration.
§ Machines to be found in the clean room are steppers for photolithography,
etching, cleaning, doping and dicing machines. The typical price range for
new machines is $700,000 to $4,000,000 ..and up to $50,000,000 for each
wafer stepper. Hundreds of machines are needed in one plant.
§ The capital depreciation can account for 50-80% of
manufacturing cost! Thus semiconductor manufacturing
equipment has a large secondary market.
http://www.ft.com/cms/s/0/b478b190-4d03-11e4-a0d7-00144feab7de.html#axzz3KbtVQwYG
http://en.wikipedia.org/wiki/Semiconductor_fabrication_plant
http://www.forbes.com/sites/jimhandy/2011/12/19/whats-it-like-in-a-semiconductor-fab/

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Layout of a semiconductor fab
‘Front-end’
‘Back-end’
Image from FormFactor:
http://www.sec.gov/Archives/edgar/data/1039399/000089161803002980/f80848b1f80848f2.gif

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MIT.nano (2018)
mitnano.mit.edu

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Generic device fabrication
Blank Si wafer
Material addition or
removal
(Characterization)
Complete device
Final
test
Material addition
• Chemical or physical
vapor deposition
(PVD or CVD)
• Oxidation
• Doping
• Ion implantation
• Electroplating
Next step?
Material removal
• Wet etching
• Dry (gas/plasma)
etching
• Chemical/mechanical
polishing (CMP)
Pattern transfer
(lithography)

2.008-F17 | 22S. Bathhurst / S.G. Kim, MIT
Silicon wafer production
Si ingot (single
crystal)
Wafers (up to 300
mm diameter)
Slicing: rotating saw or
abrasive-coated wire.
Then: etching/polishing surface.
Key specs: thickness,
roughness, flatness (“wafer
bow”)

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Example: building an array of interconnects (wires)
à W ~20 nm; t ~5 nm
Si wafer
SiO2
Metal

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Si wafer
Si wafer
SiO2
Deposit or ‘grow’ SiO2 layer
Begin with bare Si wafer (polished surface)
Deposit metal layer
Metal
Coat photoresist (PR)
Photoresist
Pattern photoresist (this is photolithography)
Etch metal (using patterned PR as the mask)
Remove photoresist
Si wafer
SiO2
Metal

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Thin film deposition methods
§ Surface reaction: the surface of the wafer
reacts to form a thin film; for example,
oxidation. The substrate surface is
consumed.
§ Physical vapor deposition (PVD): a film
is created by exposing the substrate
(lower temp) to a vapor of the desired
material.
§ Chemical vapor deposition (CVD): a film
is created by a chemical reaction of
gaseous precursors at the substrate
surface (but not consuming the substrate).
PVD by
evaporation

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Chemical vapor deposition (CVD)

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Chemical vapor deposition (CVD)
§ CVD: deposits a thin film from gaseous precursors via a
chemical reaction at the surface of a substrate.
§ Example materials:
§ Dielectrics: SiO2, Si3N4.
§ Metals: W, Al, others.
§ Semiconductors: Si, GaAs.
§ Versatile, conformal (coats topography)
§ Crystal structure of film can be controlled by process and/or
interactions with substrate.
from J. Chun

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CVD process physics: deposition of SiO2
1,7 : Diffusion 2-6 : Reactions
Generic: 2AB (gas) → 2A (solid) + B2 (gas)
Ex. http://www-inst.eecs.berkeley.edu/~ee143/fa10/lectures/Lec_13.pdf

2.008-F17 | 30http://www.mdpi.com/sensors/sensors-13-09513/article_deploy/html/images/sensors-13-09513f4-1024.png

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CVD: parameters
from J. Chun; http://www-inst.eecs.berkeley.edu/~ee143/fa10/lectures/Lec_13.pdf
Process parameters
§ Temperature
§ Total pressure
§ Partial pressure of reactants
§ Flow rate of reactants and
carrier gases
§ Time
Control parameters
§ Film thickness (~1-1000 nm,
getting thinner à atomic layers)
§ Film deposition rate (~nm/s)
§ Film uniformity and quality
Rate ∝e
−
Ea
kT
Log(rate)
High T Low T
Rate ∝T3/2

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CVD: quality
§ Conformal coverage
: For deep submicron devices, the step
coverage of films into high aspect ratio
features is extremely difficult.
§ Voids
: If deposition rate is too high,
voids may be left
from J. Chun

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Si wafer
Si wafer
SiO2
Deposit metal layer
Metal
Photoresist
Remove photoresist
Si wafer
SiO2
Metal

2.008-F17 | 34http://commons.wikimedia.org/wiki/File:Spin-coater_for_resist_coating_(DE).svg
Photoresist spin-coating

2.008-F17 | 35http://www.lithoguru.com/scientist/lithobasics.html
t ~ µ1/3
ω−1/2

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Si wafer
Si wafer
SiO2
Deposit metal layer
Metal
Photoresist
Remove photoresist
Si wafer
SiO2
Metal

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Photolithography: pattern transfer to the wafer
(light, UV, X-ray,
e-beam)
Mask (the pattern to
be transferred)

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Mask patterns = Chrome
Substrate = Glass (soda-lime or quartz)

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ASML wafer stepper
from J. Chun
Cost: up to $50M for 300mm wafers
Quality: sub-10nm alignment accuracy
Rate: m/s speed.
Flexibility: any mask (but masks are expensive)

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How small?
Photoresist pattern
Mask
Remove photoresist
Si wafer
SiO2
Metal
Light
k = process-dependent constant (<1)

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Shrinking circuits with water:
http://www.nature.com/scientificamerican/journal/v293/n1/full/scie
ntificamerican0705-64.html

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Remove photoresist
Si wafer
SiO2
Metal
à ‘Dry’ etching (gas or plasma) or ‘Wet’ etching (liquid)
Important:
§ Selectivity of material to be etched vs mask
§ Degree of directionality (anisotropy)
Last, etching

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Etching
Low selectivity
High selectivity

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Plasma etching (=dry etching)

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Remove photoresist
Si wafer
SiO2
Metal
What is important for high
quality fabrication of each layer?
§ …
§ …

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Reflection: semiconductor manufacturing
§ Rate?
§ Quality?
§ Cost?
§ Flexibility?
à How do these answers influence how electronic
products are designed and manufactured?

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Generic process flow
Blank Si wafer
Material addition or
removal
(Characterization)
Complete device
Final
test
Material addition
• Chemical or physical
vapor deposition
(PVD or CVD)
• Oxidation
• Doping
• Ion implantation
• Electroplating
Next step?
Material removal
• Wet etching
• Dry (gas/plasma)
etching
• Chemical/mechanical
polishing (CMP)
Pattern transfer
(lithography)

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3D transistors: Intel “FINFET”
22 nm refers to the half-pitch of the pattern, thus one transistor every 44 nm
https://www.semiwiki.com/forum/content/1709-designing-finfets.html

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The smallest transistor gate yet (UC Berkeley, 2016)
MoS2 transistors with 1-nanometer gate lengths; http://science.sciencemag.org.libproxy.mit.edu/content/354/6308/99
https://www.sciencedaily.com/releases/2016/10/161006140546.htm

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Digital light projector (DLP): micromirror array!
à Texas Instruments invented 1987, first product shipped 1996
à Now arrays of >2 million (~2000x1000) mirrors each ~5x5 um!
Texas Instruments /
http://www.memsjournal.com/2013/02/mems-based-optical-
engine-platforms-market-and-technology-overview.html

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§ Hinges: 60x600 nm, flex ±10°
§ The hinges have ~infinite fatigue life*
because their size along with the thin
film process control makes them single
crystals!!
*Array verified to 3 x 1012 cycles = 120 years life at 1000 hours per year.à 14 x 1018
individual mirror cycles without a single hinge fatigue failure!

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Mirror lifetime
Douglas, Proceedings of the SPIE, 4980:1-11, 2003.
§ Verified to 3 x 1012 cycles = 120 years life at 1000 hours
per year.
§ ~1,000,000 mirrors per device à ~1019 individual mirror
cycles without a single hinge fatigue failure!

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MEMS accelerometer (Analog Devices / Stata)

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MEMS + electronics: Package with ASIC
(Application-Specific Integrated Circuit)
§ The picture below shows a schematic of a
complete integrated circuit system inside
a package.
§ The upper right picture shows a x-ray
picture of a connected ASIC and MEMS
die with a hermetic cap.
§ The lower right picture shows an SEM
picture of the same device with the cap
removed.
Also see ST Microelectronics
http://electronics.stackexchange.com/questions/51441/how-thick-or-thin-is-the-die-wafer-inside-an-ic
http://www.elmos.com/english/products/know-how/system-in-a-package.html

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Transistors and MEMS are complicated and
sophisticated
…but uniform thin films and simple
photolithography patterns are extremely relevant
and useful!
(and also very sophisticated)

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Amazon Fire LCD display
Color filter
(rotated 45 deg)
1 mm
LCD
Display
Front Case
LCD display
Glass + touch sensors

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Manufacturing the color filter on glass
http://www.toppan.co.jp/electronics/english/display/lcd/production/
Color filter
1 mm

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Capacitive touch screen
1. Touchscreens 101: Understanding Touchscreen Technology and Design By Steve Kolokowsky, Senior Elect Design Engineer, and Trevor Davis, Senior Business
Development Manager, Cypress Semiconductor Corp.
2. Capacitive Touch Sensors Application Fields, technology overview and implementation example: Fujitsu microelectronics group
§ Indium tin oxide (ITO) electrode
pattern is deposited by
photolithography.
§ The touchscreen detects the
change in capacitance as your
finger passes over patterned ITO
electrodes.
§ Glass substrates are bonded by
pressure-sensitive adhesives.

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ITO: transparency and conductivity

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Continuous sputtering line

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Flash memory
(8 GB)
CPU (Quad-core
ARM 1.3 GHz)
(part 3 of 3)

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25,000 hours
$5.99
CREE LED light bulb

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Circuit board (PCB) manufacturing
Circuit board assembly including solder reflow
New pick-and-place technologies
Flexible and 3D circuits

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What is a circuit board made of?
§ Base board: typically an epoxy-impregnated glass fiber
sheet (e.g., ‘FR-4’).
§ Conductive traces: thin Cu foil (~0.001”), typically made by
rolling or continuous electroplating, then laminated onto the
board, then patterned by photolithography.
§ Components: pin-in-hole (PIH), surface mount (SMT); wide
range of sizes and functionalities.
§ Other features, e.g., alignment holes, insertion holes, vias.
Depends on complexity of the board (single-layer, multi-
layer, etc).

2.008-F17 | 70https://courses.cs.washington.edu/courses/cse467/04wi/lectures/ppt/Intro_to_SMT.pdf

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Single vs. multilayer PCBs

2.008-F17 | 72Groover.
May have dedicated ground, power planes; placement of
these and coupling (inductive, capacitive) between signal,
ground, power are critical to PCB performance

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PCB manufacturing steps (generic, 2-layer)
§ AOI = automated optical inspection
§ PTH = plated through holes
§ Legend = printing numbers for component placement
§ FQC/A = final quality control/assurance
http://www.pa-international.com/products/pcb-and-pcba

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Electrodeposition and etching

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Dry film photoresist: easy to apply to large substrates

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Stacking a multilayer PCB
https://courses.cs.washington.edu/courses/cse467/04wi/lectures/ppt/Intro_to_SMT.pdf

2.008-F17 | 78http://www.ourpcb.com/multilayer-pcb-5.html

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Surface mount components on Amazon Fire
Package Dimensions
200 µm
200 µm
Standard SMD
packages
https://en.wikipedia.org/wiki/Surface-
mount_technology
4516
0402

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Surface mount resistors
http://www.resistorguide.com/thin-and-thick-film/
• Thin film resistive layer is sputtered (vacuum deposition) onto a
ceramic base.
• Thickness ~ 0.1 micrometer (0.0001 mm).
• Resistance value established by photlithography and wet etching
or by laser trimming.
• Higher resistance and high tolerances, low temperature
coefficients and low noise.
• Also for high frequency applications thin film performs better than
thick film. Inductance and capacitance are generally lower.
• Higher cost compared to thick film resistors.
à Thin-film resistive layer
à Thick-film resistive layer
• Thick film resistive layers are deposited by screen printing.
• Thickness ~100 microns (0.1 mm).
• Higher power capacity and lower resistance but low (poor)
tolerance.
• Lower cost.

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Making surface-mount resistors
https://www.youtube.com/watch?v=wshRwO0MCSU

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Screen printing
https://www.youtube.com/watch?v=ENJ4FP6C970
Diagram from Kalpakjian; Screen images from Chromaline
§ Mask is typically patterned on the screen
§ Above: ‘325 mesh’ = 44 um opening, woven
stainless steel
§ Screen printing limits ~50-100 um width
and comparable feature height

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Surface-mount capacitors
KEMET Ceramic Capacitor Manufacturing
(influences capacitance and determines voltage rating)
g
AN
g
A
C
efflayers
ee ==

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Surface-mount capacitors 1. Screen-printing of electrodes on dielectric
2. Alignment and stacking of layers
including machine vision feedback
3. Singulation and thermal
processing
4. Insertion of chips in a die and
copper terminal coating
5. Electroplating of Ni and Sn on
copper terminals
6. Electrical and optical quality
control inspection
KEMET Ceramic Capacitor Manufacturing
Dielectric
Electrode

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PCB assembly: general sequence
§ Deposit solder paste by screen printing
§ Place components using pick-and-place machine (solder
is a bit sticky)
§ Solder reflow
§ Testing
§ Encapsulation/sealing (optional)

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https://www.youtube.com/watch?v=mA5tkcrkMVA
See also the ‘Scorpion’ (solder paste jetting): https://www.youtube.com/watch?v=SZ-Kq2Gkm5Y
High-speed pick and place (Essemtec)

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Essemtec pick-and-place machines
Paraquda Lynx
Cobra Paraquda Lynx
Minimum component size 0.4 mm x 0.2 mm 1.0 mm × 0.5 mm 0.6 mm × 0.3 mm
Maximum component size 80 mm x 70 mm 80 mm x 70 mm 45 mm x 45 mm
Max pick-and-place rate 21,000 cph 12,000 cph 4,500 cph
Number of feeder lanes 240 240 180
Maximum PCB size 47.24” x 15.75” 47.24” x 15.75” 15.94” x 12.00”
http://www.essemtec.com/products.asp?ArtNr=Paraquda
http://www.essemtec-usa.com/pick-place.php
Cobra

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Solder paste, reflow
Video: https://www.youtube.com/watch?v=Zw53kxy7yL0
https://courses.cs.washington.edu/courses/cse467/04wi/lectures/ppt/Intro_to_SMT.pdf

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PROBLEMS: Misalignment, non-uniform solder application,
non-uniform heating can cause detachment during reflow

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Wave soldering
à Upward force of ‘wave’ and capillary action draw solder into pin-hole gaps

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For PCB manufacturing overall
§ What are the serial versus parallel steps? How is the
process designed to account for these?
§ Propagation of errors?
§ Limitations to component size, component density
(#/area) and circuit board size?
à Limits to:
§ Rate
§ Quality
§ Cost
§ Flexibility
à Reflection on cost structure of the iPhone / Fire?

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Luxvue (Apple): micro-LED pick-and-place
à Electrostatic force used to remove small (~5-10um) semiconductor
microLED pixels from wafer, then place on target substrate (display surface)
à Takes advantage of high-density wafer fabrication process to manufacture
lower-density (pixels) displays on non-wafer substrates
à Wafer might be re-used to save cost
à microLEDs are much more efficient than current displays (e.g., OLEDs,
LCDs)
http://en.ofweek.com/news/Micro-LED-arrays-display-achieves-1-000-000-cd-m2-30427
Future?

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§ Apple Watch (2016) pixel size 87 um; 92,480 total pixels
Method of transferring and bonding an array of micro-devices
https://patentscope.wipo.int/search/en/detail.jsf?docId=WO2013119671&redirectedID=true

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Luxvue micro pick-and-place
Method of transferring and bonding an array of micro-devices
https://patentscope.wipo.int/search/en/detail.jsf?docId=WO2013119671&redirectedID=true
1 2
3 4
5 6

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Flex circuits
(Amazon Fire screen)

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Flexible circuits
Macleod, Peter. A Review of Flexible Circuit Technology and its Applications. PRIME Faraday Partnership, 2002.
Rigid+flex circuitMultilayer flex circuit
http://www.zseries.in/electro
nics%20lab/pcbs/pictures/rig
id%20flex%20pcb.jpg
http://www.tech-etch.com/flex/images/Flex-4-Layer.gif
Dielectric materials for flex circuit substrates
Polyimide (kapton)
PET
Aramid fibers (kevlar)
• High dimensional stability
• Good thermal resistance
• Flexibility and tear resistance
• Low moisture absorption
• Chemical resistance

2.008-F17 | 98
Ultrathin foil manufacturing: JX Kurami Works
(Japan), 9:00+
Full Video: https://www.dropbox.com/s/ukutmlonaf276en/JX_kurami_movie.wmv?dl=0

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Total thickness = 180 µm

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Stretching PCBs using serpentine patterns
IMEC presented at LOPEC 2015

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Thermoforming 3D circuits!
EU project ‘Terasel’ led by IMEC
§ Applications: conformal touch panels for consumer appliances, automotive interiors.
§ 3D lighting, e.g. LEDs on curved surfaces.
§ VIDEO: https://www.youtube.com/watch?v=hRhCTkQxshk

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Terasel project (1:00-2:00, 3:30+)
https://www.youtube.com/watch?v=hRhCTkQxshk

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Printed electronics
OE-A roadmap: http://www.oe-a.org/roadmap

2.008-F17 | 105
Wafer-based
patterning
Printed electronics: need high resolution (um)
and throughput (> 1 m2/s)

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