This document provides an overview of the history and fundamentals of VLSI technology and fabrication. It discusses how vacuum tubes in early electronic devices were replaced by transistors and integrated circuits. The first integrated circuits only had a few transistors, but due to continuous scaling and improvements in silicon manufacturing processes, modern chips can now contain over 1 billion transistors. The document outlines the key steps in fabricating integrated circuits, including crystal growth, wafer processing, lithography, deposition, doping, and packaging. It explains why silicon became the predominant semiconductor material and how CMOS technology replaced NMOS due to its lower power consumption. The syllabus covers topics like photolithography, diffusion, metallization, testing and packaging of integrated circuits.

1. Fundamentals of VLSI
and Fabrication Technology
Instructor
Abu Syed Md. Jannatul Islam
Lecturer, Dept. of EEE, KUET, BD
1
Department of Electrical and Electronic Engineering
Khulna University of Engineering & Technology
Khulna-9203
EE 4121 : VLSI Design and Technology

2. Vacuum tubes
• These devices
would control the
flow of electrons in
vacuum.
• Boeing B-29 would
consist of 300-
1000 vacuum
tubes. Each
additional
component would
reduce the
reliability and
increase trouble-
shooting time.
Point contact
Germanium
transistor
• 1947, John
Baden, William
Shockley and
Watter Brattain
of Bell labs
discovered this
Bipolar Junction
Transistor (BJT)
• In 1950, Shockley
developed the first
Bipolar Junction
Transistor (BJT)
First Integrated
Circuit
• In 1958, Jack Kilby
of Texas
Instruments
• two bipolar
transistors
connected on a
single piece of
silicon, thereby
initiating the
“Silicon Age”
2
A Brief History

3. 3
Scale of Integration
►Very-large-scale integration (VLSI) is the process of creating
an integrated circuit (IC) by combining hundreds of thousands
of transistors or devices into a single chip.
 This scale of growth has resulted from a continuous scaling of transistors
and other improvements in the Silicon manufacturing process.
IC’s----FF’s
2
Transistor
1958
IC’s
More than
1 Billion
Transistor
2018
Dual Core+ Core I7 (2015): 1.9billion and 22nm

4. 4
Integration & Moore’s Law
Integration Levels
SSI: 10 gates
MSI: 1000 gates
LSI: 10,000 gates
VLSI: > 10k gates
►1965: Gordon Moore(Intel cofounder) plotted transistor on each chip
►Moore's law: The number of transistors in a dense integrated circuit will
be doubled about every two years.

5. 5
Place for Integration
► Clean Room: a low level of environmental pollutants
► Company: Apple, IBM, AMD etc.

6. 6
Why Technology Scaling ?
The demand for battery-operated portable gadgets have
increased day by day with tons of applications including hearing
aids, cellular phone, laptops etc.
The “basic requirements” of such an application are less area,
lower power consumption and cheaper development.
For such portable devices, power dissipation is important
because the power provided by the battery is rather limited.
Unfortunately, battery technologies cannot be expected to
improve the battery storage capacity by more than 30% every
five years. This is not sufficient to handle the increasing power
needed in portable devices.

7.  By making transistors smaller, more circuits can be fabricated on the
silicon wafer and therefore, the circuit becomes cheaper. The
reduction in channel length enables faster switching operations since
less time is needed for the current to flow from drain to source.
 In other words, a smaller transistor leads to smaller capacitance. This
causes a reduction in transistor delay. As dynamic power is
proportional to capacitance, the power consumption also reduces.
This reduction of transistor size is called scaling.
 Each time a transistor is scaled, we say a new technology node has
been introduced. The minimum channel length of transistor is called
the technology node. For example, 0.18 micrometer, 0.13 micrometer,
90 nanometer etc.
 The scaling improves cost, performance and power consumption with
every new generation of technology.
7
Scaling and Technology Node

8. Early ICs used NMOS technology, because the NMOS process was fairly
simple, less expensive and more devices could be packed into a single
chip compared to CMOS technology. The first microprocessor was
announced by Intel in 1971.
In 1963, F. Wanlass and C. Sah of Fairchild unveiled the first logic gate in
which n-channel and p-channel transistors were used in a complementary
symmetric circuit configuration. This is what is known as CMOS today. It
draws almost zero static power dissipation.
One of the drawbacks of BJT is more static power dissipation. It means
that power is drawn even when the circuit is not switching. This limits the
maximum numbers of transistors that can be integrated into a single
silicon chip.
8
Why MOS not BJT in Integration ?

9. As static power dissipation of NMOS transistor is more
compared to CMOS, the power consumption of ICs
became a serious issue in the 1980s as thousands of
transistors were integrated into a single chip.
Due to features like low power, reliable performance
and high speed, CMOS technology would adopt and
replace NMOS and bipolar technology for nearly all
digital applications.
NMOS
CMOS
9
NMOS & CMOS

10. CMOS
• Scaling and improvement in processing technologies have led to
continuous enhancement in circuit speeds
• Improvement in packaging densities of chips
• Performance-to-cost ratios of microelectronics-based products
10
Scaling with CMOS

11. 11
Overview of Processing Technologies
►Although a number of processing technologies are available, the
majority of the production is done with traditional CMOS.
►Other processes are limited to areas where CMOS is not very
suitable (like high speed RF applications)

12. 12
VLSI Design Cycle
►The VLSI Design
cycle starts with a
formal specification
of a VLSI chip
follows a series of
steps, and eventually
produces a packaged
chip

13. 13
IC Fabrication
►The fabrication steps are sequenced to
form three dimensional regions that act as
transistors and interconnects that form
the network

14. 14
Chip Fabrication Processes

15. ►„
Silicon Wafer Manufacturing„
(CZ, FZ, Bridgeman..)
►Wafer Processing
• Deposition/Epitaxial Growth (MBE, MOCVD…)
• Oxidation…
• Patterning/Lithography
• Removal/Etching
• Diffusion and ion implantation…
• Annealing/Activation of the implanted dopants. …
►Metallization„
(Sputtering..)
►Testing, Assembly and Packaging
15
Chip Fabrication Processes

16. 16
Why Silicon?
Silicon is abundant in the earth crest as an ore in the form of quartzite
and it is a low cost material.
Other reason:
►It forms an oxide that is of very high quality, seals the surface with
very few pin holes or gaps. - this allows gap MOSFET to be more
easily made as the SiO2 forms the insulating layer for the Gate, -
SiO2 has been called the chip designers friend.
►Si readily forms a native oxide (SiO2) high-quality insulator protects
and “passivates” underlying circuitry helps in patterning useful for
dopant masking.
►It forms a very tough Nitride, Si3N4 Silicon Nitride forms a very high
bandgap insulator which is impermeable. - this is used to passivate
(seal) the die. - this also used to make hard masks and in other
process steps

17. 17
17
Why Silicon?
►Si has a very nice bandgap of ~ 1.12 eV, not too high so that room
temperature can't ionize it, and not so low that it has to high
leakage current.
►Silicon has relatively high dielectric strength and therefore is
suitable for power devices.
►It forms a very nice gate material. Most modern FET's used in VLSI
(up until the latest generations) have been called MOSFET but in
actual fact have used Si as the gate material. It turns out that it is
very easy to deposited non-crystalline Si on surfaces and it is
easily etched to great precision.
►Stable and strong material & crystal structure like diamond
►Higher operating temperature (125-175 oC vs. ~85 oC) and thus
become intrinsic at higher temp.

18. 18
 Crystal structure : diamond cubic
 Magnetic ordering: diamagnetic
 Electric resistivity : (20 °C) 103 Ω·m
 Thermal conductivity: (300 K) 149 W·m−1·K−1
 Thermal expansion : (25 °C) 2.6 µm·m−1·K−1
 Speed of sound : (thin rod) (20 °C) 8433 m/s
 Young’s modulus: 185 GPa
 Shear modulus : 52 GPa
 Bulk modulus :100 GPa
 Band gap energy at 300 K : 1.12eV
Silicon
► Large variety of process steps
possible without the problem of
decomposition (as in the case
of compound semiconductors)
► GeO2 - is partially soluble
► GaAs - does not form a oxide
► CO2 - is a gas
► Recently, SiC becoming popular
due to high temperature
tolerance and high power, high
frequency operation. …

19. 19
Crystal and Wafer Fabrication

20. 20
Crystal and wafer
A polished wafer

21. In semiconductor device fabrication, the various processing steps fall
into four general categories:
►Deposition,
►Removal,
►Patterning, and
►Modification of electrical properties.
21
Wafer Processing
►Deposition is any process that grows, coats, or otherwise transfers a
material onto the wafer. Available technologies include physical vapor
deposition (PVD), chemical vapor deposition (CVD), electrochemical
deposition (ECD), molecular beam epitaxy (MBE) and more
recently, atomic layer deposition (ALD) among others
►Removal is any process that removes material from the wafer;
examples include etch processes (either wet or dry) and chemical-
mechanical planarization (CMP).

22. ►Patterning is the shaping or altering of deposited materials, and is
generally referred to as lithography. For example, in conventional
lithography, the wafer is coated with a chemical called a photoresist;
then, a machine called a stepper focuses, aligns, and moves a mask,
exposing select portions of the wafer below to short wavelength light;
the exposed regions are washed away by a developer solution. After
etching or other processing, the remaining photoresist is removed
by plasma ashing.
22
Wafer Processing
►Modification of electrical properties has historically
entailed doping transistor sources and drains (originally by diffusion
furnaces and later by ion implantation). These doping processes are
followed by furnace annealing or, in advanced devices, by rapid
thermal annealing (RTA); annealing serves to activate the implanted
dopants. Modification is frequently achieved by oxidation, which can
be carried out to create semiconductor-insulator junctions.

23. 23
Syllabus
► Fabrication and Processing Technology:
Crystal growth, wafer preparation, photolithography,
oxidation, diffusion, ion implantation, epitaxi, metallization,
etching, NMOS and CMOS fabrication technology.
► Testing and packaging:
Overview of silicon semiconductor technology, power
dissipation, packaging, silicon on insulator.
► Introduction to GaAs technology:
Ultra-fast VLSI circuits and systems.

24. 24
►Two Class test.
►One/Two Spot test.
►At least 15-18 Lecture
►Copies of chapters will be provided when appropriate
►Recommended book:
► VLSI Technology by S. M. SZE (Available in Market)
► Silicon VLSI Technology by Plummer
► Other references: Will be provided in due time.
Tests and References