The document discusses the manufacturing process for CMOS integrated circuits. It describes the key steps which include wafer preparation, oxidation, diffusion, ion implantation, deposition, etching, and planarization. It emphasizes that design rules must be followed to ensure the functionality of the final circuit, as they define the minimum allowed dimensions and act as an agreement between designers and process engineers.

1. EE603 – CMOS IC DESIGN
Topic 2
Manufacturing Process
Faizah Amir
POLISAS
TEKNOLOGI
TERASPEMBANGUNAN

2. Lesson Learning Outcome
At the end of this session, you should be able to:
• explain the manufacturing process for CMOS
integrated circuit.
• apply the design rules in designing CMOS
layout.
Introduction Video

3. Stages of IC Fabrication
Silicon ingot & Wafer

4. Preparation of Silicon Wafer
1. Crystal Growth
2. Single Crystal
Ingot
3. Crystal Trimming
and Diameter
Grind
4. Flat Grinding
5. Wafer Slicing
6. Edge Rounding
7. Lapping
8. Wafer Etching
9. Polishing
10. Wafer Inspection
Slurry
Polishing table
Polishing
head
Polysilicon Seed crystal
Heater
Crucible

5. Wafer
A wafer is a thin slice of
semiconductor material such as a
silicon crystal, used in the
fabrication of integrated circuits
and other micro-devices.
Wafer is the base material for IC
manufacturing process.
Diameter of wafer is typically
between 4 and 12 inches (10 and 30
cm, respectively) and a thickness of at
most 1 mm.
Wafers are obtained by cutting a
single-crystal ingot into thin
slices.

6. Wafer Properties Required in IC Manufacturing
Silicon wafer must be in the form of a single-crystalline,
lightly doped wafer.
The surface of the wafer is doped more heavily and a
single crystal epitaxial layer of the opposite type is
grown over the surface.
Diameter of wafer is typically between 4 and 12 inches (10
and 30 cm, respectively) and a thickness of at most 1 mm.

7. Silicon Wafer
The wafer size is increasing
from time to time to ensure that
the die yield is high.

8. Fundamental of IC Process
Step
Basic Steps:
• Oxide growth
• Thermal diffusion
• Ion implantation
• Deposition
• Etching
• Planarization
Photolithography
• Photolithography is the means by which the above steps
are applied to selected areas of the silicon wafer.
Silicon Wafer

9. Oxidation
Description:
• Oxidation is the process by which a layer of
silicon dioxide is grown on the surface of a silicon
wafer.
Uses:
• Protect the underlying material from contamination
• Provide isolation between two layers.
Very thin oxides (100Å to 1000Å) are grown using dry oxidation
techniques. Thicker oxides (>1000Å) are grown using wet
oxidation techniques

10. Diffusion
• Diffusion is the movement of impurity atoms at the surface
of the silicon into the bulk of the silicon.
• Always in the direction from higher concentration to lower
concentration. A gas containing the dopant is introduced in
the tube.
• Diffusion is typically done at high temperatures: 800 to
1400°C

11. Diffusion

12. Diffusion
 Predeposition
• Dopant source is supplied.
• Wafer is heated between 1000°C to 1200°C.
• Dopant is deposited by controlling time and
temperature in the specified amount of dopant.
• Impurities is deposited on the wafer surface until the
solid solubility level is achieved.
Dopant
atoms

13. Diffusion
 Drive in
• No more dopant is supplied.
• Drive in is done to drive the dopants on the wafer
surface into the substrate according to the specified
depth by controlling temperature and time.
• Variable such as time, temperature and ambient gas is
controlled to obtain the specified junction depth.
Dopant atoms driven
into the wafer

14. Ion Implantation
 Ion implantation method is used widely in large scale
IC fabrication.
 Dopant ion beam (boron @ phosphorus) is
accelerated with high energy(10-1000eV).
 Ion implantation causes crystalline damage which
must be annealed.

15. Ion Implantation
• Ion implantation is the process by which impurity ions are
accelerated to a high velocity and physically lodged into the
target material.
• Annealing is required to activate the impurity atoms and
repair the physical damage to the crystal lattice. This step
is done at 500 to 800°C.
• Ion implantation is a lower temperature process compared to
diffusion.
• Can implant through surface layers, thus it is useful for field-
threshold adjustment.
• Can achieve unique doping profile such as buried
concentration peak.

16. Ion Implantation

17. Deposition
Deposition is the means by which various materials are
deposited on the silicon wafer.
Examples:
• Silicon nitride (Si3N4)
• Silicon dioxide (SiO2)
• Aluminum
• Polysilicon
There are various ways to deposit a material on a substrate:
• Chemical-vapour deposition (CVD)
• Low-pressure chemical-vapour deposition (LPCVD)
• Plasma-assisted chemical-vapour deposition (PECVD)
• Sputter deposition
Material that is being deposited using these techniques
covers the entire wafer and requires no mask.

18. Deposition

19. Etching
Etching is a process of selectively removing the unwanted material from
the surface of the wafer.
When etching is performed, the etchant may remove portions or all of:
• The desired material
• The underlying layer
• The masking layer
There are basically two types of etches:
• Wet etch which uses chemicals
• Dry etch which uses chemically active ionized gases/plasma.

20. Etching
• Wet etching
 Liquid chemicals such as acids, bases and solvents are used to
chemically remove wafer surface material.
 Certain etching agent will etch only certain material.
 Wet etch is generally applicable only for larger geometries
(>3µm).
 The disadvantage of wet etching is that it can cause undercutting
(the pattern size is not the same as the mask size).
 Undercutting happens because wet etching is isotropic (etching
happens in all direction).
WET ETCHING

21. Etching
ETCHANTS ETCHED LAYER
HIDROFLORIC ACID / NITRIC ACID SiO2
HIDROFLORIC ACID SILICON NITRATE
HIDROFLORIC ACID / NITRIC / ACETIC ALUMINIUM
NITRIC ACID + HIDROFLORIC ACID POLYSILICON
SULFURIC ACID + ASETON + TRICHLOROETERINE PHOTO RESIST
ETCHANTS

22. Etching
• Dry etch exposes the wafer surface to a plasma created
in the gaseous state. The plasma passes through the
openings in the patterned resist and interacts physically
or chemically (or both) with the wafer to remove the
surface material.
• Etching will happen only at the targeted area
(anisotropic).
• Pattern size produced is the same as the image on
mask size.
• Dry etch is generally applicable for smaller geometries
(<2µm).
DRY ETCHING/PLASMA ETCHING

23. Etching
DIFFERENCES BETWEEN WET ETCHING AND DRY ETCHING
Wet Etching Dry Etching
1. Etching is done using liquid
chemical.
Etching is done using plasma.
2. Inexpensive. Highly cost.
3. Etching rate is not uniform. Etching rate is uniform.
4. Undercutting will happen that
cause the pattern size is larger
than the size of image on the
mask.
The pattern size is the same as
the size of image on the mask.
5. If phosphoric acid is used to etch
certain material, the photoresist is
also being etched.
Photoresist lifting will not occur.
6. Isotropic Anisotropic

24. Etching

25. Planarization
Planarization attempts to minimize the variation in surface
height of the wafer.
Planarization techniques
• Repeated applications of spin-on-glass (SOG).
• Resist etch-back – highest areas of oxide are exposed
longest to the etchant and therefore erode away the most.
A chemical-mechanical planarization (CMP) step is
included before the deposition of an extra metal layer on
top of the insulating SiO2 layer.

26. Planarization
Chemical Mechanical Polishing (CMP)
• CMP produces the required degree of planarization
for modern submicron technology.

27. Manufacturing Process
Sequence of N-Dual- Well
CMOS Circuit

28. Manufacturing Process
Sequence of N-Dual- Well
CMOS Circuit
1.
Active area
p+ substrate
p - epi

29. Manufacturing Process
Sequence of N-Dual- Well
CMOS Circuit
2.
n+ dopants
p+ dopants
p+ substrate
p+ substrate
p - epi
p - epi

30. Manufacturing Process
Sequence of N-Dual- Well
CMOS Circuit
3.
p+ substrate
p - epi
p n

31. Manufacturing Process
Sequence of N-Dual- Well
CMOS Circuit
4.
p-epi
p+ substrate
Contact

32. Manufacturing Process
Sequence of N-Dual- Well
CMOS Circuit
5.
Chip Manufacturing Video

33. Design Rules
 Design rule is a set of regulations which
define the acceptable dimensions and
electrical characteristics achievable in a
fabrication process.
3D Perspective of NMOS Transistor

34. Design Rules
• Interface between designer and process engineer
• Guidelines for constructing process masks
• Unit dimension: Minimum line width
» scalable design rules: lambda (λ) parameter
» absolute dimensions (micron rules)

35. Design Rules
Lambda (λ ) parameter
 can define design rules in terms of lambdas.
 can easily be scaled to different fabrication process as
fabrication technology advances.
 1λ = 1/2 minimum feature size,
e.g, in 0. 6μm process, 1λ=0.3μm

36. Design Rules
Micron rules
 1 micron = 1µm = 1x10-6
m
 Technology size @ feature size is mentioned in
micron unit, e.g. feature size of 0.5 micron implies
that the distance between the source and drain is 0.5µm.
* A single strand of hair usually has a diameter of 20
to 180µm.

37. CMOS Process Layer

38. Intra -Layer Design Rules
5
5
2
λ
3 3 3
A few common design rules:

39. Verifying The Layout
• The layout must be verified to ensure that
none of the design rules is violated.
• Failing to obey the design rules will surely
lead to a non-functional design.
• Verifying the layout is now done by
computers using Computer-aided Design-
Rule Checking (called DRC).

40. SUMMARY
• The manufacturing process of integrated circuits
require a large number of steps each of which
consists of a sequence of basic operations.
• The design rules set define the constraints in terms
of minimum width and separation that the IC design
has to adhere to if the resulting circuit is to be fully
functional. This design rules acts as the contract
between the circuit designer and the process
engineer.