The majority of electronic failures occur due to thermally induced stresses and strains caused by excessive differences in coefficients of thermal expansion (CTE) across materials.
CTE mismatches occur in both 1st and 2nd level interconnects in electronics assemblies.
-1st level interconnects connect the die to a substrate.
-This substrate can be underfilled so there are both global and local CTE mismatches to consider.
-2nd level interconnects connect the substrate, or package, to the printed circuit board (PCB). This would be considered a “board level” CTE mismatch.
-Several stress and strain mitigation techniques exist including the use of conformal coating.
The purpose of this presentation is to show that accelerated testing can be successfully used to predict solder joint and plated through hole (PTH) fatigue behavior.
The Effect of Coating and Potting on the Reliability of QFN DevicesCheryl Tulkoff
The lack of a compliant lead structure makes QFN devices more susceptible to PCB warpage related failures:
oMechanical properties of the potting material
oGlass transition temperature (Tg)
oModulus should be specified above and below the Tg
oCTE should be specified above and below the Tg
The design of the housing:
oMay provide a surface to which the potting material can pull against when shrinking causing PCB warpage
oShould be designed to provide as close to a hydrostatic pressure as possible (equal pressure on all sides)
Today, plastic packaged integrated circuits are ubiquitous even for high-reliability applications. Reliability testing and standards play a key role in reliability engineering to achieve the necessary reliability performance. Traditional stress-based standards are easy to use but often over- or under-stress units and don’t focus on key vulnerabilities, particularly moisture-related ones. Knowledge-based standards have evolved to fix this, but rely on knowledge of mechanisms, control of board manufacturing conditions, and understanding and specifying end use conditions. This motivates a survey of plastic package mechanisms and testing with particular focus on moisture-related mechanisms and testing. The moisture-related examples will cover HAST testing, and the “popcorn” mechanism.
Learning Objectives
1.Understand the philosophy and methods behind reliability testing of ICs as applied to plastic-packaged ICs.
2.Learn the historical development of the JEDEC temperature-humidity-bias (HAST) moisture reliability testing standard.
3.Get a practical overview of key thermal, thermo-mechanical, moisture (chemical), and moisture (“popcorn”) mechanisms.
4.Appreciate how transformation of environmental conditions to conditions at the site of failure in the package is used to “scale” reliability models.
Reliable Plated Through-Via Design and FabricationCheryl Tulkoff
The base knowledge and understanding of PTV Fatigue is robust
-Decades of testing and simulation
-Use of reliability physics is best practice
-Detailed understanding is still missing
-Key expertise (process parameters, material properties, simulation, testing) is rarely in the same organization
-Not a pure science activity (significant amount of human influence)
-Improvements in out-of-plane CTE and plating properties have greatly improved PTV performance
-Avoiding defects continues to be the biggest risk
How to find defects in SMT electronics manufacturingBill Cardoso
This presentation covers several examples of defects found in today's SMT electronics manufacturing lines. Learn how x-rays can be used to find these defects, and most importantly, diagnose your manufacturing line.
All x-ray images taken with TruView X-Ray Inspection systems.
- Where Are Defects Introduced in the SMT production line?
- Solder Paste Application Defects
- Component Placement Defects
- Reflow Oven Defects
- Statistical Process Control
The Effect of Coating and Potting on the Reliability of QFN DevicesCheryl Tulkoff
The lack of a compliant lead structure makes QFN devices more susceptible to PCB warpage related failures:
oMechanical properties of the potting material
oGlass transition temperature (Tg)
oModulus should be specified above and below the Tg
oCTE should be specified above and below the Tg
The design of the housing:
oMay provide a surface to which the potting material can pull against when shrinking causing PCB warpage
oShould be designed to provide as close to a hydrostatic pressure as possible (equal pressure on all sides)
Today, plastic packaged integrated circuits are ubiquitous even for high-reliability applications. Reliability testing and standards play a key role in reliability engineering to achieve the necessary reliability performance. Traditional stress-based standards are easy to use but often over- or under-stress units and don’t focus on key vulnerabilities, particularly moisture-related ones. Knowledge-based standards have evolved to fix this, but rely on knowledge of mechanisms, control of board manufacturing conditions, and understanding and specifying end use conditions. This motivates a survey of plastic package mechanisms and testing with particular focus on moisture-related mechanisms and testing. The moisture-related examples will cover HAST testing, and the “popcorn” mechanism.
Learning Objectives
1.Understand the philosophy and methods behind reliability testing of ICs as applied to plastic-packaged ICs.
2.Learn the historical development of the JEDEC temperature-humidity-bias (HAST) moisture reliability testing standard.
3.Get a practical overview of key thermal, thermo-mechanical, moisture (chemical), and moisture (“popcorn”) mechanisms.
4.Appreciate how transformation of environmental conditions to conditions at the site of failure in the package is used to “scale” reliability models.
Reliable Plated Through-Via Design and FabricationCheryl Tulkoff
The base knowledge and understanding of PTV Fatigue is robust
-Decades of testing and simulation
-Use of reliability physics is best practice
-Detailed understanding is still missing
-Key expertise (process parameters, material properties, simulation, testing) is rarely in the same organization
-Not a pure science activity (significant amount of human influence)
-Improvements in out-of-plane CTE and plating properties have greatly improved PTV performance
-Avoiding defects continues to be the biggest risk
How to find defects in SMT electronics manufacturingBill Cardoso
This presentation covers several examples of defects found in today's SMT electronics manufacturing lines. Learn how x-rays can be used to find these defects, and most importantly, diagnose your manufacturing line.
All x-ray images taken with TruView X-Ray Inspection systems.
- Where Are Defects Introduced in the SMT production line?
- Solder Paste Application Defects
- Component Placement Defects
- Reflow Oven Defects
- Statistical Process Control
Design for reliability in automotive electronicsGil Sharon
This is a slide show that I presented last year in Detroit. This presentation talks about what it takes to design reliable electronics in automotive applications. There is a brief primer on reliability in general and a discussion on the effects of temperature cycling on solder and copper fatigue.
Thermo-Mechanical Simulation of Through Silicon Stack AssemblyKamal Karimanal
The electronics industry has been using Finite Element Analysis (FEA) to model IC package assembly process for understanding the effects of process conditions, material choice as well as design parameters. What was already practiced as an engineering-art within packaging organizations for monolithic IC packages has now become more complex due to the need for collaboration across organizational walls in the case of 3D stacking. The holistic solution needed for collaborative engineering of 3D stacking process calls for streamlined methodologies and information exchange protocols.
This presentation will introduce the idea of automated chip stacking process modeling approach with detailed discussions on inputs needed, gaps in existing modeling methodologies and output metrics of engineering relevance. The presentation will discuss wafer level warpage due to thinning and RDL films, their control, assembly implications of different under filling and encapsulation processes and pre attach warpage at reflow temperature
The Phase Field Method: Mesoscale Simulation Aiding Materials DiscoveryPFHub PFHub
Two types of computational materials science, model development and materials discovery. PF is used less than atomic scale methods. PF focused on model development not discovery. How to use PF for materials discovery?
Pad Cratering: Prevention, Mitigation and Detection StrategiesCheryl Tulkoff
Pad cratering is defined as cracking which initiates within the laminate during a dynamic mechanical event such as In Circuit Testing (ICT), board depanelization, connector insertion, and other shock and vibration inducing activities.
During this tutorial, you'll learn about the key drivers, measurement and detection protocols, and preventive tactics for this serious but prevalent failure. Pad cratering was first recognized in BGA packages but newer leadless, bottom termination components are also vulnerable.
Electroplating, Phosphating, Powder Coating and Metal Finishing Ajjay Kumar Gupta
Electroplating, Phosphating, Powder Coating and Metal Finishing (Electroplating Plant, Copper Plating, Electroforming, Brass Plating, Silver Plating, Tin-Nickel Alloy Plating, Gold Plating (Gilding), Cadmium Plating, Zinc Plating)
Electroplating is a process that uses electric current to reduce dissolved metal cations so that they form a thin coherent metal coating on an electrode. The term is also used for electrical oxidation of anions onto a solid substrate, as in the formation silver chloride on silver wire to make silver/silver-chloride electrodes. Electroplating is primarily used to change the surface properties of an object (e.g. abrasion and wear resistance, corrosion protection, lubricity, aesthetic qualities, etc.), but may also be used to build up thickness on undersized parts or to form objects by electroforming.
See more
https://goo.gl/bKk1XU
https://goo.gl/5QasBV
https://goo.gl/sBmyLI
Contact us:
Niir Project Consultancy Services
106-E, Kamla Nagar, Opp. Spark Mall,
New Delhi-110007, India.
Email: npcs.ei@gmail.com , info@entrepreneurindia.co
Tel: +91-11-23843955, 23845654, 23845886, 8800733955
Mobile: +91-9811043595
Website: www.entrepreneurindia.co , www.niir.org
Tags
Electroplating Plant, Automatic Equipment, Surface Coatings and Treatments, Electroplating and Coating Plants, Electroplating Plant Equipment, Powder Coating Plants, Powder Coating Equipments, How to Start Powder Coating Business, Powder Coating Business Plan, Business Plan on Powder Coating, Start Powder Coating Business, Start High Profit Powder Coating Business, Starting Metal Polishing Business, Electroplating Business, Gold Plating Business, How to Start Metal Plating Business, Starting Zinc Plating Business, How to Start Electroplating Business, How to Start Metal Finishing Business, Starting Metal Polishing Business, Metal Finishing Industry, Business Plans for Metal Finishing, Zinc Plating Process, Zinc Plating Plant, Electroplating Plant for Acid Zinc, Electroplating Plant Equipment, Fixed Sequence Automatic Plating Plant, Trojan and Gem Type Automatic Plant, Vulcan Lattice Arm Type Automatic Plant, Titan Type Automatic Plant, Digit Pivoted Arm Type Automatic Plant, Straight-Through Type Automatic Plant, Methods of Transporter Control, Microprocessor and Computer Control, Semi-Automatic Plating Plant, Barrel Planting Plant, Suitability of Articles for Barrel Plating, Glydo/Glydette Barrel Plating Equipment, Calculation of Work Loads, Manual Planting Plant, Single Station Barrel Plating Units, Modular Plant and Specialised Equipment for Electronics Industry, Electroplating Equipment, Welded Steel Tanks, Plastic Tanks Reinforced with Glass Fibre, Tank Lining Materials, Glass Fibre (GRP) Tanks, Treatment of Rubber Linings, Ilex Grade Plastic Lined Tanks, Galvanised Steel Coils, Lead and Lead Alloy Coils, Titanium Coils, Metal Cased Heaters, Teflon Immersion Heaters, Silica Cased Heaters
We designed and manufactured Auto Insertion machine in Shenzhen China, and provide SMT equipments, spare parts services support.
Please email: jasonwu@smthelp.com
High Entropy Alloys are a new class of alloys discovered to perform at potentially useful applications. Eg : CoCrFeMnNi is useful for Cryogenic applications and MoNbTaWV is useful for Refractory applications.
High Entropy Alloy was discovered in 1996. Being a completely new topic, it is unknown to us in all aspects. It's excellent combination of all mechanical properties is representing a new frontier in Materials Engineering field of research.
Fatigue is important as it is the largest cause of failure in metals, estimated to comprise approximately 90% of all metallic failures; polymers and ceramics are also susceptible to this type of failure.
Phase Change Materials as an Alternative to Thermal Grease for Networking Applications - a technical comparison of Thermal Interface Materials in networking applications. Presented jointly by Juniper Networks and Honeywell Electronic Materials.
Design for reliability in automotive electronicsGil Sharon
This is a slide show that I presented last year in Detroit. This presentation talks about what it takes to design reliable electronics in automotive applications. There is a brief primer on reliability in general and a discussion on the effects of temperature cycling on solder and copper fatigue.
Thermo-Mechanical Simulation of Through Silicon Stack AssemblyKamal Karimanal
The electronics industry has been using Finite Element Analysis (FEA) to model IC package assembly process for understanding the effects of process conditions, material choice as well as design parameters. What was already practiced as an engineering-art within packaging organizations for monolithic IC packages has now become more complex due to the need for collaboration across organizational walls in the case of 3D stacking. The holistic solution needed for collaborative engineering of 3D stacking process calls for streamlined methodologies and information exchange protocols.
This presentation will introduce the idea of automated chip stacking process modeling approach with detailed discussions on inputs needed, gaps in existing modeling methodologies and output metrics of engineering relevance. The presentation will discuss wafer level warpage due to thinning and RDL films, their control, assembly implications of different under filling and encapsulation processes and pre attach warpage at reflow temperature
The Phase Field Method: Mesoscale Simulation Aiding Materials DiscoveryPFHub PFHub
Two types of computational materials science, model development and materials discovery. PF is used less than atomic scale methods. PF focused on model development not discovery. How to use PF for materials discovery?
Pad Cratering: Prevention, Mitigation and Detection StrategiesCheryl Tulkoff
Pad cratering is defined as cracking which initiates within the laminate during a dynamic mechanical event such as In Circuit Testing (ICT), board depanelization, connector insertion, and other shock and vibration inducing activities.
During this tutorial, you'll learn about the key drivers, measurement and detection protocols, and preventive tactics for this serious but prevalent failure. Pad cratering was first recognized in BGA packages but newer leadless, bottom termination components are also vulnerable.
Electroplating, Phosphating, Powder Coating and Metal Finishing Ajjay Kumar Gupta
Electroplating, Phosphating, Powder Coating and Metal Finishing (Electroplating Plant, Copper Plating, Electroforming, Brass Plating, Silver Plating, Tin-Nickel Alloy Plating, Gold Plating (Gilding), Cadmium Plating, Zinc Plating)
Electroplating is a process that uses electric current to reduce dissolved metal cations so that they form a thin coherent metal coating on an electrode. The term is also used for electrical oxidation of anions onto a solid substrate, as in the formation silver chloride on silver wire to make silver/silver-chloride electrodes. Electroplating is primarily used to change the surface properties of an object (e.g. abrasion and wear resistance, corrosion protection, lubricity, aesthetic qualities, etc.), but may also be used to build up thickness on undersized parts or to form objects by electroforming.
See more
https://goo.gl/bKk1XU
https://goo.gl/5QasBV
https://goo.gl/sBmyLI
Contact us:
Niir Project Consultancy Services
106-E, Kamla Nagar, Opp. Spark Mall,
New Delhi-110007, India.
Email: npcs.ei@gmail.com , info@entrepreneurindia.co
Tel: +91-11-23843955, 23845654, 23845886, 8800733955
Mobile: +91-9811043595
Website: www.entrepreneurindia.co , www.niir.org
Tags
Electroplating Plant, Automatic Equipment, Surface Coatings and Treatments, Electroplating and Coating Plants, Electroplating Plant Equipment, Powder Coating Plants, Powder Coating Equipments, How to Start Powder Coating Business, Powder Coating Business Plan, Business Plan on Powder Coating, Start Powder Coating Business, Start High Profit Powder Coating Business, Starting Metal Polishing Business, Electroplating Business, Gold Plating Business, How to Start Metal Plating Business, Starting Zinc Plating Business, How to Start Electroplating Business, How to Start Metal Finishing Business, Starting Metal Polishing Business, Metal Finishing Industry, Business Plans for Metal Finishing, Zinc Plating Process, Zinc Plating Plant, Electroplating Plant for Acid Zinc, Electroplating Plant Equipment, Fixed Sequence Automatic Plating Plant, Trojan and Gem Type Automatic Plant, Vulcan Lattice Arm Type Automatic Plant, Titan Type Automatic Plant, Digit Pivoted Arm Type Automatic Plant, Straight-Through Type Automatic Plant, Methods of Transporter Control, Microprocessor and Computer Control, Semi-Automatic Plating Plant, Barrel Planting Plant, Suitability of Articles for Barrel Plating, Glydo/Glydette Barrel Plating Equipment, Calculation of Work Loads, Manual Planting Plant, Single Station Barrel Plating Units, Modular Plant and Specialised Equipment for Electronics Industry, Electroplating Equipment, Welded Steel Tanks, Plastic Tanks Reinforced with Glass Fibre, Tank Lining Materials, Glass Fibre (GRP) Tanks, Treatment of Rubber Linings, Ilex Grade Plastic Lined Tanks, Galvanised Steel Coils, Lead and Lead Alloy Coils, Titanium Coils, Metal Cased Heaters, Teflon Immersion Heaters, Silica Cased Heaters
We designed and manufactured Auto Insertion machine in Shenzhen China, and provide SMT equipments, spare parts services support.
Please email: jasonwu@smthelp.com
High Entropy Alloys are a new class of alloys discovered to perform at potentially useful applications. Eg : CoCrFeMnNi is useful for Cryogenic applications and MoNbTaWV is useful for Refractory applications.
High Entropy Alloy was discovered in 1996. Being a completely new topic, it is unknown to us in all aspects. It's excellent combination of all mechanical properties is representing a new frontier in Materials Engineering field of research.
Fatigue is important as it is the largest cause of failure in metals, estimated to comprise approximately 90% of all metallic failures; polymers and ceramics are also susceptible to this type of failure.
Phase Change Materials as an Alternative to Thermal Grease for Networking Applications - a technical comparison of Thermal Interface Materials in networking applications. Presented jointly by Juniper Networks and Honeywell Electronic Materials.
SCR and TTR modeling using shell and beam elements to deal with local interests, such as touch-down compression or buckling. Two examples are presented. The FEA tool employed is ABAQUS. Videos can only be seen when downloaded.
International Journal of Engineering Research and Development (IJERD)IJERD Editor
We would send hard copy of Journal by speed post to the address of correspondence author after online publication of paper.
We will dispatched hard copy to the author within 7 days of date of publication
A memory stack on logic 3D IC stack was considered for comparative study of warpage response to two different process choices, namely, Die to Die (D2D) and Package to Die (P2D) assembly. Process and reliability modeling software CielMech, and Commercial Finite Element Analysis (FEA) software ANSYS Mechanical were utilized to simulate thermo-mechanical effects of sequential chip attach, underfilling and encapsulation process steps for the chosen flows. Warpage at room temperature as well as attach temperature after each attach step were compared. Results indicated that underfill, substrate, and mold compound thermal strains play important roles in warpage evolution. Significant differences in the final assembled state warpage was predicted and is attributable to path dependence of warpage evolution.
Solving Problems with Reliability in the Lead-Free EraCheryl Tulkoff
This presentation provides a focused but comprehensive discussion on potential reliability issues that can arise within Pb-free processes. Areas of potential high risk are examined. For each reliability concern, a brief description is provided, followed by the current state of industry knowledge and an opportunity for risk mitigation based upon the product design, materials, complexity, volumes, and customer expectations of reliability. A final summary provides the attendees a roadmap for ensuring the reliability of Pb-free product.
A Study on Stochastic Thermal Characterization of Electronic PackagesIJERA Editor
Insofar as the electronics can be found now in several applications of multiple domains, we have tried to
highlight in this study that, those systems must be based on unquestionable reliability and meet the needs of the
external environment. Starting from the unit "°c / w" concerning the thermal resistance from the gap between
junction temperature and a reference temperature, we have tried to compare the thermal performance of
electronic packages taking into consideration the thermal management. Our approach is based on the Monte
Carlo simulation and the stochastic characterization of the QFN. From the norm of normalization, we have
obtained standardized data sheets allowing accurate comparisons of the thermal performance of electronic
packages as produced by different manufacturers. Our numerical model through simulation, prototyping
concerning the design involves the JEDEC recommendations, which we consider a very interesting alternative.
Through the deterministic analysis, we conducted an analysis from the Matlab program parameters, which
control the Ansys software, the results were processed by statistical techniques to evaluate the times of the
thermal resistance of the QFN. That is why we must consider the electronic package (encapsulating the
integrated circuit), through the printed circuit board (PCB) to ensure the junction temperature maintenance and
avoid the dissipation of the heat. Also our process was based on the union of the finite element method to the
Monte Carlo simulation and stochastic characterization of the QFN.
Keywords: Electronic package; Finite element method; printed
Thermal Stress Analysis of Electro Discharge MachiningIJESFT
Procedures and results of experimental work to find thermal stress analysis in electric discharge machined surfaces are presented. In this study, an axisymmetric thermo-physical FEA model for the simulation of single sparks machining during electrical discharge machining (EDM) process is shown. This model has been solved using ANSYS 14.0 software. A transient thermal analysis assuming a Gaussian distribution heat source with temperature-dependent material properties is used to investigate the stress analysis based on temperature distribution. The effect on significant machining parameters (Gap current – Gap voltage) on aforesaid responses had been investigated and found that the stresses sharply changes with the parameters [1].
The FEA model is used to study the relation between these parameters and maximum temperature attended at the end of cycle which is further used to find residual stress produced at the end of cooling cycle. To find residual stresses in the work piece during EDM, the temperature distribution at the end of pulse duration in the work piece has to be estimated [2]
High residual thermal stresses are developed on the surfaces of electric discharge machined parts because of the high temperature gradients generated at the gap during electrical discharge machining (EDM) in a small heat-affected zone. These thermal stresses can be responsible for micro-cracks, decrease in fatigue life and strength and possibly catastrophic failure. The results of the analysis show high temperature gradient zones and the regions of large stresses where, sometimes, they exceed the material yield strength. A transient thermal analysis assuming a Gaussian distribution heat can be used to investigate the Stress analysis.
A Silicon-to-System Thermo-Mechanical Review of ElectronicsKamal Karimanal
A Silicon-to-System Review of Thermo-Mechanical Considerations in Electronics
Author: Kamal Karimanal, Cielution LLC
Thermal and Mechanical challenges to IC package reliability has been addressed with a sufficiently working system of information exchange across a supply chain that spans the foundries to system level assembly plants.The never ending market demand for miniaturization, performance, functionality and cost reduction invariably translates to manufacturing, design, assembly, and reliability challenges to the engineer. Within the Thermal and Mechanical realm these challenges manifest to the engineer in the form of seemingly disconnected problems areas such as BEOL yield, flipchip interconnect reliability, warpage mitigation, heat sink retention design, interface choice, thermally aware board and chassis layout, fan sizing and system level optimization. Evolving technology also introduces newer puzzles such as heterogeneous packaging using 3D ICs. The talk will focus on the tools, methodologies and information exchange protocols used by the thermal management and mechanical reliability professionals across the supply chain to address the various challenges.
Securing your Kubernetes cluster_ a step-by-step guide to success !KatiaHIMEUR1
Today, after several years of existence, an extremely active community and an ultra-dynamic ecosystem, Kubernetes has established itself as the de facto standard in container orchestration. Thanks to a wide range of managed services, it has never been so easy to set up a ready-to-use Kubernetes cluster.
However, this ease of use means that the subject of security in Kubernetes is often left for later, or even neglected. This exposes companies to significant risks.
In this talk, I'll show you step-by-step how to secure your Kubernetes cluster for greater peace of mind and reliability.
Connector Corner: Automate dynamic content and events by pushing a buttonDianaGray10
Here is something new! In our next Connector Corner webinar, we will demonstrate how you can use a single workflow to:
Create a campaign using Mailchimp with merge tags/fields
Send an interactive Slack channel message (using buttons)
Have the message received by managers and peers along with a test email for review
But there’s more:
In a second workflow supporting the same use case, you’ll see:
Your campaign sent to target colleagues for approval
If the “Approve” button is clicked, a Jira/Zendesk ticket is created for the marketing design team
But—if the “Reject” button is pushed, colleagues will be alerted via Slack message
Join us to learn more about this new, human-in-the-loop capability, brought to you by Integration Service connectors.
And...
Speakers:
Akshay Agnihotri, Product Manager
Charlie Greenberg, Host
Builder.ai Founder Sachin Dev Duggal's Strategic Approach to Create an Innova...Ramesh Iyer
In today's fast-changing business world, Companies that adapt and embrace new ideas often need help to keep up with the competition. However, fostering a culture of innovation takes much work. It takes vision, leadership and willingness to take risks in the right proportion. Sachin Dev Duggal, co-founder of Builder.ai, has perfected the art of this balance, creating a company culture where creativity and growth are nurtured at each stage.
Dev Dives: Train smarter, not harder – active learning and UiPath LLMs for do...UiPathCommunity
💥 Speed, accuracy, and scaling – discover the superpowers of GenAI in action with UiPath Document Understanding and Communications Mining™:
See how to accelerate model training and optimize model performance with active learning
Learn about the latest enhancements to out-of-the-box document processing – with little to no training required
Get an exclusive demo of the new family of UiPath LLMs – GenAI models specialized for processing different types of documents and messages
This is a hands-on session specifically designed for automation developers and AI enthusiasts seeking to enhance their knowledge in leveraging the latest intelligent document processing capabilities offered by UiPath.
Speakers:
👨🏫 Andras Palfi, Senior Product Manager, UiPath
👩🏫 Lenka Dulovicova, Product Program Manager, UiPath
JMeter webinar - integration with InfluxDB and GrafanaRTTS
Watch this recorded webinar about real-time monitoring of application performance. See how to integrate Apache JMeter, the open-source leader in performance testing, with InfluxDB, the open-source time-series database, and Grafana, the open-source analytics and visualization application.
In this webinar, we will review the benefits of leveraging InfluxDB and Grafana when executing load tests and demonstrate how these tools are used to visualize performance metrics.
Length: 30 minutes
Session Overview
-------------------------------------------
During this webinar, we will cover the following topics while demonstrating the integrations of JMeter, InfluxDB and Grafana:
- What out-of-the-box solutions are available for real-time monitoring JMeter tests?
- What are the benefits of integrating InfluxDB and Grafana into the load testing stack?
- Which features are provided by Grafana?
- Demonstration of InfluxDB and Grafana using a practice web application
To view the webinar recording, go to:
https://www.rttsweb.com/jmeter-integration-webinar
Kubernetes & AI - Beauty and the Beast !?! @KCD Istanbul 2024Tobias Schneck
As AI technology is pushing into IT I was wondering myself, as an “infrastructure container kubernetes guy”, how get this fancy AI technology get managed from an infrastructure operational view? Is it possible to apply our lovely cloud native principals as well? What benefit’s both technologies could bring to each other?
Let me take this questions and provide you a short journey through existing deployment models and use cases for AI software. On practical examples, we discuss what cloud/on-premise strategy we may need for applying it to our own infrastructure to get it to work from an enterprise perspective. I want to give an overview about infrastructure requirements and technologies, what could be beneficial or limiting your AI use cases in an enterprise environment. An interactive Demo will give you some insides, what approaches I got already working for real.
UiPath Test Automation using UiPath Test Suite series, part 4DianaGray10
Welcome to UiPath Test Automation using UiPath Test Suite series part 4. In this session, we will cover Test Manager overview along with SAP heatmap.
The UiPath Test Manager overview with SAP heatmap webinar offers a concise yet comprehensive exploration of the role of a Test Manager within SAP environments, coupled with the utilization of heatmaps for effective testing strategies.
Participants will gain insights into the responsibilities, challenges, and best practices associated with test management in SAP projects. Additionally, the webinar delves into the significance of heatmaps as a visual aid for identifying testing priorities, areas of risk, and resource allocation within SAP landscapes. Through this session, attendees can expect to enhance their understanding of test management principles while learning practical approaches to optimize testing processes in SAP environments using heatmap visualization techniques
What will you get from this session?
1. Insights into SAP testing best practices
2. Heatmap utilization for testing
3. Optimization of testing processes
4. Demo
Topics covered:
Execution from the test manager
Orchestrator execution result
Defect reporting
SAP heatmap example with demo
Speaker:
Deepak Rai, Automation Practice Lead, Boundaryless Group and UiPath MVP
Monitoring Java Application Security with JDK Tools and JFR Events
Temperature Cycling and Fatigue in Electronics
1. Temperature Cycling and Fatigue in Electronics
Cheryl Tulkoff, ASQ CRE
DfR Solutions
Senior Member of the Technical Staff
ctulkoff@dfrsolutions.com
SMTAI 2014
Rosemont, Il
1
2. Abstract
The majority of electronic failures occur due to thermally induced stresses and strains caused by excessive differences in coefficients of thermal expansion (CTE) across materials.
CTE mismatches occur in both 1st and 2nd level interconnects in electronics assemblies.
1st level interconnects connect the die to a substrate.
This substrate can be underfilled so there are both global and local CTE mismatches to consider.
2nd level interconnects connect the substrate, or package, to the printed circuit board (PCB). This would be considered a “board level” CTE mismatch.
Several stress and strain mitigation techniques exist including the use of conformal coating.
The purpose of this presentation is to show that accelerated testing can be successfully used to predict solder joint and plated through hole (PTH) fatigue behavior.
2
3. Describes the potential for product failure when subjected to periodic changes in environmental stress or an overstress event that are thermal or mechanical in nature
What types of thermal or mechanical stress could cause failure in today’s electronics?
Focus in this presentation is temperature cycling
Thermo/Mechanical Reliability
3
4. Due to Solar Loading
Temperature Cycling
Due to Power Dissipation
4
5. Failures are not always about electrical overstress (EOS)!
Recent studies suggest that the majority of electronic failures are thermo-mechanically related*
Why Care About Temperature Cycling?
*Wunderle, B. and B. Michel, “Progress in Reliability Research in Micro and Nano Region”, Microelectronics and Reliability, V46, Issue 9-11, 2006.
5
6. Why Care About Temperature Cycling?
Everything is Hot
Everything is Mobile
Everything is Everywhere
M2M Technology
6
7. Use many different materials
Semiconductors, Ceramics, Metals, Polymers
Bond these different materials together
Plating, Solder, Adhesive
Materials expand/contract at different rates
Why Do Electronics Fail Under Temperature Cycling?
7
8. Why do Solder Joints Fail under Temperature Cycling?
Two different expansion/contraction behaviors
Because solder is connecting two materials that are expanding / contracting at different rates (GLOBAL)
Because solder is expanding / contracting at a different rate than the material to which it is connected (LOCAL)
8
9. Differential expansion and contraction introduces stress into the solder joint
Stress causes the solder to deform (aka, elastic and plastic strain)
Extent of this strain (that is, strain range or strain energy) tells us the lifetime of the solder joint
Higher the strain, the more the solder joint is damaged, the shorter the lifetime
Why do Solder Joints Fail under Temperature Cycling? (cont.)
9
10. Knowing the critical drivers for solder joint fatigue allows development of predictive models and design rules
Drivers for Solder Joint Thermo- Mechanical Failures
CTE of Board
Elastic Modulus (Compliance) of Board
CTE of Component Elastic Modulus (Compliance) of Component Length of Component
Volume of Solder
Thickness of Solder
Solder Fatigue Properties
10
12. Typical Field Conditions
Field Conditions for Various Industries
IPC-SM-785, Guidelines for Accelerated Reliability Testing of Surface Mount Solder Attachments
12
13. JESD47G Conditions Used in Accelerated Tests
13
Stress-Test-Driven Qualification of Integrated Circuits, Nonhermetic package temperature cycling requirements
14. Mfg Provided Laminate Properties
Weave Illustration showing X and Y Fiber Orientation in FR-4
Isola 370HR Laminate and Prepreg Datasheet, http://www.isola- group.com/wp-content/uploads/2014/04/370HR-Laminate-and-Prepreg-Data- Sheet-Isola.pdf
14
15. Out-of-plane CTE (CTEz) is almost always provided on the laminate datasheet
Sometimes in ppm/C above and below the Tg
Sometimes in % between 50-260C
Out-of-plane modulus (Ez) is almost never provided on the laminate datasheet
Requires calculation based on in-plane laminate properties, glass fiber properties, glass fiber volume fraction, and Rule-of-Mixtures / Halpin-Tsai models
Laminate Datasheets
1/Elaminate = Vepoxy/Eepoxy + Vfiber/Efiber
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18. Solder Fatigue Crack Formation
Grains grow as the solder joint is stressed
Growing grains cause micro-voids to appear at the grain boundaries
Micro-voids connect with each other to create micro-cracks and eventually macro-cracks
Solder joints in Electronics: Design for Reliability, Werner Engelmaier
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19. Knowing the drivers and how to predict provides powerful insight to the design process
Identify which designs and environments are at potential risk of solder joint fatigue
Quantitatively benchmark material changes
Develop accurate accelerated life tests
Thermo-Mechanical Design Rules
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20. Predictive Models – Physics of
Failure (PoF)
Modified Engelmaier for Pb-free Solder (SAC305)
Semi-empirical analytical approach
Energy based fatigue
Determine the strain range (Dg)
C is a correction factor that is a function of dwell time
and temperature, LD is diagonal distance, a is
coefficient of thermal expansion (CTE), DT is
temperature cycle, h is solder joint height
T
h
L
C
s
D Dg DaD
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21. Predictive Models – Physics of
Failure (PoF)(cont.)
Determine the shear force applied to the solder joint
F is shear force, L is length, E is elastic modulus, A is
the area, h is thickness, G is shear modulus, and a is edge
length of bond pad
Subscripts: 1 is component, 2 is board, s is solder joint, c
is bond pad, and b is board
Takes into consideration foundation stiffness and
both shear and axial loads
D
A G G a
h
A G
h
E A
L
E A
L
T L F
c c b
c
s s
s
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2
1 1 2 2
2 1
a a
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22. Predictive Models – Physics of
Failure (PoF)(cont.)
Determine the strain energy dissipated by the
solder joint
Calculate cycles-to-failure (N50), using energy
based fatigue models
1 0.0019 N DW f
s A
F
DW 0.5Dg
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25. 25
Thermal Cycling: SnPb vs. SAC
Where does SnPb outperform Pb-free?
Leadless, ceramic components
Leadless ceramic chip carriers (crystals, oscillators, resistor networks, etc.)
SMT resistors
Ceramic BGAs
Severe temperature cycles
-40 to 125ºC
-55 to 125ºC
Syed, Amkor
“Overview of Reliability Models and Data Needs,” Ahmer Syed, Amkor Technology
26. Time to 1% Failure for 2512 Resistors Attached with SAC and SnPb Solder
Time to 1% Failure for TSOPs attached with SAC and SnPb with Long Dwells (8 hours)
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•At small changes in temperature, SnPb fails first but performs better at higher temperature changes
•Longer dwell times allow more stress relaxation of solder and are thought to cause more damage as a result
•Longer dwell times at higher temperatures also cause more damage than long dwell times at low temperatures
27. The dominant failure mode in PTH tends to be barrel fatigue
Barrel fatigue is the circumferential cracking of the copper plating that forms the PTH wall
Driven by differential expansion between the copper plating (~17 ppm) and the out-of-plane CTE of the printed board (~70 ppm)
How do PTH’s Fail?
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28. Historically, two material properties of concern
Out-of-plane coefficient of thermal expansion (CTEz)
Out-of-plane elastic modulus (‘stiffness’)(Ez)
Key Assumption: No exposure to temperatures above the glass transition temperature (Tg)
The two material properties (CTE and E) are driven by choices in resin, glass style, and filler
PCB Materials and PTH Reliability
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29. Round Robin Reliability Evaluation of Small Diameter (<20 mil) Plated Through Holes in PWBs
Activity initiated by IPC and published in 1988
Objectives
Confirm sufficient reliability
Benchmark different test procedures
Evaluate influence of PTH design and plating (develop a model)
IPC TR-579
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30. IPC TR-579 (cont.)
Determine stress applied (σ)
Assumes perfectly elastic deformation when below yield strength (Sy)
Linear stress-strain relationship above Sy
h
PTV Height
d
PTV Diameter
t
Plating Thickness
E
Elastic Modululs
a
Coefficient of Thermal Expansion
T
Temperature (oC)
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35. Majority of failures in electronics are caused by thermo-mechanical loads
Solder fatigue is the major failure mechanism
CTE mismatch between the board, component and attach materials creates stresses in the solder and the plating material
Experimental data for solder fatigue predictions and basic models can be used to predict solder fatigue for surface mount components
Conclusions
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35
36. PCB designers can change component placement and board laminate material to alleviate fatigue since component level design changes are usually not an option
PCB design also affects PTH reliability.
PCB designer influences PTH reliability by modifying drill diameters, laminate material, and plating parameters.
Solder and PTH fatigue are just two of the many effects of thermo-mechanical loads but they can be predicted and prevented
Conclusions
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37. Presenter Biography
Cheryl has over 20 years of experience in electronics manufacturing focusing on failure analysis and reliability. She is passionate about applying her unique background to enable her clients to maximize and accelerate product design and development while saving time, managing resources, and improving customer satisfaction.
Throughout her career, Cheryl has had extensive training experience and is a published author and a senior member of both ASQ and IEEE. She views teaching as a two-way process that enables her to impart her knowledge on to others as well as reinforce her own understanding and ability to explain complex concepts through student interaction. A passionate advocate of continued learning, Cheryl has taught electronics workshops that introduced her to numerous fascinating companies, people, and cultures.
Cheryl has served as chairman of the IEEE Central Texas Women in Engineering and IEEE Accelerated Stress Testing and Reliability sections and is an ASQ Certified Reliability Engineer, an SMTA Speaker of Distinction and serves on ASQ, IPC and iNEMI committees.
Cheryl earned her Bachelor of Mechanical Engineering degree from Georgia Tech and is currently a student in the UT Austin Masters of Science in Technology Commercialization (MSTC) program. She was drawn to the MSTC program as an avenue that will allow her to acquire relevant and current business skills which, combined with her technical background, will serve as a springboard enabling her clients to succeed in introducing reliable, blockbuster products tailored to the best market segment.
In her free time, Cheryl loves to run! She’s had the good fortune to run everything from 5k’s to 100 milers including the Boston Marathon, the Tahoe Triple (three marathons in 3 days) and the nonstop Rocky Raccoon 100 miler. She also enjoys travel and has visited 46 US states and over 20 countries around the world. Cheryl combines these two passions in what she calls “running tourism” which lets her quickly get her bearings and see the sights in new places.
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