This document discusses synchronous and asynchronous circuits. Synchronous circuits use a global clock signal to coordinate timing, but this limits speed and wastes power. Asynchronous circuits coordinate activity through local handshaking signals instead of a clock. They can run at each component's natural speed without wasted idle time. Asynchronous circuits have advantages like higher speed, lower power usage, and less electromagnetic interference compared to synchronous circuits. However, asynchronous design is more complex and lacks mature design tools.

1. BY: Saumya Ranjan Behura

2. Talk Flow:
Introduction.
Concept of clock.
Working of synchronous circuits.
Problem of synchronous circuits.
Concept of clockless chip.
Working of asynchronous circuit.
Advantages of clockless design.
Applications.
Challenges.
Conclusion.
References. 2

3. Concept of clock
CLOCK:
Tiny crystal oscillator.
Sets basic rhythm used throughout the machine.
ADVANTAGES:
 Signals the device of the chip when to i/p or o/p.
This functionality makes designing of synchronous chip easier.
3

4. Adapted : http://www.cs.columbia.edu/async/misc/technologyreview_oct_01_2001.html
4

5. continued…
This circuit looks for a particular signal(leading edge)
of the clock.
All actions takes place only at this part of clock cycle.
When transferring data to registers the computation
settles down and wait till the next leading edge
Designer’ challenge: to complete one operation
before next clock tick.
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6. Problems of synchronous circuit
Speed
 chip can only work as fast as its slowest component.
 leads to wasting of computation time.
 to traverse the chip’s longest wire in one clock cycle.
 so one alternate solution: Second clock incur
overhead and power consumption.
6

7. continued…
Power consumption
Consume more power than any other component.
Not associated with direct computation.
If no. of transistors more power consumption more.
EMI(Electro Magnetic Interference)
It is more in synchronous elements.
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8. 8

9. Concept of Clockless chip
Clockless chip/asynchronous/self timed/event driven.
Do not have a global clock.
Rely upon handshaking signals , hand-off signals and
sometimes a local clock to synchronize all actions.
Draw power only when there is useful work to do.
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10. Continued…
Chip can run at the average speed of all components.
Different part work at different speeds.
Hand-off the result immediately.
Very low Electro Magnetic Noise.
10

11. Adapted : http://www.cs.columbia.edu/async/misc/technologyreview_oct_01_2001.html
11

12. Continued…
GENERAL MODEL OF ASYNCHRONOUS DESIGN:
Adapted:David Geer,”Is it time for clockless chips?,”IEEE paper,pp.18-21,March 2005 12

13. Continued…
TYPES OF IMPLEMENTATION:
BOUNDED DELAY METHOD
similar to synchronous design
DELAY INSENSITIVE METHOD
opposite of bounded delay method
NULL CONVENTIONAL LOGIC(NCL)
it uses a NULL state when data is in reset
phase,
as opposed to data in set phase. 13

14. Continued…
BOUNDED DELAY METHOD:
Simplest implementation of asynchronous design.
Assumption: we know the largest amount of time for
each component to perform its task.
Very similar to synchronous design.
Prototype delay is introduced here.
14

15. Adapted:David Geer,”Is it time for clockless chips?,”IEEE paper,pp.18-21,March 2005 15

16. Continued…
DELAY INSENSITIVE METHOD:
Does not assume any
bound on time.
One method of this
type is : Dual-rail
method.
16
XH=O XL=O Data not
ready
XH=O XL=I Logical O
XH=I XL=O Logical I
XH=I XL=I Not used

17. Adapted:David Geer,”Is it time for clockless chips?,”IEEE paper,pp.18-21,March 2005 17
BLBL

18. Continued…
NULL CONVENTIONAL LOGIC:
NCL integrates data transformation and control into
a single expression.
It gives solutions for power , noise and system
integration issue.
NCL uses threshold gates with hysteresis.
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19. Continued…
NCL:
Adapted:David Geer,”Is it time for clockless chips?,”IEEE paper,pp.18-21,March 2005 19

20. Advantages of clockless design:
Increase in speed
Reduced power consumption
Less Electro Magnetic Noise
Flexible design
Provide superior encryption
20

21. Adapted: Ivan E Sutherland and J Ebergen,”Computers without clocks,”2nd
edition,p.405,2000. 21

22. Applications:
In the lab.
In mobile electronics.
In personal computers.
In encryption devices.
22

23. Adapted : http://www.cs.columbia.edu/async/misc/technologyreview_oct_01_2001.html
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24. Challenges
Design difficulties.
Lack of good tools.
Engineers are not trained in these fields.
Academically, no courses available.
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25. Conclusion:
Clocks are getting faster , while chips are getting
bigger, both of which make clock distribution harder.
There are also various other problems associated with
it. So we could only get out of it , if more focus ,
especially at the university level is given to the
asynchronous design. It is certainly a challenge , but
as software community is moving towards
concurrency, hardware community must move to
incorporate asynchronous logic.
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26. References:
David Geer , “ Is it time for clockless chips? , ” IEEE paper, pp. 18-
20,March 2005.
Tadao Murata ,et al, “Petri nets:properties ,analysis and applications,”
IEEE Proceedings, Vol. 77, No. 4, April 1989.
Robert L. Boylestad and Louis Nashelsky ,“Electronic Devices and
Circuit Theory ,” 6th
edition , pp. 798-801 ,1997.
Ivan E Sutherland and Jo Ebergen ,“ Computers without clocks,” 2nd
edition ,p. 405 ,2000.
http://www.cs.columbia.edu/async/technologyreview_oct_01_2001.ht
ml.
http://www.eetimes.com/story/OEG20030606S0033 26

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QUERIES??