The document discusses asynchronous chips, which operate without a central clock. It notes problems with synchronous chips like speed limitations and wasted energy from distributing a global clock. Asynchronous chips can operate at different speeds in different parts and exchange data using handshake signals only when needed. While asynchronous chips could reduce power consumption and noise, challenges remain in interfacing them with synchronous devices and a lack of expertise and tools for asynchronous design. The conclusion states that clocks will face difficulties in future complex chip designs due to noise, power and costs, making asynchronous approaches more appealing.

1. Seminar
On
Asynchronous Chips
Presented By – RitikKumar

2. CONTENTS
INTRODUCTION
PROBLEMS WITH SYNCHRONOUS
Approach ASYNCHRONOUS LOGIC
HOW DO THEYWORK?
SOME FEATURES
A CHALLENGING TIME
CONCLUSION
REFERENCES

3. INTRODUCTION
Computer chips of today are synchronous.
They contain a main clock, which controls the timing of
the entire chips.
There are problems, however, involved with these
clocked designs that are common today.
One problem is speed. A chip can only work as fast asits
slowest component.

4. Problems with Synchronous Approach
Distributing the clock globally.
Wastage of energy.
Traverse the chip’s longest wires in one clock cycle.
Order of arrival of the signals is unimportant.
Clocks themselves consume lot of energy (~30%).

5. Asynchronous logic circuits
Colckless chips/Asynchronous/self-timed circuits.
Functions away from the clock.
Different parts work at different speeds.
Hand-off the result immediately.

6. Clock time cycle vs. clockless time cycle

8. RENDEZVOUS CIRCUITS

9. How do they work?
No pure asynchronous chips are available.
Uses handshake signals for the data exchange.
Data moves only when required, not always.
◦ Minimizes power consumption.
◦ Less EMI  less noise  more applications.
◦ Stream data applications.

10. Some features
Integrated pipelining mode.
◦ Domino logic.
◦ Delay – insensitive.
Two different implementation details
◦ Dual rail.
◦ Bundled data.

11. Challenges
Interfacing between synchronous and
asynchronous
◦ Many devices available now are synchronous in
nature.
◦ Special circuits are needed to align them.
Lack of expertise.
Lack of tools.
Engineers are not trained in these fields.
Academically, no courses available.

12. CONCLUSION
Clocks haveserved the electronics design
industry very well for along time,but
there are insignificant difficulties looming
for clocked design in future.These
difficulties are most obvious in complex
SOC development, where electricalnoise,
power and design costs threaten to
render the potential of future process
technologies inaccessible to clocked
design.

13. REFERNCES
www.google.com
www.wikipedia.com

14. Thanks