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CLOCKLESS CHIP BY Saurabh singh PART 2
1. A SEMINAR REPORT ON
CLOCKLESS CHIP
SUBMITTED IN PARTIAL FULLFILMENT FOR
AWARD OF THE DEGREE OF
BACHELOR OF TECHNOLOGY
IN
ELECTRONICS AND COMMUNICATION ENGINEERING
SUBMITTED BY:-
SAURABH SINGH
EC III B
Roll no: 1016431096
DEPARTMENT OF ELECTRONICS COMMUNICATION ENGINEERING
PRANVEER SINGH INSTITUTE OF TECHNOLOGY
KANPUR-208020
2. Abstract
Every action of the computer takes place in tiny steps, each a billionth of a second long. A
simple transfer of data may take only one step; complex calculations may take many steps.
All operations, however, must begin and end according to the clock’s timing signals.
The use of a central clock also creates problems. As speed have increased, distributing the
timing signals has become more and more difficult. Present day transistors can process data
more quickly that they can accomplish several steps in the time that it takes a wire to carry a
signal from one side of the chip to the other.
Clock less chips are electronic chips that are not using clock for timing signal. They are
implemented in asynchronous circuits. An asynchronous circuit is a circuit in which the parts
are largely autonomous. They are not governed by a clock circuit or global clock signal, but
instead need only wait for the signals that indicate completion of instructions and operations.
These signals are specified by simple data transfer protocols. This digital logic design is
contrasted with a synchronous circuit which operates according to clock timing signals.
The term asynchronous logic is used to describe a variety of design styles, which use
different assumptions about circuit properties.
These vary from the bundled delay model - which uses 'conventional' data processing
elements with completion indicated by a locally generated delay model - to delay-insensitive
design - where arbitrary delays through circuit elements can be accommodated. The latter
style tends to yield circuits which are larger and slower than synchronous (or bundled data)
implementations, but which are insensitive to layout and parametric variations and are thus
"correct by design." Unlike a conventional processor, a clock less processor (asynchronous
CPU) has no central clock to coordinate the progress of data through the pipeline. Instead,
stages of the CPU are coordinated using logic devices called "pipeline controls" or "FIFO
sequencers." Basically, the pipeline controller clocks the next stage of logic when the existing
stage is complete. In this way, a central clock is unnecessary. It may actually be even easier
to implement high performance devices in asynchronous, as opposed to clocked logic.
[i]
3. Contents
1. Introduction 1-2
1.1 Definition 1
1.2 Clock Concept 1
2. Clockless approach 2-3
2.1 Clock Limitations 2
2.2 Asynchronous View 3
3. Problems with synchronous circuits 4-6
3.1 Performance 4
3.2 Speed 4
3.3 Power Dissipation 5
3.4 Electromagnetic Noise 6
4. Asynchronous circuits 6-7
4.1 Clockless Chips Implementation 6
4.2 Throwing Away Global Clock 6
4.3 Standardize of Components 7
5. How clockless chips works 7
6. Simplicity in design 7-11
6.1 Asynchronous for higher performance 10
6.2 Asynchronous for low power 10
6.3 Asynchronous for low noise 11
7. Applications of clockless chips 11-13
7.1 wearable computers 11
7.2 infrared communication receiver 12
7.3 in pagers 12
7.4 filter bank for digital hearing 12
8. Challenges 13
9. Conclusion 14
10. References 15
[ii]
![Abstract
Every action of the computer takes place in tiny steps, each a billionth of a second long. A
simple transfer of data may take only one step; complex calculations may take many steps.
All operations, however, must begin and end according to the clock’s timing signals.
The use of a central clock also creates problems. As speed have increased, distributing the
timing signals has become more and more difficult. Present day transistors can process data
more quickly that they can accomplish several steps in the time that it takes a wire to carry a
signal from one side of the chip to the other.
Clock less chips are electronic chips that are not using clock for timing signal. They are
implemented in asynchronous circuits. An asynchronous circuit is a circuit in which the parts
are largely autonomous. They are not governed by a clock circuit or global clock signal, but
instead need only wait for the signals that indicate completion of instructions and operations.
These signals are specified by simple data transfer protocols. This digital logic design is
contrasted with a synchronous circuit which operates according to clock timing signals.
The term asynchronous logic is used to describe a variety of design styles, which use
different assumptions about circuit properties.
These vary from the bundled delay model - which uses 'conventional' data processing
elements with completion indicated by a locally generated delay model - to delay-insensitive
design - where arbitrary delays through circuit elements can be accommodated. The latter
style tends to yield circuits which are larger and slower than synchronous (or bundled data)
implementations, but which are insensitive to layout and parametric variations and are thus
"correct by design." Unlike a conventional processor, a clock less processor (asynchronous
CPU) has no central clock to coordinate the progress of data through the pipeline. Instead,
stages of the CPU are coordinated using logic devices called "pipeline controls" or "FIFO
sequencers." Basically, the pipeline controller clocks the next stage of logic when the existing
stage is complete. In this way, a central clock is unnecessary. It may actually be even easier
to implement high performance devices in asynchronous, as opposed to clocked logic.
[i]](data:image/gif;base64,R0lGODlhAQABAIAAAAAAAP///yH5BAEAAAAALAAAAAABAAEAAAIBRAA7)