This document describes designing a two-phase non-overlapping clock generator circuit with buffered outputs. The circuit is required to generate clean square wave clock signals from a single-phase input clock between 10-100MHz. The output signals must drive a 0.33pF capacitive load without distortion. The design will be implemented using Cadence tools and modified through simulation to meet the objectives of generating true non-overlapping signals with at least 1ns of underlap that can operate over the specified frequency range and drive the required load.

1. TWO-PHASE NON OVERLAPPING CLOCK GENERATOR WITH BUFFERED OUTPUT
Chapter 1
INTRODUCTION
This mini project focuses on designing and analyzing a simple two phase non
overlapping low frequency clock generator with buffered output on both phases. A two-phase
clock offers a great deal of freedom in sequential circuit design if the clock period and the
duration of the signals ɸ1 and ɸ2 are correctly chosen. With two-phase clocking strategy, data
is allowed to become stable before and processing and there is no chance of race condition
occurring.
Clocked circuitry is considerably easier to design than the corresponding
asynchronous sequential circuitry. It does, however, usually pay the penalty of being slower.
It is necessary to recognize the fact that ɸ1 and ɸ2 need not be symmetrical always. For a
given clock period, each clock phase period and associated underlap period can be varied as
the application demands.
Along with its application is synchronizing circuits two-phase non overlapping clock
signals are used in dynamic pass transistor circuits to ensure that at any point of time only
one block of logic circuit is operational. This is also called as two-phase clocking circuit and
is one of the most widely used timing strategies.
Owing to wide popularity of two-phase clocking strategies several researchers have
proposed different techniques to generate non overlapping two-phase clock signals. Adding
to the same list, this mini project focuses on developing a simple two-phase non overlapping
clock generator that could meets the basic objectives of the clocking strategies.
The designed circuit is required to accept a single phase input clock signal of
minimum 10 MHz and a maximum of 100 MHz clock frequency. The output clock signals
are to be clean square waves and each should be capable of driving a capacitive load of 0.33
pF without undue waveform degradation. The approach taken is one of the circuit
developments through the design of schematic, simulation of circuit and necessary
modifications, improving the performance of the two-phase clock generator.
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2. TWO-PHASE NON OVERLAPPING CLOCK GENERATOR WITH BUFFERED OUTPUT
Objectives
1. Designing a circuit to generate true non overlapping two-phase clock signals with
under-lap of atleast 1ns.
2. Two-phase clock signal generator circuit should be capable of operating in the
frequency range of 10 MHz – 100 MHz.
3. Two-phase clock signal generator circuit should be capable of driving reasonable load
capacitance without undue distorted waveforms.
The schematic is created in Cadence Virtuoso Schematic editor and simulated using
the ADE-L simulation tool provided with the Cadence Virtuoso EDA tool package. Based on
the results obtained the basic circuit is modified to meet all the objectives and to give better
performance.
The rest of the report is organized as follows: Chapter 2, under the heading Literature
Survey gives the insight into the works done by other researchers in the same field. Chapter 3
explains about the Computer Aided Design tools used in Very Large Scale Integration
design. In Chapter 4, description of different concepts associated with this mini project is
explained. Chapter 5 describes how the design was implemented and improved. The
simulation results for all the versions of design are shown in the same section. Section 6
concludes the report.
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3. TWO-PHASE NON OVERLAPPING CLOCK GENERATOR WITH BUFFERED OUTPUT
Chapter 2
LITERATURE SURVEY
In electronics and especially synchronous digital circuits, clocks are defined as
pulsed, synchronizing signals that provide the time reference for the movement of data in the
synchronous digital system. A clock signal is produced by a clock generator. Although more
complex arrangements are used, the most common clock signal is in the form of a square
wave with a 50% duty cycle, usually with a fixed, constant frequency. Circuits using the
clock signal for synchronization may become active at either the rising edge, falling edge, or,
in the case of double data rate, both in the rising and in the falling edges of the clock cycle.
Most integrated circuits (ICs) of sufficient complexity use a clock signal in order to
synchronize different parts of the circuit, cycling at a rate less than the worst-case internal
propagation delays. In some cases, more than one clock cycle is required to perform a
predictable action. As ICs become more complex, the problem of supplying accurate and
synchronized clocks to all the circuits becomes increasingly difficult. The preeminent
example of such complex chips is the microprocessor, the central component of modern
computers, which relies on a clock from a crystal oscillator. The only exceptions are
asynchronous circuits such as asynchronous CPUs.
A clock signal might also be gated, that is, combined with a controlling signal that
enables or disables the clock signal for a certain part of a circuit. This technique is often used
to save power by effectively shutting down portions of a digital circuit when they are not in
use, but comes at a cost of increased complexity in timing analysis.
Based on the number of phases, clock signals could be divided as single-phase clock
and multi phase clock (two-phase clock or four-phase clock).
Single-phase clock: Most modern synchronous circuits use only a "single phase clock" -- in
other words, they transmit all clock signals on (effectively) 1 wire.
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4. TWO-PHASE NON OVERLAPPING CLOCK GENERATOR WITH BUFFERED OUTPUT
Two-phase clock: In synchronous circuits, a "two-phase clock" refers to clock signals
distributed on 2 wires, each with non-overlapping pulses. Traditionally one wire is called
"phase 1" or "phi1", the other wire carries the "phase 2" or "phi2" signal. Two-phase clock
finds itself a great importance in sequential circuits. Certain ICs requires two-phase clock
signals to be generated externally, whereas some ICs incorporated the two-phase clock
generation on chip so only a single phase clock input was required, simplifying system
design. The Difference in the phase angle between the two clock signals depends on the
particular application. In this project the circuit is designed to maintain a phase difference
between two clock signals is 180° as shown in fig 1.1.
Figure 1.1 Typical two-phase non overlapping clock signals with 180° phase shift.
Over the years researchers have proposed different circuits for the implementation of
two-phase clock non overlapping clock generator to operate under different frequencies and
capacitive load. Each circuit design has its own advantages and short comings. All the
circuits shown below are represented in their basic form (not improved to operate for
capacitive load) and are included only for indicative purpose.
1. Using Inverters:
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5. TWO-PHASE NON OVERLAPPING CLOCK GENERATOR WITH BUFFERED OUTPUT
2. Using AND gates and divide-by-two circuit:
&
&
ɸ
ɸ1
ɸ2
DIV2
1
3. Using NOR gates and inverters with feedback:
4. Using NOR gates and inverters with feedback and buffers:
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6. TWO-PHASE NON OVERLAPPING CLOCK GENERATOR WITH BUFFERED OUTPUT
5. Using NAND gates and inverters with feedback:
All the above mentioned above circuit designs (except (1) and (2)) share similarity with
Kevin Karplus’s circuit designs [1]. Several researchers have even proposed robust design
which incorporates adjustable duty cycle [2] and programmable two phase non overlapping
clock generators [3]. The amount of research work done on this particular topic clearly shows
the importance of two-phase clocking circuits. In this mini project the focus is laid on
designing a simple two-phase non overlapping circuit generating clock signals, which
performs reasonably well with relatively large capacitive load at frequencies up to 100MHz.
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7. TWO-PHASE NON OVERLAPPING CLOCK GENERATOR WITH BUFFERED OUTPUT
Chapter 3
CAD TOOLS FOR VLSI
2.1 VLSI Design
Design Flow: It provides a description of the ASIC design flow adopted and the tools used
during the process.
Cell Libraries: It provides necessary information regarding our cell libraries such as how to
receive and use our cell libraries.
CAD Tools: It provides necessary information to receive source for our CAD tools (two
automatic test pattern generators and two fault simulators) along with some benchmark
circuits.
Figure 2.1 Bottom-up design flow for a transistor-level circuit
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8. TWO-PHASE NON OVERLAPPING CLOCK GENERATOR WITH BUFFERED OUTPUT
The bottom-up design flow for a transistor-level circuit layout always starts with a set
of design specifications. The "specs" typically describe the expected functionality (Boolean
operations) of the designed block, as well as the maximum allowable delay times, the silicon
area and other properties such as power dissipation. Usually, the design specifications allow
considerable freedom to the circuit designer on issues concerning the choice of a specific
circuit topology, individual placement of the devices, the locations of input and output pins,
and the overall aspect ratio (width-to-height ratio) of the final design. Note that the
limitations spelled out in the initial design specs typically require certain design trade-offs,
such as increasing the dimensions of the transistors in order to reduce the delay times.
In a large-scale design, the initial design specifications may also evolve during the
design process to accommodate other specs or limitations. This implies that the designer(s)
of individual blocks or modules must communicate clearly and frequently about the spec
updates, in order to avoid later inconsistencies.
The traditional method for capturing (i.e. describing) transistor-level or gate-level
design is via the schematic editor. Schematic editors provide simple, intuitive means to draw,
to place and to connect individual components that make up the design. The resulting
schematic drawing must accurately describe the main electrical properties of all components
and their interconnections. Also included in the schematic are the power supply and ground
connections, as well as all "pins" for the input and output signals of the circuit. This
information is crucial for generating the corresponding netlist, which is used in later stages of
the design. The generation of a complete circuit schematic is therefore the first important step
of the transistor-level design flow. Usually, some properties of the components (e.g.
transistor dimensions) and/or the interconnections between the devices are subsequently
modified as a result of iterative optimization steps. These later modifications and
improvements on the circuit structure must also be accurately reflected in the most current
version of the corresponding schematic.
If a certain circuit design consists of smaller hierarchical components (or modules), it
is usually very beneficial to identify such modules early in the design process and to assign
each such module a corresponding symbol (or icon) to represent that circuit module. This
step largely simplifies the schematic representation of the overall system. The "symbol" view
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9. TWO-PHASE NON OVERLAPPING CLOCK GENERATOR WITH BUFFERED OUTPUT
of a circuit module is an icon that stands for the collection of all components within the
module.
Figure 2.2 Sample schematic editing
A symbol view of the circuit is also required for some of the subsequent simulation
steps, thus, the schematic capture of the circuit topology is usually followed by the creation
of a symbol to represent the entire circuit. The shape of the icon to be used for the symbol
may suggest the function of the module (e.g. logic gates - AND, OR, NAND, NOR), but the
default symbol icon is a simple rectangular box with input and output pins. Note that this
icon can now be used as the building block of another module, and so on, allowing the circuit
designer to create a system-level design consisting of multiple hierarchy levels.
After the transistor-level description of a circuit is completed using the Schematic
Editor, the electrical performance and the functionality of the circuit must be verified using a
Simulation tool. The detailed transistor-level simulation of the design will be the first indepth validation of its operation, hence, it is extremely important to complete this step before
proceeding with the subsequent design optimization steps. Based on simulation results, the
designer usually modifies some of the device properties (such as transistor width-to-length
ratio) in order to optimize the performance.
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10. TWO-PHASE NON OVERLAPPING CLOCK GENERATOR WITH BUFFERED OUTPUT
The creation of the mask layout is one of the most important steps in the full-custom
(bottom-up) design flow, where the designer describes the detailed geometries and the
relative positioning of each mask layer to be used in actual fabrication, using a Layout
Editor. Physical layout design is very tightly linked to overall circuit performance (area,
speed and power dissipation) since the physical structure determines the transconductances
of the transistors, the parasitic capacitances and resistances, and obviously, the silicon area
which is used to realize a certain function. On the other hand, the detailed mask layout of
logic gates requires a very intensive and time-consuming design effort.
Figure 2.3 Symbol
The physical (mask layout) design of CMOS logic gates is an iterative process which
starts with the circuit topology and the initial sizing of the transistors. It is extremely
important that the layout design must not violate any of the Layout Design Rules, in order to
ensure a high probability of defect-free fabrication of all features described in the mask
layout. The created mask layout must conform to a complex set of design rules, in order to
ensure a lower probability of fabrication defects. A tool built into the Layout Editor, called
Design Rule Checker, is used to detect any design rule violations during and after the mask
layout design. The detected errors are displayed on the layout editor window as error
markers, and the corresponding rule is also displayed in a separate window. The designer
must perform DRC (in a large design, DRC is usually performed frequently - before the
entire design is completed), and make sure that all layout errors are eventually removed from
the mask layout, before the final design is saved.
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11. TWO-PHASE NON OVERLAPPING CLOCK GENERATOR WITH BUFFERED OUTPUT
After the mask layout design of the circuit is completed, the design should be checked
against the schematic circuit description created earlier. The design called "Layout-versusSchematic (LVS) Check" will compare the original network with the one extracted from the
mask layout, and prove that the two networks are indeed equivalent. The LVS step provides
an additional level of confidence for the integrity of the design, and ensures that the mask
layout is a correct realization of the intended circuit topology
Figure 2.4 Sample layout
The electrical performance of a full-custom design can be best analyzed by
performing a post-layout simulation on the extracted circuit net-list. At this point, the
designer should have a complete mask layout of the intended circuit/system, and should have
passed the DRC and LVS steps with no violations. The detailed (transistor-level) simulation
performed using the extracted net-list will provide a clear assessment of the circuit speed, the
influence of circuit parasitics (such as parasitic capacitances and resistances), and any
glitches that may occur due to signal delay mismatches.
Finally, note that a satisfactory result in post-layout simulation is still no guarantee
for a completely successful product; the actual performance of the chip can only be verified
by testing the fabricated prototype. Even though the parasitic extraction step is used to
identify the realistic circuit conditions to a large degree from the actual mask layout, most of
the extraction routines and the simulation models used in modern design tools have
inevitable numerical limitations. This should always be one of the main design
considerations, from the very beginning.
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12. TWO-PHASE NON OVERLAPPING CLOCK GENERATOR WITH BUFFERED OUTPUT
Chapter 4
BASIC CONCEPTS
4.1 Two-Phase Clocking
A two-phase clock offers a great deal of freedom in sequential circuit design if the
clock period and the duration of the signals ɸ1 and ɸ2 are correctly chosen. If this is the case,
data is allowed to become stable before and further transfer takes place and there is no
chance of race condition occurring.
Clocked circuitry is considerably easier to design than to corresponding asynchronous
sequential circuitry. It does, however, usually pay the penalty of being slower. It is necessary
to recognize the fact that ɸ1 and ɸ2 need not be symmetrical always. For a given clock period,
each clock phase period and its associated underlap period can be varied if the need arises in
optimizing a design.
A very simple arrangement using combinational logic generating a two-phase clock at
the frequency of a single phase input clock is set out in fig 4.1. The input clock signal C is
used to provide a delayed version of it (CD) by passing through an even number of inverters.
The delay thus produced determines the underlap period for the two-phase clock. The phase
1 signal ɸ1 is generated by ANDing C with CD whilst the phase 2 ɸ2 is produced by NORing
C with CD. Clearly the minimum underlap period will be that generated by the delayed
through two inverters and this is also the increment by which the delay may be increased by
adding further inverter pairs.
C
ɸ1
CD
ɸ2
Figure 4.1 Simple two-phase clock generator circuit — basic form
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13. TWO-PHASE NON OVERLAPPING CLOCK GENERATOR WITH BUFFERED OUTPUT
Since clock lines often feed many stages and are associated with long bus lines, they
often present quite considerable capacitance to the clock line drivers. The circuit shown in fig
4.1 operates very well at low frequencies with limited fan-out and short bus lines. It also
offers very less under-lap, in other words the clock signals ɸ1 and ɸ2 overlap. Simple way out
of overlapping problem is addition of one more pair of inverters. These inverter buffers add
to the overall propagation delay providing sufficient under-lap required by the clock signals.
The circuit shown in fig 4.2 is the improved version of the basic form and performs
reasonably well under relatively high frequency and capacitive load.
ɸ
C
ɸ1
CD
ɸ2
Figure 4.2 Simple two-phase clock generator circuit — additional buffers
4.2 Driving Large capacitive loads
The problem of driving comparatively large capacitance arises when signals must be
propagated from the chip to off chip destinations. Generally, typical off chip capacitances
may be several orders higher than on chip □Cg values. For example, if the off chip load is
denoted by CL then
CL ≥ 104 □Cg
The capacitances which of this order must be driven through low resistances,
otherwise excessively long delays will occur. Large capacitance is presented at the input,
which in turn slows down the rate of change of voltage at input.
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14. TWO-PHASE NON OVERLAPPING CLOCK GENERATOR WITH BUFFERED OUTPUT
Similar condition arises when the fan-out of the device is more. The value of the
capacitive load increases. One of the best possible way to overcome such a problem of high
capacitive load is use of inverters as drivers.
4.3 Standard unit for capacitance □Cg
It is convenient to employ a standard unit of capacitance that can be given a value
appropriate to the technology but can also be used in calculations without associating it with
an absolute value. The unit is denoted □Cg and is defined the gate-to-channel capacitance of a
MOS transistor having W = L = feature size for lambda based design rules.
4.4 Cascaded Inverters as drivers
Inverters intended to drive large capacitive loads must be present low pull-up and pull
down resistance. Obviously, for MOS circuits low resistance values of Zpd and Zpu imply low
L:W ratio; in other words, channels must be made very wide to reduce resistance value and,
in consequence, an inverter to meet this need occupies large area. Moreover, because of the
large L: W ratio and since length L cannot be reduced below the minimum feature size, the
gate region area L×W becomes significant and a comparatively large capacitance is presented
at the input, which in turn slows down the rates of change of voltage can take place at the
input.
The remedy is to use N cascaded inverters each one of which is larger than the
preceding stage by a width factor of ‘f’ as shown in figure.
Figure 4.3 Driving large capacitive loads
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15. TWO-PHASE NON OVERLAPPING CLOCK GENERATOR WITH BUFFERED OUTPUT
Clearly as the width factor increases, so the capacitive load presented at the inverter
input increases and the area occupied increases also. Equally clearly, the rate at which width
increases will influence the number N of stages which must be cascaded to drive a particular
value of CL. Thus with large f, N decreases but delay per stage increases.
Delay per CMOS pair = 7fτ.
y = CL/□Cg = fN
Therefore the choice of f and N are interdependent.
Determine the value of f which will minimize the overall delay for a given value of y.
Apply logarithms on both side of the equation
ln(y) = N ln(f)
i.e.
N = ln(y)/ln(f)
For N even (CMOS)
Total delay = N/2 (7fτ)
= 3.5Nfτ
From above relations, we can write
Delay α Nfτ = [ln(y)/ln(f)] fτ
It can be shown that total delay is minimized if f assumes the value of e for CMOS inverters.
Assume f = e, we have
N = ln(y)/ln(e)
i.e. N = ln(y)
Overall delay td
td = 3.5 eNτ (CMOS)
N even:
N odd:
( for logical transition 0 to 1)
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td = [3.5(N-1)+2] eτ (CMOS)
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16. TWO-PHASE NON OVERLAPPING CLOCK GENERATOR WITH BUFFERED OUTPUT
(for logical transition 1 to 0)
td = [3.5(N-1) +5] eτ (CMOS)
4.5 Race conditions
In general, race condition refers to a situation in which the result depends upon the sequence
in which events happen. In particular, a race condition occurs when a system/device is
designed assuming a particular sequence of events without taking steps to ensure it. In logic
gates, it happens when the inputs arrive at the gate in a sequence not assumed while deriving
the function. This results, sometimes, in the anomalous behavior of the logic gate because of
the unexpected dependence on the sequence of arrival of inputs. Since, the function of the
logic gate is calculated assuming static inputs; the order of arrival may have impact on the
output. We can consider race condition as a situation in which two or more signals are racing
to have their effect on the output. This is how; race condition derives its name.
For a very simple example, consider the following logic function: Z = A˖A’
Figure 4.4 Circuit having race condition
Theoretically, the output will always be ‘0’. However, this is true only if the noninverted portion of the signal has greater delay in reaching the AND gate (we have
considered ‘0’ -> ‘1’ transition of the input signal ‘A’). As shown in the figure above, the
signal passing through inverter will have some delay of its own. If the signal through inverter
reaches the AND gate later than the one without inverter, there will be a glitch as shown in
the figure 2. For ‘1’ -> ‘0’ transition, the opposite will happen.
If the condition for race is violated, as shown in fig 4.5, the design may enter an
undefined state, the one which might not have been considered while designing. Hence, the
whole system will malfunction in such a scenario leading to failure. It might be the case that
some elements in the design enter metastable state, which can further cause problems. Hence,
it is very important to give proper consideration to race conditions.
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17. TWO-PHASE NON OVERLAPPING CLOCK GENERATOR WITH BUFFERED OUTPUT
Figure 4.5 Glitch caused at the output of AND gate due to inverted signal being delayed than
non-inverted signal
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18. TWO-PHASE NON OVERLAPPING CLOCK GENERATOR WITH BUFFERED OUTPUT
Chapter 5
IMPLEMENTATION AND RESULTS
5.1 Circuit Description
The circuit is required to accept a single phase input clock signal of 10 MHz
(minimum) – 100 MHz (maximum) frequency and, from this, generate two-phase non
overlapping clock signals at the same input clock frequency. The two-phase clock signals are
to be good, clean ‘square’ waves, and each phase should be capable of driving a load
capacitance of 0.33 pF without undue waveform degradation. The approach taken is one of
the circuit developments through the design schematic, simulation of performance,
improvement where necessary, modified schematic, simulation of modified schematic, and
so on.
5.2 Design Process
Version 1:
In order to achieve the waveform requirements, first the complete the schematic for
the basic arrangement without output buffers was created in virtuoso schematic editor. All
the transistors were taken from the GPDK 180 nm technology library. The symbol for the
schematic is created. In a new schematic window the symbol is placed along with the voltage
source and input clock pulse. The symbol is simulated using ADE-L before proceeding
further. The circuit realized is shown in fig 5.1 and is a straight forward translation of the
logic diagram shown in fig 4.1. Circuit realized to test the symbol of the two-phase clock is
shown in the fig 5.2.
The circuit is tested for different input clock frequency: 10 MHz, 12.5 MHz, 25 MHz,
50 MHz and 100 MHz. The need to uses different input clock frequency is to show the
response of the circuit at different frequencies. Table 5.1 shows the W : L ratio of all the
transistors. In version 1 design all the transistors (both p-type and n-type) have a uniform W :
L ratio of 1 : 1.
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19. TWO-PHASE NON OVERLAPPING CLOCK GENERATOR WITH BUFFERED OUTPUT
Table 5.1 W : L ratio of transistors for version 1 Two-phase clock generator
Transistors
T1
T2
T3
T4
T5
T6
T7
T8
T9
T10 T11
T12 T13 T14
W:L ratio
1:1
1:1
1:1
1:1
1:1
1:1
1:1
1:1
1:1
1:1
1:1 1:1 1:1
1:1
The simulated transient analysis output waveforms for 10 MHz and 100 MHz input
clock frequency are shown in fig 5.3 and fig 5.4 respectively. As expected the circuit
performs very well for the lower end frequencies. As the input clock frequency is increased
the output phase signals start to degrade.
Schematic Diagram
T5
T11
T13
T1
T6
T10
T3
T7
T9
T14
T13
T2
T4
T8
Fig 5.1 Schematic Diagram of Version 1 Two-phase clock generator
Fig 5.2 Test symbol circuit of Version 1 Two-phase clock generator
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20. TWO-PHASE NON OVERLAPPING CLOCK GENERATOR WITH BUFFERED OUTPUT
Table 5.2 Values of different parameters
Instance
Parameters
Vdc
Vin = 1.8 V
Vpulse
V1 = 0 V
V2 = 1.8 V
Rise time = 1 ps
Fall time = 1ps
The total period and pulse period was varied according to frequency under test
For 100 MHz test simulation:
Total Period = 10 ns
Pulse Period = 5 ns
Simulation Results:
Fig 5.3 Transient response of Version 1 Two-phase clock generator (12.5 MHz Input
clock)
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21. TWO-PHASE NON OVERLAPPING CLOCK GENERATOR WITH BUFFERED OUTPUT
Fig 5.4 Transient response of Version 1 Two-phase clock generator (100 MHz Input
clock)
Result analysis of version 1 circuit:
1. The amount of underlap between phase 1 (ɸ1) and phase 2 (ɸ2) waveforms is barely
adequate.
2. Phase 1 (ɸ1) output rises faster than the phase 2 (ɸ2) owing to the time required for
the NOR gate output to rise.
3. The square waves produced at each output are not particularly good at higher
frequencies (50 MHz and100 MHz).
Version 2
Clearly, all the performance shortcomings of version 1 could be improved by
1. Increasing the delay presently introduced by the two inverters in series.
2. Reducing the output resistance of the final delay generating inverter so that the gate
capacitance of the NOR gate will be charged faster, and also reducing the output
resistance by widening the channels of the two p-type pullup transistors of the NOR
gate.
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22. TWO-PHASE NON OVERLAPPING CLOCK GENERATOR WITH BUFFERED OUTPUT
All the above points have been taken into account in version 2, noting that (1) the delayed
clock waveform is now generated by dour inverters in series and (2) that the driving
capability has been improved by progressively decreasing the L:W ratio for the transistor
channel in the inverter.
The circuit implementation now appears as fig 4.2, the revised schematic diagram
looks as shown in fig 5.5 and the corresponding simulation results as fig 5.6 and fig 5.7.
Schematic Diagram
T15
T16
T17
T18
Fig 5.5 Schematic Diagram of Version 2 Two-phase clock generator
Table 5.3 W : L ratio of transistors for Version 2 Two-phase clock generator
Transistors
T1
T2
T3
T4
T5
T6
T7
T8
T9
T10
W:L ratio
1:1
1:1
1:2
1:2
1:1
1:1
1:1
1:1
1:1
1:1
Transistors
T11
T12
T13
T14
T15
T16
T17
T18
W:L ratio
1:2
1:2
1:1
1:1
1:3
1:3
1:4
1:4
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23. TWO-PHASE NON OVERLAPPING CLOCK GENERATOR WITH BUFFERED OUTPUT
Fig 5.6 Transient response of Version 2 Two-phase clock generator (12.5 MHz Input
clock)
Fig 5.7 Transient response of Version 2 Two-phase clock generator (100 MHz Input
clock)
Dept of ECE, S.D.M.C.E.T, Dharwad
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24. TWO-PHASE NON OVERLAPPING CLOCK GENERATOR WITH BUFFERED OUTPUT
Version 3:
Waveforms and delay are now predicted to be within acceptable limits and it now
remains to add the output buffer at each output. An acceptable approach is to cascade
inverters of increasing channel width. The number of cascaded stages is given by N = ln(y).
Thus in this case for 0.33 pF:
y = CL/□Cg
□Cg = 20000 aF/µm2 = 0.02 pF/µm2
i.e y = (0.33/0.02)
= 16.5
Therefore, N= ln(16.5)
= 2.80 ≈ 3
Thus, we need 3 inverters in series, each one being 2.7 times (say 2.5) its
predecessor’s width. Noting the existing output inverter for phase 1, we need two additional
buffer inverter stages to provide the phase 1 output. Three will be needed for phase 2 but a
fourth is added to maintain the original phase relationship. The circuit is shown in fig 5.8.
Table 5.4 W : L ratio of transistors for version 3 Two-phase clock generator
Transistors T1
W:L ratio
T2
T3
T4
T5
T6
T7
T8
T9
T10
1:1 1:1 1:2 1:2 1:1 1:1 1:1 1:1 1:1 1:1
Transistors T11 T12 T13 T14 T15 T16 T17 T18 T19
W:L ratio
1:2 1:2 1:1 1:1 1:3 1:3 1:4 1:4 1:2.5 1:2.5
Transistors T21
W:L ratio
T20
T22
T23 T24 T25
T26
T27
T28
T29
T30
1:6.5 1:6.5 1:1 1:1 1:2.5 1:2.5 1:6.5 1:6.5 1:6.5 1:6.5
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25. TWO-PHASE NON OVERLAPPING CLOCK GENERATOR WITH BUFFERED OUTPUT
Schematic Diagram
T29
T27
T25
T23
T19
T21
T22
T30
T28
T26
T24
T20
Fig 5.8 Schematic Diagram of Version 3 Two-phase clock generator
Fig 5.9 Test symbol circuit of Version 3 Two-phase clock generator
The version 3 of the two-phase non overlapping clock generator schematic is first simulated
on no external capacitive load. The waveforms generated at 10 MHz clock frequency were
recorded. Near ideal non overlapping square waves were observed with 1ns under-lap as
shown in fig 5.10. In order to assess the effect of increasing this maximum operating
frequency, the input clock rate was increased till 100 MHz input clock and resulting
waveforms were observed as in fig 5.11. It will be seen that the performance of the circuit is
still excellent with proper non overlapping phases. Finally the outputs were loaded with load
capacitance CL and resulting waveforms were observed as in fig 5.12.
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26. TWO-PHASE NON OVERLAPPING CLOCK GENERATOR WITH BUFFERED OUTPUT
Fig 5.10 Transient response of Version 3 Two-phase clock generator with no load
capacitor (12.5 MHz Input clock)
Fig 5.11 Transient response of Version 3 Two-phase clock generator with no load
capacitor (100 MHz Input clock)
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27. TWO-PHASE NON OVERLAPPING CLOCK GENERATOR WITH BUFFERED OUTPUT
Fig 5.11 Transient response of Version 3 Two-phase clock generator with 0.33 pF load
capacitor (10 MHz Input clock)
Fig 5.11 Transient response of Version 3 Two-phase clock generator with 0.33 pF load
capacitor (100 MHz Input clock)
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28. TWO-PHASE NON OVERLAPPING CLOCK GENERATOR WITH BUFFERED OUTPUT
Chapter 6
CONCLUSION
The two-phase non-overlapping clock generator with reasonably good performance
over a wide frequency range and different load capacitance is designed. GPDK 180nm
technology library was used in designing the schematic of the two-phase non-overlapping
clock generator in the Cadence Virtuoso schematic editor environment. All the objectives
were successfully covered by the version 3 of the design. The design generates true non
overlapping two-phase clock signals with adequate under-lap. Circuit operates reasonably
well over the frequency range 10 MHz – 100 MHz. The circuit is capable of driving
reasonable load capacitance without undue distorted waveforms, which was one of the major
concerns while taking up this mini project in the first place. The circuit is simulated with
different input conditions to demonstrate the robustness of the circuit. It was a great
experience working in the cadence environment and getting familiarized with the industry
standard CAD tool.
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29. TWO-PHASE NON OVERLAPPING CLOCK GENERATOR WITH BUFFERED OUTPUT
REFERENCES
[1] “A programmable clock oscillator for integrated sensor applications”, Electron Devices
Meeting, 1998. Proceedings. 1998 IEEE Hong Kong.
[2] Magnus Karlsso, Mark Vesterbacka and Wlodek Kulesza, “A non-overlapping two-phase
clock generator With adjustable duty cycle”
[3] R. Długosz, K. Iniewski, T. Talaśka3, “0.35 μm 22μW Multiphase Programmable Clock
Generator for Circular Memory SC FIR Filter For Wireless Sensor Applications”,
Published in IEEE Workshop on Signal Processing Systems (SIPS) IM3, M3-5, 157-160,
2006.
[4] Douglas A. Pucknell and Kamran Eshraghian , “Basic Vlsi Design”, Third edition, PHI
Private Limited, 1994.
[5] Rajalaxmi Das, Ghanshyam Kumar Singh & Ram Mohan Mehra, “Two-Phase Clocking
Scheme for Low-Power and High-Speed VLSI”, International Journal of Advances in
Engineering & Technology, Volume 2, issue 1, 2011
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