The document outlines the process of ASIC physical design and placement, particularly focusing on techniques for optimizing placement for timing and congestion. Key topics include timing-driven placement, congestion-driven placement, high fanout synthesis, and scan chain optimization, emphasizing the importance of circuit placement in modern technology nodes (65nm and below). Strategies to minimize routing congestion and ensure legal cell placement are discussed to meet timing and area constraints.

1. Intro TDP Congestion HFNS Scan Chain Optimization
Placement
How to Plan your own chip
Ahmed Abdelazeem
Faculty of Engineering
Zagazig University
RTL2GDSII Flow, February 2022
Ahmed Abdelazeem ASIC Physical Design

2. Intro TDP Congestion HFNS Scan Chain Optimization
Table of Contents
1 Introduction
2 Timing Driven Placement
3 Congestion Driven Placement
4 High Fanout Synthesis (HFS)
5 Scan Chain Reordering
6 Placement Optimization
Ahmed Abdelazeem ASIC Physical Design

3. Intro TDP Congestion HFNS Scan Chain Optimization Place Flow
Table of Contents
1 Introduction
2 Timing Driven Placement
3 Congestion Driven Placement
4 High Fanout Synthesis (HFS)
5 Scan Chain Reordering
6 Placement Optimization
Ahmed Abdelazeem ASIC Physical Design

4. Intro TDP Congestion HFNS Scan Chain Optimization Place Flow
Design Status Prior to Placement
Design Planning is completed
Second-Pass Synthesis is completed
Second-Pass Data Setup is completed
“Floorplanned cell” is generated- ready for placement
1 Core and periphery areas defined
2 Macros are placed and “fixed”
3 Placement blockages defined
4 Power grid pre-routed
5 Standard cell placement is discarded
Ahmed Abdelazeem ASIC Physical Design

5. Intro TDP Congestion HFNS Scan Chain Optimization Place Flow
Placement Problem
The goal of placement is to minimize the total area and
interconnect cost.
The quality of the attainable routing is
highly determined by the placement.
Circuit placement becomes very critical in
65nm and below technologies.
Ahmed Abdelazeem ASIC Physical Design

6. Intro TDP Congestion HFNS Scan Chain Optimization Place Flow
Placement
Placement is the stage of the design flow, during which each
standard cell is given an exact location
Ahmed Abdelazeem ASIC Physical Design

7. Intro TDP Congestion HFNS Scan Chain Optimization Place Flow
Placement
Placement is the stage of the design flow, during which each
standard cell is given an exact location
Placement does not just place the standard cell available in
the synthesized netlist, it also optimized the design.
Ahmed Abdelazeem ASIC Physical Design

8. Intro TDP Congestion HFNS Scan Chain Optimization Place Flow
Placement
Placement is the stage of the design flow, during which each
standard cell is given an exact location
Placement does not just place the standard cell available in
the synthesized netlist, it also optimized the design.
Inputs:
Ahmed Abdelazeem ASIC Physical Design

9. Intro TDP Congestion HFNS Scan Chain Optimization Place Flow
Placement
Placement is the stage of the design flow, during which each
standard cell is given an exact location
Placement does not just place the standard cell available in
the synthesized netlist, it also optimized the design.
Inputs:
1 Netlist of gates and wires.
2 Floorplan and Technology constraints
Outputs:
Ahmed Abdelazeem ASIC Physical Design

10. Intro TDP Congestion HFNS Scan Chain Optimization Place Flow
Placement
Placement is the stage of the design flow, during which each
standard cell is given an exact location
Placement does not just place the standard cell available in
the synthesized netlist, it also optimized the design.
Inputs:
1 Netlist of gates and wires.
2 Floorplan and Technology constraints
Outputs:
1 All cells located in the floorplan.
Goals:
Ahmed Abdelazeem ASIC Physical Design

11. Intro TDP Congestion HFNS Scan Chain Optimization Place Flow
Placement
Placement is the stage of the design flow, during which each
standard cell is given an exact location
Placement does not just place the standard cell available in
the synthesized netlist, it also optimized the design.
Inputs:
1 Netlist of gates and wires.
2 Floorplan and Technology constraints
Outputs:
1 All cells located in the floorplan.
Goals:
1 Provide legal location of entire netlist
2 Enable detailed route of all nets
3 Meet timing, area, and power targets
Ahmed Abdelazeem ASIC Physical Design

12. Intro TDP Congestion HFNS Scan Chain Optimization Place Flow
Global and Detailed Placement
In general, most tools partition the placement task into two
stages:
Ahmed Abdelazeem ASIC Physical Design

13. Intro TDP Congestion HFNS Scan Chain Optimization Place Flow
Global Placement
Standard cells must be in groups in such a way that the
number of connections between groups is minimum
Ahmed Abdelazeem ASIC Physical Design

14. Intro TDP Congestion HFNS Scan Chain Optimization Place Flow
Global Placement
Standard cells must be in groups in such a way that the
number of connections between groups is minimum
This issue is solved through circuit partitioning
Ahmed Abdelazeem ASIC Physical Design

15. Intro TDP Congestion HFNS Scan Chain Optimization Place Flow
Global Placement
Standard cells must be in groups in such a way that the
number of connections between groups is minimum
This issue is solved through circuit partitioning
As a basic criterion, the minimum is taken among group
connections
Ahmed Abdelazeem ASIC Physical Design

16. Intro TDP Congestion HFNS Scan Chain Optimization Place Flow
Detailed Placement
As a rule, detailed placemen
is solved in two stages:
1 Coarse placement
2 Legalization of cell
placement
Ahmed Abdelazeem ASIC Physical Design

17. Intro TDP Congestion HFNS Scan Chain Optimization Place Flow
Coarse placement
In a coarse placement all the cells are placed in the
approximate locations but they are not legally placed.
Cells overlap and are not on-grid.
Large cells (e.g. RAMs) form large placement blockages for
other smaller leaf cells.
Power routing forms routing layer blockages that will also be
checked and avoided if specified.
Ahmed Abdelazeem ASIC Physical Design

18. Intro TDP Congestion HFNS Scan Chain Optimization Place Flow
Legalize Cell Placement
Provide a legal placement for each instance with no overlap
Try and minimize wirelength (or other cost metrics)
Try to finish with uncongested design
Ahmed Abdelazeem ASIC Physical Design

19. Intro TDP Congestion HFNS Scan Chain Optimization Timing
Table of Contents
1 Introduction
2 Timing Driven Placement
3 Congestion Driven Placement
4 High Fanout Synthesis (HFS)
5 Scan Chain Reordering
6 Placement Optimization
Ahmed Abdelazeem ASIC Physical Design

20. Intro TDP Congestion HFNS Scan Chain Optimization Timing
Timing-Driven Placement (1)
All steps including placement are
timing-driven
Timing-driven placement tries to
place critical path cells close
together to reduce net RCs and to
meet setup timing
RCs are based on Virtual Route
(VR)
Ahmed Abdelazeem ASIC Physical Design

21. Intro TDP Congestion HFNS Scan Chain Optimization Timing
Timing-Driven Placement (2)
Timing-driven placement
based on Virtual Route
Tries to place cells along
timing-critical paths close
together to reduce net
RCs and meet setup
timing
Net RCs are based on
Virtual Routing (VR)
estimates
Ahmed Abdelazeem ASIC Physical Design

22. Intro TDP Congestion HFNS Scan Chain Optimization Timing
Timing-Driven Placement (3)
Standard cells are placed in “placement rows”
Cells in a timing-critical path are placed close together to
reduce routing-related delays → Timing-Driven Placement
Ahmed Abdelazeem ASIC Physical Design

23. Intro TDP Congestion HFNS Scan Chain Optimization Timing
TDP: Estimating Rnet and Cnet Before Placement
Ahmed Abdelazeem ASIC Physical Design

24. Intro TDP Congestion HFNS Scan Chain Optimization Congestion Issues Solution
-
Ahmed Abdelazeem ASIC Physical Design

25. Intro TDP Congestion HFNS Scan Chain Optimization Congestion Issues Solution
Table of Contents
1 Introduction
2 Timing Driven Placement
3 Congestion Driven Placement
4 High Fanout Synthesis (HFS)
5 Scan Chain Reordering
6 Placement Optimization
Ahmed Abdelazeem ASIC Physical Design

26. Intro TDP Congestion HFNS Scan Chain Optimization Congestion Issues Solution
Congestion
Congestion occurs when the number of required routing tracks
exceeds the number of available tracks.
Congestion can be estimated from the results of a quick global
route.
Global bins with routing overflow can be identified
Ahmed Abdelazeem ASIC Physical Design

27. Intro TDP Congestion HFNS Scan Chain Optimization Congestion Issues Solution
Congestion Driven Placement: Routing resource
Ahmed Abdelazeem ASIC Physical Design

28. Intro TDP Congestion HFNS Scan Chain Optimization Congestion Issues Solution
Placement Issues with Congestion
If congestion is not too severe, the
actual route can be detoured
around the congested area
The detoured nets will have worse
RC delay compared to the VR
estimates
congested
In highly congested areas, delay estimates during placement will be
optimistic.
Ahmed Abdelazeem ASIC Physical Design

29. Intro TDP Congestion HFNS Scan Chain Optimization Congestion Issues Solution
Non Routable on Severely Congested Design
It is important to minimize or
eliminate congestion before
continuing
Severe congestion can cause a
design to be un-routable
Ahmed Abdelazeem ASIC Physical Design

30. Intro TDP Congestion HFNS Scan Chain Optimization Congestion Issues Solution
Congestion Calculation
Ahmed Abdelazeem ASIC Physical Design

31. Intro TDP Congestion HFNS Scan Chain Optimization Congestion Issues Solution
Congestion-driven Placement
It is important to minimize or
eliminate congestion before
continuing
Severe congestion can cause a
design to be un-routable
Ahmed Abdelazeem ASIC Physical Design

32. Intro TDP Congestion HFNS Scan Chain Optimization Congestion Issues Solution
Congestion-driven Placement
Congestion Reduction
The tool tries to evaluate congestion hotspots and spread the
cells (lower utilization) in the area to reduce congestion.
The tool can also choose cell location based on congestion,
rather than wire-length.
Ahmed Abdelazeem ASIC Physical Design

33. Intro TDP Congestion HFNS Scan Chain Optimization Congestion Issues Solution
Congestion vs. Timing-Driven Placement
Ahmed Abdelazeem ASIC Physical Design

34. Intro TDP Congestion HFNS Scan Chain Optimization Congestion Issues Solution
Global Route (GR) for Congestion Map
Ahmed Abdelazeem ASIC Physical Design

35. Intro TDP Congestion HFNS Scan Chain Optimization Congestion Issues Solution
Strategies to Fix Congestion
Modify the floorplan:
Mark areas for low utilization.
Top-level ports
Changing to a different metal layer
Spreading them out, re-ordering or moving to other sides
Macro location or orientation
Alignment of bus signal pins
Increase of spacing between macros
Add blockages and halos
Core aspect ratio and size
Making block taller to add more horizontal routing resources
Increase of the block size to reduce overall congestion
Power grid
Fixing any routed or non-preferred layers
Ahmed Abdelazeem ASIC Physical Design

36. Intro TDP Congestion HFNS Scan Chain Optimization HFNS
Table of Contents
1 Introduction
2 Timing Driven Placement
3 Congestion Driven Placement
4 High Fanout Synthesis (HFS)
5 Scan Chain Reordering
6 Placement Optimization
Ahmed Abdelazeem ASIC Physical Design

37. Intro TDP Congestion HFNS Scan Chain Optimization HFNS
High Fanout Synthesis (HFS)
Ahmed Abdelazeem ASIC Physical Design

38. Intro TDP Congestion HFNS Scan Chain Optimization HFNS
High Fanout Synthesis
What is fanout?
Fanout is the number of gate inputs to which the output can
be safely connected. i.e., The load that a gate output can
drive.
The maximum fanout of an output measures it’s load-driving
capability. Fanout belongs to the output.
What are High Fanout Nets(HFN) ?
High Fanout Nets are the nets which drive more number of
load. We set some max fanout limit by using the command
set max fanout
The nets which have greater than these limit are considered as
High Fanout Nets (HFN).
Generally clock nets, reset, scan, enable nets are High Fanout
Nets.
Ahmed Abdelazeem ASIC Physical Design

39. Intro TDP Congestion HFNS Scan Chain Optimization HFNS
What is High Fanout Net Synthesis (HFNS)?
High Fanout Net Synthesis (HFNS) is the process of buffering
the High Fanout Nets to balance the load.
To balance the load HFNS is perfomed.
Too many load affects delay numbers and transition times,
Because load is directly proportional to the delay.
Generally at placement step HFNS performed. HFNS can also
be performed at synthesis step using Design Compiler. But
it’s not good idea, Buffers will be removed during PD and
again HFNS is performed.
Care that should taken during HFNS:
1 Make sure an appropriate fanout limit is set using
set max fanout command
2 Verify the SDC used for PD should not have set ideal network
or set dont touch commands on High Fanout Nets.
3 Use ideal clock network – As clock nets are synthesized
separately during Clock Tree Synthesis (CTS) step, we set
clock network as ideal network.
Ahmed Abdelazeem ASIC Physical Design

40. Intro TDP Congestion HFNS Scan Chain Optimization Scan Chain
Table of Contents
1 Introduction
2 Timing Driven Placement
3 Congestion Driven Placement
4 High Fanout Synthesis (HFS)
5 Scan Chain Reordering
6 Placement Optimization
Ahmed Abdelazeem ASIC Physical Design

41. Intro TDP Congestion HFNS Scan Chain Optimization Scan Chain
Pre-Existing Scan Chains?
Ahmed Abdelazeem ASIC Physical Design

42. Intro TDP Congestion HFNS Scan Chain Optimization Scan Chain
What’s the Issue with Existing Scan Chains?
Ahmed Abdelazeem ASIC Physical Design

43. Intro TDP Congestion HFNS Scan Chain Optimization Scan Chain
Placement Based Scan Chain Routing
Ahmed Abdelazeem ASIC Physical Design

44. Intro TDP Congestion HFNS Scan Chain Optimization Scan Chain
SCANDEF Reordering
Ahmed Abdelazeem ASIC Physical Design

45. Intro TDP Congestion HFNS Scan Chain Optimization Scan Chain
Partitioning with SCANDEF
Ahmed Abdelazeem ASIC Physical Design

46. Intro TDP Congestion HFNS Scan Chain Optimization Scan Chain
SCANDEF generated with DFTC
Ahmed Abdelazeem ASIC Physical Design

47. Intro TDP Congestion HFNS Scan Chain Optimization Scan Chain
Alpha-Numeric Ordering
Ahmed Abdelazeem ASIC Physical Design

48. Intro TDP Congestion HFNS Scan Chain Optimization Scan Chain
Reordering Within Scan-Chain
Ahmed Abdelazeem ASIC Physical Design

49. Intro TDP Congestion HFNS Scan Chain Optimization Scan Chain
Reordering Across Scan-Chains
Ahmed Abdelazeem ASIC Physical Design

50. Intro TDP Congestion HFNS Scan Chain Optimization Optimization
Table of Contents
1 Introduction
2 Timing Driven Placement
3 Congestion Driven Placement
4 High Fanout Synthesis (HFS)
5 Scan Chain Reordering
6 Placement Optimization
Ahmed Abdelazeem ASIC Physical Design

51. Intro TDP Congestion HFNS Scan Chain Optimization Optimization
Optimization techniques
Ahmed Abdelazeem ASIC Physical Design

52. Intro TDP Congestion HFNS Scan Chain Optimization Optimization
Optimization techniques
Ahmed Abdelazeem ASIC Physical Design

53. Intro TDP Congestion HFNS Scan Chain Optimization Optimization
No Hold Time Fixing
By default place opt tries to fix only setup time violations -
No hold time fixing
Hold time will be addressed during clock tree synthesis
All timing calculations are based on ideal clocks (clock skew
= 0). Therefore, it is a common practice to give more
constrained timing to placement engine with:
1 Extra uncertainty
2 Frequency Overdrive
Ahmed Abdelazeem ASIC Physical Design

54. Intro TDP Congestion HFNS Scan Chain Optimization Optimization
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Ahmed Abdelazeem ASIC Physical Design