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FPGA

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FPGA

Engineering
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Semiconductor Chips FPGA & CPLD ASICs Application Specific Integrated Circuits Microprocessors Microcontrollers
FPGA Principles • A Field-Programmable Gate Array (FPGA) is an integrated circuit that can be configured by the user to emulate any digital circuit as long as there are enough resources • An FPGA can be seen as an array of Configurable Logic Blocks (CLBs) connected through programmable interconnect (Switch Boxes)
3 Implementation Architecture Logic Implementation Interconnect Technology Symmetrical Array Row based Array Hierarchial PLD Sea of Gates Look Up table Multiplexer based PLD Block NAND Gates Static Ram Antifuse E/EPROM FPGA types
FPGA Advantages • Very fast custom logic • massively parallel operation • Faster than microcontrollers and microprocessors • much faster than DSP engines • More flexible than dedicated chipsets • allows unlimited product differentiation • More affordable and less risky than ASICs • no NRE, minimum order size, or inventory risk • Reprogrammable at any time • in design, in manufacturing, after installation
Manufacturers • Xilinx • Altera • Lattice • Actel We will work with XILINX FPGAs
.June 2011 The 4 biggest FPGA producers are : Xilinx 2.4 Billion$ in 2011 49% of US mrket Altera 40% 1. Billion955 Quick Logic 1% 26 Million$ MicriSemi 4% 207 Million $ Lattice Semi 6% 297 Million Xilinx and Altera have 89% of the Market With the top two FPGA companies taking up 89% of the FPGA market, you can be forgiven for thinking there was no one else out there. Xilinx and Altera have done a good job of defending the duopoly but a few companies are gradually winning market share by targeting specific applications
7
8 Row-based Interconnect Logic Block PLD Block Interconnect overlayed on Logic Blocks Logic Block Interconnect Sea-of-Gates Hierarchical PLD Interconnect Symmetrical Array Classes of common commercial FPGA Various Block Architecture & Routing Architecture
9 Company General Architecture Logic Block Type Programming Technology Xilinx Symmetrical Array Look-up Table Static RAM Actel Row-based Multiplexer-Based Anti-fuse Altera Hierarchical-PLD PLD Block EPROM Plessey Sea-of-Gates NAND-gate Static RAM PLUS Hierarchical-PLD PLD Block EPROM AMD Hierarchical-PLD PLD Block EEPROM QuickLogic Symmetrical Array Multiplexer-Based Anti-fuse Algotronix Sea-of-gates Multiplexers & Basic Gate Static RAM Concurrent Sea-of-gates Multiplexers & Basic Gate Static RAM Crosspoint Row-based Transistors Pairs & Multiplexers Anti-fuse FPGAs….[1] Table 2.2 Summary of Commercially Available FPGAs
10 TAB (Taped Automated Bonding) PQFP (Plastic Quad Flat Package) PLCC (Plastic Leaded Chip Carrier) DIP (Dual In-line Package)
Programmable interconnect Programmable logic blocks The Design Warrior’s Guide to FPGAs Devices, Tools, and Flows. ISBN 0750676043 Copyright © 2004 Mentor Graphics Corp. (www.mentor.com) General structure of an FPGA
Xilinx FPGAs - 16 Field-Programmable Gate Arrays • Logic blocks • to implement combinational and sequential logic • Interconnect • wires to connect inputs and outputs to logic blocks • I/O blocks • special logic blocks at periphery of device for external connections • Key questions: • how to make logic blocks programmable? • how to connect the wires? • after the chip has been fabbed
General FPGA chip architecture a.k.a. CLB -- “configurable logic block” Rissacher EE365 Lect #14
CLB CLB CLB CLB Logic cell Slice Logic cell Logic cell Slice Logic cell Logic cell Slice Logic cell Logic cell Slice Logic cell Configurable logic block (CLB) The Design Warrior’s Guide to FPGAs Devices, Tools, and Flows. ISBN 0750676043 Copyright © 2004 Mentor Graphics Corp. (www.mentor.com) Xilinx Spartan 3 FPGAs
Spartan-II FPGA Family DLL: Delay Locked Loop
Island Style Architecture
21 Interconnect Resources Logic Block I/O Cell CONCEPTUAL FPGA
Switch Boxes Fs, defines for a wiring segment entering the S block the number of other wiring segments it can be connected to
Routings using C and S Boxes
• Maze Router • A* Search Routing • The Pathfinder Routing Algorithms
Xilinx Virtex Architecture • Basic cell of the Virtex FPGA is configurable logic block(CLB) • CLB contains circuitry that allows it to efficiently perform arithmetic • LUT’s can be configured as SRAM cells • Contains programmable input output blocks (IOBs) interconnected to the CLBs
LB Logic Block LB Logic Block LB Logic Block LB Logic Block LB Logic Block LB Logic Block LB Logic Block LB Logic Block LB Logic Block S/V block I/O Cell S/V block I/O Cell S/V block I/O Cell S/V block I/O Cell S/V block I/O Cell S/V block I/O Cell S/V block I/O Cell S/V block I/O Cell S/V block I/O Cell S/V block I/O Cell S/V block I/O Cell S/V block I/O Cell FPGA - Field Programmable Gate Array
The basic elements of the FPGA structure: 1. Logic blocks  Based on memories (LUT – Lookup Table) Xilinx  Based on multiplexers (Multiplexers) Actel  Based on PAL/PLA (PAL - Programmable Array Logic, PLA – Programmable Logic Array) Altera  Transistor Pairs 2. Interconnection Resources  Symmetrical FPGA-s  Row-based FPGA-s  Sea-of-gates type of FPGA-s  Hierarchical FPGA-s (CPLD) 3. Input-output cells (I/O Cell)  Possibilities for programming : a. Input b. Output c. Bidirectional  Buffering by triggers  Slew Rate The structure of FPGA
LB Symmetrical Array LB LB LB LB LB LB LB LB Row-based LB LB LB LB LB LB LB LB LB LB Sea-of-Gates LB LB LB LB LB Hierarchical (CPLD) PLA PLA PLA PLA PLA PLA PLA PLA Architecture of FPGA-s
LUT LUT S MUX 0 1 S MUX 0 1 T T Logical block based on LUT-s
S 0 1 MUX S 0 1 MUX S 0 1 MUX 0 0 1 1 X1 X2 X3 X2 X3 Y Y = X1 X2 + X1 X3 X1 X2 + X1 X3 X3 X2 1 0 0 1 X1 = 0 X1 = 1 X3 = 0 X3 = 1 X2 = 0 X2 = 1 Example: realisation of function based on MUX-s.
T T S/V contact I/O pad S MUX 0 1 S MUX 0 1 I/O cells
Spring 2002 EECS150 - Lec05-FPGA Page 35 Idealized FPGA Logic Block • 4-input look up table (LUT) • implements combinational logic functions • Register • optionally stores output of LUT 4-LUT FF 1 0 latch Logic Block set by configuration bit-stream 4-input "look up table" OUTPUT INPUTS
The Virtex CLB
Xilinx FPGAs - 37 The Virtex CLB
Xilinx FPGAs - 38 Details of One Virtex Slice
x y COUT 0 0 1 1 0 1 0 1 y y CIN CIN Propagate = x  y Generate = y Sum= Propagate  CIN = x  y  CIN x y Carry & Control Logic in Xilinx FPGAs
Carry & Control Logic in Spartan 3 FPGAs LUT Hardwired (fast) logic
Simplified View of Spartan-3 FPGA Carry and Arithmetic Logic in One Logic Cell
Simplified View of Carry Logic in One Spartan 3 Slice
Configurable Logic Blocks A CLB can contain several slices, which make up a single CLB. Xilinx Virtex-5 FPGAs (right) have two slices: SLICEL (logic) and SLICEM (memory). In addition to the basic CLB architecture, the Virtex-5 contains wide-function MUXs which can implement: - 4:1 MUX using 1 LUT - 8:1 MUX using 2 LUTs - 16:1 MUX using 4 LUTs
4-input function 3-input function; registered
e.g. 9-input parity Implement Some Larger Functions
Xilinx FPGAs - 47 Implements any 5-input Function 5-input function
Xilinx FPGAs - 48 Two Slices: Any 6-input Function 6-input function from other slice
Xilinx FPGAs - 49 Fast Carry Chain: Add two bits per slice Sum(a,b,cin) Carry(a,b,cin) a b cin
Xilinx FPGAs - 50 Lookup Tables used as memory (16 x 2) [ Distributed Memory ]
Xilinx FPGAs - 51 Lookup Tables used as memory (32 x 1)
Xilinx FPGAs - 52 Virtex IOB
Xilinx Virtex-5 FPGAs Multi-FPGA-based emulation framework for NoC design and verification (UNLV Networking and System Integration Laboratory)
Virtex-5 CLB A single CLB in Virtex-5 consists of two slices: SLICEL (logic) and SLICEM (memory). Each CLB is connected to a switch matrix which can access to a general routing (global) matrix. Every slice contains four LUTS, wide function MUXs, carry logic, and configurable memory elements. SLICEM support storing data using distributed RAM and data shifting with 32- bit shift registers
SLICEL
SLICEM
FPGA Design Comparison Virtex-5, Virtex-6, and spartan 6 Virtex-6 CLB have the same setup as Virtex-5 (SLICEL & SLICEM) Virtex-6 devices add four additional storage elements which can only be configured as edge-triggered D-FFs. The D inputs are driven by the output of the LUTs or bypass slice inputs AX-DX
FPGA structure CLB SB SB SB CLB SB CLB SB CLB Configurable Logic Blocks Interconnection Network I/O Signals (Pins)
Simplified CLB Structure CLB SB SB SB CLB SB CLB SB CLB Configurable Logic Blocks Interconnection Network I/O Signals (Pins) Look-Up Table (LUT) Q Q SET CLR D MUX
Example: 4-input AND gate A B C D O A B C D O 0 0 0 0 0 0 0 0 1 0 0 0 1 0 0 0 0 1 1 0 0 1 0 0 0 0 1 0 1 0 0 1 1 0 0 0 1 1 1 0 1 0 0 0 0 1 0 0 1 0 1 0 1 0 0 1 0 1 1 0 1 1 0 0 0 1 1 0 1 0 1 1 1 0 0 1 1 1 1 1 Q Q SET CLR D MUX A B C D 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 Configuration bits O 0
Example 2: Find the configuration bits for the following circuit Q Q SET CLR D 2-to-1 MUX A0 A1 S Clock Q Q SET CLR D MUX A0 A1 S Configuration bits A0 A1 S 0 0 0 0 0 1 0 1 0 0 1 1 1 0 0 1 0 1 1 1 0 1 1 1
Interconnection Network CLB SB SB SB CLB SB CLB SB CLB Configurable Logic Blocks Interconnection Network I/O Signals (Pins) Configuration bits 1 0 0 0 0 0
Example 3 • Determine the configuration bits for the following circuit implementation in a 2x2 FPGA, with I/O constraints as shown in the following figure. Assume 2-input LUTs in each CLB. CLB0 SB0 SB1 SB2 CLB1 SB3 CLB2 SB4 CLB3 Input1 Input2 Output Input3 Q Q SET CLR D Input1 Input2 Input3 Output
CLBs required Q Q SET CLR D Input1 Input2 Input3 Output CLB 1 CLB 2 Q Q SET CLR D MUX Input1 Input2 0 0 0 1 Configuration bits O 1 Q Q SET CLR D MUX O Input3 0 1 1 0 Configuration bits Output 0
Placement: Select CLBs CLB0 SB0 SB1 SB2 CLB1 SB3 CLB2 SB4 CLB3 Input1 Input2 Output Input3
Routing: Select path CLB0 SB0 SB1 SB2 CLB1 SB3 CLB2 SB4 CLB3 Input1 Input2 Output Input3 Configuration bits SB1 1 0 0 0 0 0 Configuration bits SB4 0 0 0 0 1 0
Configuration Bitstream • The configuration bitstream must include ALL CLBs and SBs, even unused ones • CLB0: 00011 • CLB1: 01100 • CLB2: XXXXX • CLB3: ????? • SB0: 000000 • SB1: 000010 • SB2: 000000 • SB3: 000000 • SB4: 000001
Realistic FPGA CLB: Xilinx
XC 4000 • XC4000 CLB  3 LUTs and 2 Flip-flops in a two stage arrangement  2 Outputs: Can be registered or combinational  External signals can also be registered  More of internal signals are available for connections  Can implement any two independent functions of four variables or any single function of five variables
Spring 2002 EECS150 - Lec05-FPGA Page 72 Xilinx FPGAs (IOB detail)
XC4000E I/O Block Rissacher EE365 Lect #14
Xilinx 4000-series FPGAs Rissacher EE365 Lect #14
Xilinx Virtex-II Pro Development System
Xilinx Virtex-II Pro Development System Logic and FPGA Interaction
Xilinx Virtex 5 Development System (Front)
Xilinx Virtex 5 Development System (Back)
Xilinx Spartan-3E Starter Kit FPGA switches buttons LEDs
Virtex 5 Development System Components (FPGA) Configurable Logic Blocks Array (Row*Column): 160*54 Virtex 5 Slices: 17,280 Max Distributed RAM (Kb): 1,120 Block RAM Blocks 18Kb: 296 36Kb: 148 Max (Kb): 5,328 DSP48E Slices: 64 CMTs: 6 PowerPC Processor Blocks: 0 In Comparison to the Virtex 2 Configurable Logic Blocks Array (Row*Column): 80*46 Virtex 2 Slices: 13,969 Max Distributed RAM (Kb): 428 Block RAM Blocks Max (Kb): 2,448
Programming Environment (ISE Simulator) • ISE Foundation (Project Navigator) allows for the start of the FPGA design process • Runs in background to maintain operation and flow of design by managing the chain of tools involved including but not limited to: Embedded Development Kit (EDK), ChipScope Pro and AccelDSP • EDK consists of XPS as mentioned before this can be run independently to begin a project however use of the project navigator provides for a more organized design process of an embedded system
Recommended Tool Set • Design Entry • HDL Designer / Active HDL / Text Pad • Simulation • ModelSim / Active HDL / NC Sim • Synthesis • XST / Amplify / Synplify • Place & Route • ISE
Features Artix-7 Kintex-7 Virtex-7 Spartan-6 Virtex-6 Logic Cells 352,000 480,000 2,000,000 150,000 760,000 BlockRAM 19Mb 34Mb 68Mb 4.8Mb 38Mb DSP Slices 1,040 1,920 3,600 180 2,016 DSP Performance (symmetric FIR) 1,248GMACS 2,845GMACS 5,335GMACS 140GMACS 2,419GMA CS Transceiver Count 16 32 96 8 72 Transceiver Speed 6.6Gb/s 12.5Gb/s 28.05Gb/s 3.2Gb/s 11.18Gb/s Total Transceiver Bandwidth (full duplex) 211Gb/s 800Gb/s 2,784Gb/s 50Gb/s 536Gb/s Memory Interface (DDR3) 1,066Mb/s 1,866Mb/s 1,866Mb/s 800Mb/s 1,066Mb/s PCI Express® Interface Gen2x4 Gen2x8 Gen3x8 Gen1x1 Gen2x8 Agile Mixed Signal (AMS)/XADC Yes Yes Yes Yes Configuration AES Yes Yes Yes Yes Yes I/O Pins 600 500 1,200 576 1,200 I/O Voltage 1.2V, 1.35V, 1.5V, 1.8V, 2.5V, 3.3V 1.2V, 1.35V, 1.5V, 1.8V, 2.5V, 3.3V 1.2V, 1.35V, 1.5V, 1.8V, 2.5V, 3.3V 1.2V, 1.5V, 1.8V, 2.5V, 3.3V 1.2V, 1.5V, 1.8V, 2.5V EasyPath Cost Reduction Solution - Yes Yes - Yes FPGA Comparison Table
FPGA
FPGA

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FPGA

  • 1. Semiconductor Chips FPGA & CPLD ASICs Application Specific Integrated Circuits Microprocessors Microcontrollers
  • 2. FPGA Principles • A Field-Programmable Gate Array (FPGA) is an integrated circuit that can be configured by the user to emulate any digital circuit as long as there are enough resources • An FPGA can be seen as an array of Configurable Logic Blocks (CLBs) connected through programmable interconnect (Switch Boxes)
  • 3. 3 Implementation Architecture Logic Implementation Interconnect Technology Symmetrical Array Row based Array Hierarchial PLD Sea of Gates Look Up table Multiplexer based PLD Block NAND Gates Static Ram Antifuse E/EPROM FPGA types
  • 4. FPGA Advantages • Very fast custom logic • massively parallel operation • Faster than microcontrollers and microprocessors • much faster than DSP engines • More flexible than dedicated chipsets • allows unlimited product differentiation • More affordable and less risky than ASICs • no NRE, minimum order size, or inventory risk • Reprogrammable at any time • in design, in manufacturing, after installation
  • 5. Manufacturers • Xilinx • Altera • Lattice • Actel We will work with XILINX FPGAs
  • 6. .June 2011 The 4 biggest FPGA producers are : Xilinx 2.4 Billion$ in 2011 49% of US mrket Altera 40% 1. Billion955 Quick Logic 1% 26 Million$ MicriSemi 4% 207 Million $ Lattice Semi 6% 297 Million Xilinx and Altera have 89% of the Market With the top two FPGA companies taking up 89% of the FPGA market, you can be forgiven for thinking there was no one else out there. Xilinx and Altera have done a good job of defending the duopoly but a few companies are gradually winning market share by targeting specific applications
  • 7. 7
  • 8. 8 Row-based Interconnect Logic Block PLD Block Interconnect overlayed on Logic Blocks Logic Block Interconnect Sea-of-Gates Hierarchical PLD Interconnect Symmetrical Array Classes of common commercial FPGA Various Block Architecture & Routing Architecture
  • 9. 9 Company General Architecture Logic Block Type Programming Technology Xilinx Symmetrical Array Look-up Table Static RAM Actel Row-based Multiplexer-Based Anti-fuse Altera Hierarchical-PLD PLD Block EPROM Plessey Sea-of-Gates NAND-gate Static RAM PLUS Hierarchical-PLD PLD Block EPROM AMD Hierarchical-PLD PLD Block EEPROM QuickLogic Symmetrical Array Multiplexer-Based Anti-fuse Algotronix Sea-of-gates Multiplexers & Basic Gate Static RAM Concurrent Sea-of-gates Multiplexers & Basic Gate Static RAM Crosspoint Row-based Transistors Pairs & Multiplexers Anti-fuse FPGAs….[1] Table 2.2 Summary of Commercially Available FPGAs
  • 10. 10 TAB (Taped Automated Bonding) PQFP (Plastic Quad Flat Package) PLCC (Plastic Leaded Chip Carrier) DIP (Dual In-line Package)
  • 11.
  • 12.
  • 13. Programmable interconnect Programmable logic blocks The Design Warrior’s Guide to FPGAs Devices, Tools, and Flows. ISBN 0750676043 Copyright © 2004 Mentor Graphics Corp. (www.mentor.com) General structure of an FPGA
  • 14.
  • 15.
  • 16. Xilinx FPGAs - 16 Field-Programmable Gate Arrays • Logic blocks • to implement combinational and sequential logic • Interconnect • wires to connect inputs and outputs to logic blocks • I/O blocks • special logic blocks at periphery of device for external connections • Key questions: • how to make logic blocks programmable? • how to connect the wires? • after the chip has been fabbed
  • 17. General FPGA chip architecture a.k.a. CLB -- “configurable logic block” Rissacher EE365 Lect #14
  • 18. CLB CLB CLB CLB Logic cell Slice Logic cell Logic cell Slice Logic cell Logic cell Slice Logic cell Logic cell Slice Logic cell Configurable logic block (CLB) The Design Warrior’s Guide to FPGAs Devices, Tools, and Flows. ISBN 0750676043 Copyright © 2004 Mentor Graphics Corp. (www.mentor.com) Xilinx Spartan 3 FPGAs
  • 19. Spartan-II FPGA Family DLL: Delay Locked Loop
  • 22. Switch Boxes Fs, defines for a wiring segment entering the S block the number of other wiring segments it can be connected to
  • 23. Routings using C and S Boxes
  • 24. • Maze Router • A* Search Routing • The Pathfinder Routing Algorithms
  • 25.
  • 26.
  • 27. Xilinx Virtex Architecture • Basic cell of the Virtex FPGA is configurable logic block(CLB) • CLB contains circuitry that allows it to efficiently perform arithmetic • LUT’s can be configured as SRAM cells • Contains programmable input output blocks (IOBs) interconnected to the CLBs
  • 29. The basic elements of the FPGA structure: 1. Logic blocks  Based on memories (LUT – Lookup Table) Xilinx  Based on multiplexers (Multiplexers) Actel  Based on PAL/PLA (PAL - Programmable Array Logic, PLA – Programmable Logic Array) Altera  Transistor Pairs 2. Interconnection Resources  Symmetrical FPGA-s  Row-based FPGA-s  Sea-of-gates type of FPGA-s  Hierarchical FPGA-s (CPLD) 3. Input-output cells (I/O Cell)  Possibilities for programming : a. Input b. Output c. Bidirectional  Buffering by triggers  Slew Rate The structure of FPGA
  • 30. LB Symmetrical Array LB LB LB LB LB LB LB LB Row-based LB LB LB LB LB LB LB LB LB LB Sea-of-Gates LB LB LB LB LB Hierarchical (CPLD) PLA PLA PLA PLA PLA PLA PLA PLA Architecture of FPGA-s
  • 32. S 0 1 MUX S 0 1 MUX S 0 1 MUX 0 0 1 1 X1 X2 X3 X2 X3 Y Y = X1 X2 + X1 X3 X1 X2 + X1 X3 X3 X2 1 0 0 1 X1 = 0 X1 = 1 X3 = 0 X3 = 1 X2 = 0 X2 = 1 Example: realisation of function based on MUX-s.
  • 34.
  • 35. Spring 2002 EECS150 - Lec05-FPGA Page 35 Idealized FPGA Logic Block • 4-input look up table (LUT) • implements combinational logic functions • Register • optionally stores output of LUT 4-LUT FF 1 0 latch Logic Block set by configuration bit-stream 4-input "look up table" OUTPUT INPUTS
  • 37. Xilinx FPGAs - 37 The Virtex CLB
  • 38. Xilinx FPGAs - 38 Details of One Virtex Slice
  • 39.
  • 40. x y COUT 0 0 1 1 0 1 0 1 y y CIN CIN Propagate = x  y Generate = y Sum= Propagate  CIN = x  y  CIN x y Carry & Control Logic in Xilinx FPGAs
  • 41. Carry & Control Logic in Spartan 3 FPGAs LUT Hardwired (fast) logic
  • 42. Simplified View of Spartan-3 FPGA Carry and Arithmetic Logic in One Logic Cell
  • 43. Simplified View of Carry Logic in One Spartan 3 Slice
  • 44. Configurable Logic Blocks A CLB can contain several slices, which make up a single CLB. Xilinx Virtex-5 FPGAs (right) have two slices: SLICEL (logic) and SLICEM (memory). In addition to the basic CLB architecture, the Virtex-5 contains wide-function MUXs which can implement: - 4:1 MUX using 1 LUT - 8:1 MUX using 2 LUTs - 16:1 MUX using 4 LUTs
  • 47. Xilinx FPGAs - 47 Implements any 5-input Function 5-input function
  • 48. Xilinx FPGAs - 48 Two Slices: Any 6-input Function 6-input function from other slice
  • 49. Xilinx FPGAs - 49 Fast Carry Chain: Add two bits per slice Sum(a,b,cin) Carry(a,b,cin) a b cin
  • 50. Xilinx FPGAs - 50 Lookup Tables used as memory (16 x 2) [ Distributed Memory ]
  • 51. Xilinx FPGAs - 51 Lookup Tables used as memory (32 x 1)
  • 52. Xilinx FPGAs - 52 Virtex IOB
  • 53. Xilinx Virtex-5 FPGAs Multi-FPGA-based emulation framework for NoC design and verification (UNLV Networking and System Integration Laboratory)
  • 54. Virtex-5 CLB A single CLB in Virtex-5 consists of two slices: SLICEL (logic) and SLICEM (memory). Each CLB is connected to a switch matrix which can access to a general routing (global) matrix. Every slice contains four LUTS, wide function MUXs, carry logic, and configurable memory elements. SLICEM support storing data using distributed RAM and data shifting with 32- bit shift registers
  • 57. FPGA Design Comparison Virtex-5, Virtex-6, and spartan 6 Virtex-6 CLB have the same setup as Virtex-5 (SLICEL & SLICEM) Virtex-6 devices add four additional storage elements which can only be configured as edge-triggered D-FFs. The D inputs are driven by the output of the LUTs or bypass slice inputs AX-DX
  • 58.
  • 59.
  • 60. FPGA structure CLB SB SB SB CLB SB CLB SB CLB Configurable Logic Blocks Interconnection Network I/O Signals (Pins)
  • 61. Simplified CLB Structure CLB SB SB SB CLB SB CLB SB CLB Configurable Logic Blocks Interconnection Network I/O Signals (Pins) Look-Up Table (LUT) Q Q SET CLR D MUX
  • 62. Example: 4-input AND gate A B C D O A B C D O 0 0 0 0 0 0 0 0 1 0 0 0 1 0 0 0 0 1 1 0 0 1 0 0 0 0 1 0 1 0 0 1 1 0 0 0 1 1 1 0 1 0 0 0 0 1 0 0 1 0 1 0 1 0 0 1 0 1 1 0 1 1 0 0 0 1 1 0 1 0 1 1 1 0 0 1 1 1 1 1 Q Q SET CLR D MUX A B C D 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 Configuration bits O 0
  • 63. Example 2: Find the configuration bits for the following circuit Q Q SET CLR D 2-to-1 MUX A0 A1 S Clock Q Q SET CLR D MUX A0 A1 S Configuration bits A0 A1 S 0 0 0 0 0 1 0 1 0 0 1 1 1 0 0 1 0 1 1 1 0 1 1 1
  • 64. Interconnection Network CLB SB SB SB CLB SB CLB SB CLB Configurable Logic Blocks Interconnection Network I/O Signals (Pins) Configuration bits 1 0 0 0 0 0
  • 65. Example 3 • Determine the configuration bits for the following circuit implementation in a 2x2 FPGA, with I/O constraints as shown in the following figure. Assume 2-input LUTs in each CLB. CLB0 SB0 SB1 SB2 CLB1 SB3 CLB2 SB4 CLB3 Input1 Input2 Output Input3 Q Q SET CLR D Input1 Input2 Input3 Output
  • 66. CLBs required Q Q SET CLR D Input1 Input2 Input3 Output CLB 1 CLB 2 Q Q SET CLR D MUX Input1 Input2 0 0 0 1 Configuration bits O 1 Q Q SET CLR D MUX O Input3 0 1 1 0 Configuration bits Output 0
  • 67. Placement: Select CLBs CLB0 SB0 SB1 SB2 CLB1 SB3 CLB2 SB4 CLB3 Input1 Input2 Output Input3
  • 68. Routing: Select path CLB0 SB0 SB1 SB2 CLB1 SB3 CLB2 SB4 CLB3 Input1 Input2 Output Input3 Configuration bits SB1 1 0 0 0 0 0 Configuration bits SB4 0 0 0 0 1 0
  • 69. Configuration Bitstream • The configuration bitstream must include ALL CLBs and SBs, even unused ones • CLB0: 00011 • CLB1: 01100 • CLB2: XXXXX • CLB3: ????? • SB0: 000000 • SB1: 000010 • SB2: 000000 • SB3: 000000 • SB4: 000001
  • 71. XC 4000 • XC4000 CLB  3 LUTs and 2 Flip-flops in a two stage arrangement  2 Outputs: Can be registered or combinational  External signals can also be registered  More of internal signals are available for connections  Can implement any two independent functions of four variables or any single function of five variables
  • 72. Spring 2002 EECS150 - Lec05-FPGA Page 72 Xilinx FPGAs (IOB detail)
  • 73. XC4000E I/O Block Rissacher EE365 Lect #14
  • 74.
  • 75.
  • 76.
  • 77.
  • 78.
  • 79.
  • 80.
  • 81.
  • 82.
  • 83.
  • 85. Xilinx Virtex-II Pro Development System
  • 86. Xilinx Virtex-II Pro Development System Logic and FPGA Interaction
  • 87. Xilinx Virtex 5 Development System (Front)
  • 88. Xilinx Virtex 5 Development System (Back)
  • 89. Xilinx Spartan-3E Starter Kit FPGA switches buttons LEDs
  • 90. Virtex 5 Development System Components (FPGA) Configurable Logic Blocks Array (Row*Column): 160*54 Virtex 5 Slices: 17,280 Max Distributed RAM (Kb): 1,120 Block RAM Blocks 18Kb: 296 36Kb: 148 Max (Kb): 5,328 DSP48E Slices: 64 CMTs: 6 PowerPC Processor Blocks: 0 In Comparison to the Virtex 2 Configurable Logic Blocks Array (Row*Column): 80*46 Virtex 2 Slices: 13,969 Max Distributed RAM (Kb): 428 Block RAM Blocks Max (Kb): 2,448
  • 91. Programming Environment (ISE Simulator) • ISE Foundation (Project Navigator) allows for the start of the FPGA design process • Runs in background to maintain operation and flow of design by managing the chain of tools involved including but not limited to: Embedded Development Kit (EDK), ChipScope Pro and AccelDSP • EDK consists of XPS as mentioned before this can be run independently to begin a project however use of the project navigator provides for a more organized design process of an embedded system
  • 92. Recommended Tool Set • Design Entry • HDL Designer / Active HDL / Text Pad • Simulation • ModelSim / Active HDL / NC Sim • Synthesis • XST / Amplify / Synplify • Place & Route • ISE
  • 93. Features Artix-7 Kintex-7 Virtex-7 Spartan-6 Virtex-6 Logic Cells 352,000 480,000 2,000,000 150,000 760,000 BlockRAM 19Mb 34Mb 68Mb 4.8Mb 38Mb DSP Slices 1,040 1,920 3,600 180 2,016 DSP Performance (symmetric FIR) 1,248GMACS 2,845GMACS 5,335GMACS 140GMACS 2,419GMA CS Transceiver Count 16 32 96 8 72 Transceiver Speed 6.6Gb/s 12.5Gb/s 28.05Gb/s 3.2Gb/s 11.18Gb/s Total Transceiver Bandwidth (full duplex) 211Gb/s 800Gb/s 2,784Gb/s 50Gb/s 536Gb/s Memory Interface (DDR3) 1,066Mb/s 1,866Mb/s 1,866Mb/s 800Mb/s 1,066Mb/s PCI Express® Interface Gen2x4 Gen2x8 Gen3x8 Gen1x1 Gen2x8 Agile Mixed Signal (AMS)/XADC Yes Yes Yes Yes Configuration AES Yes Yes Yes Yes Yes I/O Pins 600 500 1,200 576 1,200 I/O Voltage 1.2V, 1.35V, 1.5V, 1.8V, 2.5V, 3.3V 1.2V, 1.35V, 1.5V, 1.8V, 2.5V, 3.3V 1.2V, 1.35V, 1.5V, 1.8V, 2.5V, 3.3V 1.2V, 1.5V, 1.8V, 2.5V, 3.3V 1.2V, 1.5V, 1.8V, 2.5V EasyPath Cost Reduction Solution - Yes Yes - Yes FPGA Comparison Table

Editor's Notes

  1. The S boxes allow wires to switch between vertical and horizontal wires. Its flexibility, Fs, defines for a wiring segment entering the S block the number of other wiring segments it can be connected to. The topology of the S blocks is very important since it is possible to choose two different topologies with the same flexibility Fs that result in very different routabilities. For example, this figure shows that meanwhile topology 1 can’t connect wire A with B, topology 2 can.
  2. Has 2 Physical Power PC Cores
  3. Top: Block Diagram of the Virtex-II System LEFT Side: Ways to configure the FPGA, Power the FPGA, Manage Clocking of the FPGA RIGHT Side: Components/Peripherals and Outputs that can be utilized by the FPGA Bottom: I/O pad connections to the Peripheral Devices
  4. Unlike the Virtex 2 the Virtex 5 uses a MicroBlaze processor; it is entirely software-based. Designed for Xilinx FPGAs from Xilinx. As a soft-core processor, MicroBlaze is implemented entirely in the general-purpose memory and logic fabric of Xilinx FPGAs
  5. 1. Virtex-5 FPGA slices are organized differently from previous generations. Each Virtex-5 FPGA slice contains four LUTs and four flip-flops (previously it was two LUTs and two flip-flops.) 2. Each DSP48E slice contains a 25 x 18 multiplier, an adder, and an accumulator. 3. Block RAMs are fundamentally 36 Kbits in size. Each block can also be used as two independent 18-Kbit blocks. 4. Each Clock Management Tile (CMT) contains two DCMs and one PLL. 5. This table lists separate Ethernet MACs per device. 6. RocketIO GTP transceivers are designed to run from 100 Mb/s to 3.75 Gb/s. RocketIO GTX transceivers are designed to run from 150 Mb/s to 6.5 Gb/s. 7. This number does not include RocketIO transceivers. 8. Includes configuration Bank 0. DCM: Digital Clock Manager A phase-locked loop or phase lock loop (PLL) is a control system that generates a signal that has a fixed relation to the phase of a "reference" signal. A phase-locked loop circuit responds to both the frequency and the phase of the input signals, automatically raising or lowering the frequency of a controlled oscillator until it is matched to the reference in both frequency and phase. A phase-locked loop is an example of a control system using negative feedback. In simpler terms, a PLL compares the frequencies of two signals and produces an error signal which is proportional to the difference between the input frequencies. The error signal is then low-pass filtered and used to drive a voltage-controlled oscillator (VCO) which creates an output frequency. The output frequency is fed through a frequency divider back to the input of the system, producing a negative feedback loop. If the output frequency drifts, the error signal will increase, driving the frequency in the opposite direction so as to reduce the error. Thus the output is locked to the frequency at the other input. This input is called the reference and is often derived from a crystal oscillator, which is very stable in frequency.