Assignment#7a
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This document describes how to implement a full adder and full subtractor using an 8:1 multiplexer. It provides the theory of multiplexers, truth tables for full adders and full subtractors, and circuit diagrams showing how to connect the components. The procedure explains how to check components, insert the IC, make connections, provide inputs, and observe the outputs on LEDs to verify the circuits. The goal is to design full adders and full subtractors using an 8:1 multiplexer.
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Assignment#3b
This document discusses the implementation of half subtractors and full subtractors using basic logic gates and universal gates. It begins by defining a half subtractor and full subtractor, providing their truth tables. It then shows how to design half and full subtractors using NAND, NOR, and other gates. Circuit diagrams are provided for subtractors built with basic gates as well as those using only NAND or only NOR gates. The purpose is for students to realize subtractor circuits using different gate implementations and understand their logic and components.
Assignment#1a
To study and verify the truth table of logic gates. Also study the realization of
basic gates using universal gates.
Assignment#4b
This document provides instructions for designing and implementing an 8:1 multiplexer using a 74151 IC. It describes the components needed, including the 74151 IC, and provides pin diagrams and a truth table for the IC. It then gives two Boolean expressions to implement using the multiplexer - f1 = ∑ m (2, 3, 6, 7) and f2 = ∏ M (2, 3, 5, 7) - and provides the procedure for connecting the inputs to achieve the desired logic functions using the multiplexer. The goal is to use the 74151 IC to physically realize the two Boolean expressions.
Assignment#7b
This document describes how to implement a 16:1 multiplexer using two 8:1 multiplexers and an OR gate. It provides details on the components needed, including IC 74151 (8:1 multiplexer), IC 7432 (OR gate), and IC 7404 (NOT gate). It includes the pin descriptions and truth tables of the IC 74151 8:1 multiplexer. The circuit diagram shows how two IC 74151 multiplexers and an IC 7432 OR gate can be connected to create a 16:1 multiplexer. The procedure and results of building this circuit on a logic gates trainer kit are also outlined.
Assignment#6
This document provides instructions for implementing a MOD-10 counter using the IC 7490 decade counter chip. It begins with an overview of counter circuits and describes asynchronous and synchronous counters. It then discusses modulus counters and explains that a MOD-10 counter requires 4 flip-flops. The truth table and internal structure of the IC 7490 chip are shown, along with a logic diagram for the MOD-10 counter circuit. Steps are provided to build the circuit using the IC 7490 and verify that it functions as a MOD-10 counter by observing the output LEDs for different input combinations.
Assignment#2
The document discusses implementing reduced Boolean functions using K-maps and basic or universal logic gates. It provides examples of using K-maps to reduce Boolean expressions in sum of products (SOP) and product of sums (POS) form. Truth tables are converted to K-maps and the reduced expressions are then used to design logic circuits with AND, OR, NOT, NAND and NOR gates. Components required and procedures for building the circuits are also outlined.
Assignment#3a
This document discusses the implementation of half adders and full adders using basic logic gates and universal gates. It provides truth tables and logic equations for half adders and full adders. Circuit designs are shown for implementing half adders using only NAND gates or only NOR gates. Full adders are also implemented using basic gates, two half adders, or only NAND gates or only NOR gates. The purpose is for students to realize adder circuits using different gate configurations and observe the outputs on an IC trainer kit by providing various input combinations.
Assignment#1b
Implementation of given Boolean functions using basic gates and universal gates in
both SOP (Sum of Product) and POS (Product of Sum) form.
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Assignment#3b
This document discusses the implementation of half subtractors and full subtractors using basic logic gates and universal gates. It begins by defining a half subtractor and full subtractor, providing their truth tables. It then shows how to design half and full subtractors using NAND, NOR, and other gates. Circuit diagrams are provided for subtractors built with basic gates as well as those using only NAND or only NOR gates. The purpose is for students to realize subtractor circuits using different gate implementations and understand their logic and components.
Assignment#1a
To study and verify the truth table of logic gates. Also study the realization of
basic gates using universal gates.
Assignment#4b
This document provides instructions for designing and implementing an 8:1 multiplexer using a 74151 IC. It describes the components needed, including the 74151 IC, and provides pin diagrams and a truth table for the IC. It then gives two Boolean expressions to implement using the multiplexer - f1 = ∑ m (2, 3, 6, 7) and f2 = ∏ M (2, 3, 5, 7) - and provides the procedure for connecting the inputs to achieve the desired logic functions using the multiplexer. The goal is to use the 74151 IC to physically realize the two Boolean expressions.
Assignment#7b
This document describes how to implement a 16:1 multiplexer using two 8:1 multiplexers and an OR gate. It provides details on the components needed, including IC 74151 (8:1 multiplexer), IC 7432 (OR gate), and IC 7404 (NOT gate). It includes the pin descriptions and truth tables of the IC 74151 8:1 multiplexer. The circuit diagram shows how two IC 74151 multiplexers and an IC 7432 OR gate can be connected to create a 16:1 multiplexer. The procedure and results of building this circuit on a logic gates trainer kit are also outlined.
Assignment#6
This document provides instructions for implementing a MOD-10 counter using the IC 7490 decade counter chip. It begins with an overview of counter circuits and describes asynchronous and synchronous counters. It then discusses modulus counters and explains that a MOD-10 counter requires 4 flip-flops. The truth table and internal structure of the IC 7490 chip are shown, along with a logic diagram for the MOD-10 counter circuit. Steps are provided to build the circuit using the IC 7490 and verify that it functions as a MOD-10 counter by observing the output LEDs for different input combinations.
Assignment#2
The document discusses implementing reduced Boolean functions using K-maps and basic or universal logic gates. It provides examples of using K-maps to reduce Boolean expressions in sum of products (SOP) and product of sums (POS) form. Truth tables are converted to K-maps and the reduced expressions are then used to design logic circuits with AND, OR, NOT, NAND and NOR gates. Components required and procedures for building the circuits are also outlined.
Assignment#3a
This document discusses the implementation of half adders and full adders using basic logic gates and universal gates. It provides truth tables and logic equations for half adders and full adders. Circuit designs are shown for implementing half adders using only NAND gates or only NOR gates. Full adders are also implemented using basic gates, two half adders, or only NAND gates or only NOR gates. The purpose is for students to realize adder circuits using different gate configurations and observe the outputs on an IC trainer kit by providing various input combinations.
Assignment#1b
Implementation of given Boolean functions using basic gates and universal gates in
both SOP (Sum of Product) and POS (Product of Sum) form.
Assignment#4a
A 4:1 multiplexer is designed and implemented using a 74153 IC. The 74153 IC contains two multiplexers that each have 4 inputs and 1 output. The IC uses a pair of select lines (S1 and S0) to choose which of the 4 inputs is transmitted to the output. When the enable/strobe line is low, the selected input is sent to the output regardless of the state of the other inputs. The document provides the pin diagram, truth table, and procedure for connecting the 74153 IC to implement a 4:1 multiplexer that can select one of 4 inputs for its output based on the values of the select lines.
Assignment#5
This document discusses various types of flip flops including RS, JK, D, and T flip flops. It provides the theory of sequential circuits and flip flops. It also gives the truth tables and explanations for each type of flip flop. The aim is to verify the truth tables of these flip flops experimentally using logic gates, input switches, and output LEDs. The procedure and result are to check the components, make the circuit connections, provide various input combinations, and note the output to verify the truth tables for each flip flop type.
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Decoders
A decoder is a digital circuit that takes binary inputs and selects one of multiple outputs. It has N inputs and 2N outputs. The decoder decodes the binary value on its N inputs and activates exactly one output corresponding to that input combination. Decoders generate all possible combinations or "minterms" of the input variables.
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The truth table is not complete because it is missing the encoding for when no inputs are active. A complete truth table would include a row for all zero inputs to specify the output in that case.
The output equations are:
A0 = D7
A1 = D6 + D5 + D4 + D3
A2 = D2 + D1 + D0
This encodes the highest priority input on the lowest two bits, with the next two highest priorities on the middle bit, and any active input setting the highest bit.
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Assignment#4a
A 4:1 multiplexer is designed and implemented using a 74153 IC. The 74153 IC contains two multiplexers that each have 4 inputs and 1 output. The IC uses a pair of select lines (S1 and S0) to choose which of the 4 inputs is transmitted to the output. When the enable/strobe line is low, the selected input is sent to the output regardless of the state of the other inputs. The document provides the pin diagram, truth table, and procedure for connecting the 74153 IC to implement a 4:1 multiplexer that can select one of 4 inputs for its output based on the values of the select lines.
Assignment#5
This document discusses various types of flip flops including RS, JK, D, and T flip flops. It provides the theory of sequential circuits and flip flops. It also gives the truth tables and explanations for each type of flip flop. The aim is to verify the truth tables of these flip flops experimentally using logic gates, input switches, and output LEDs. The procedure and result are to check the components, make the circuit connections, provide various input combinations, and note the output to verify the truth tables for each flip flop type.
What is a decoder and 2 to 4 DECODER
A binary decoder converts an n-bit binary input into a one-hot 2^n bit output. It has n input lines and 2^n output lines. A 2-to-4 binary decoder takes a 2-bit binary input and activates exactly one of its 4 output lines based on the input. It can be implemented using AND and NOT gates, with an enable input to control the outputs. Alternatively, a 2-to-4 decoder can be implemented using NAND gates to generate the max terms as outputs.
Decoders
A decoder is a digital circuit that takes binary inputs and selects one of multiple outputs. It has N inputs and 2N outputs. The decoder decodes the binary value on its N inputs and activates exactly one output corresponding to that input combination. Decoders generate all possible combinations or "minterms" of the input variables.
08 decoder
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Multiplexer
A multiplexer has N control inputs, 2^N data inputs, and 1 output. It routes the selected data input to the output based on the value of the control inputs. The document provides examples of using multiplexers to build larger multiplexers, including an 8-to-1 multiplexer using 4-to-1 and 2-to-1 multiplexers, and a 16-to-1 multiplexer using only 4-to-1 multiplexers. It also mentions multiplexers can be designed in VHDL.
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This document discusses decoders and provides details about binary coded decimal (BCD) to decimal decoders. It explains that decoders recognize various input combinations and provide corresponding outputs. A BCD to decimal decoder specifically provides decimal outputs from a binary coded input. The document then presents the circuit design and operation of a BCD to decimal decoder using AND gates. It analyzes how the circuit decodes input codes to activate the proper decimal output and discusses how faults could be identified by analyzing input-output relationships.
Decoder
A decoder is a logic circuit that takes a binary input and activates only one of multiple outputs based on the input value. If a decoder has an n-bit input, it will have 2^n outputs. The decoder's truth table shows the logic function that maps each input combination to activate the correct output. The circuit diagram implements this logic function using gates.
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This document discusses binary addition and different types of adders used in digital circuits. It describes half adders, full adders, and ripple carry adders. A ripple carry adder is constructed by cascading full adder blocks in series, with the carryout of one stage feeding into the carry-in of the next stage. For an n-bit ripple carry adder, n full adders are required. The document provides truth tables for a full adder and ripple carry adder, and includes block diagrams and layout of a 4-bit ripple carry adder. Ripple carry adders are suitable for small bit applications and allow easy addition of two n-bit numbers.
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Encoders and decoders are combinational logic circuits that convert between binary and encoded representations. An encoder converts data into a coded format, while a decoder converts the coded data back into its original form. Specific encoder and decoder circuits are discussed, including octal to binary encoders, priority encoders, binary decoders, BCD to decimal decoders, and BCD to seven segment decoders. Truth tables and schematic diagrams are provided to illustrate how these circuits function.
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This document discusses various combinational logic circuits including encoders, decoders, and multiplexers. It provides objectives for constructing and verifying binary to gray code converters, gray to binary converters, two to four line decoders, seven segment decoders, priority encoders, and two to one and four to one line multiplexers. It also defines combinational circuits, discusses code conversion procedures for gray codes, different types of decoders including one to two line and two to four line decoders, and applications of multiplexers and demultiplexers. Finally, it contrasts the key differences between combinational and sequential logic circuits.
Decoder for digital electronics
A decoder is a logic circuit that takes a binary input and activates only one output corresponding to the input number. It has N input lines to handle N-bit codes and 2^N output lines. A decoder uses AND gates as the basic decoding element, producing a HIGH output only when all inputs are HIGH. For example, a 4-bit BCD-to-7-segment decoder takes a 4-bit BCD coded input and outputs the correct 7-bit code to light the appropriate segments on a 7-segment display to display the corresponding decimal number.
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The document describes the design of a 0-9 binary coded decimal (BCD) counter circuit. The circuit uses a 74LS90 BCD decade counter integrated circuit to count from 0 to 9, and a 74LS47 BCD to 7-segment decoder driver integrated circuit to display the count on a 7-segment display. When a push button is pressed, the counter increments and the display updates to show the new count. Potential applications mentioned include token counters, production line counting systems, clocks, and timers.
Dld (lab 1 & 2)
The document provides instructions for a lab experiment using a microprocessor interfacing trainer (AM-2001). It includes:
- An overview of the AM-2001 which allows interfacing with microprocessors through an ISA bus interface card, making it platform independent.
- A description of the hardware components included in the AM-2001 such as power supplies, logic level indicators, logic switches, and a binary coded decimal input.
- Instructions for Lab 1 which introduce the components and demonstrate measuring logic levels and using logic switches and BCD input.
- Instructions for Lab 2 involve using an AND gate IC to verify its truth table outputs by connecting switches as inputs and an LED as the output.
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The document describes the design of combinational logic circuits for 7-segment displays, comparators, adders, and parallel adders. It includes truth tables, Karnaugh maps, logic expressions, and circuit diagrams for 7-segment displays to display digits, a 2-bit comparator to compare two binary numbers, half adders, full adders using half adders, and a 4-bit parallel binary adder.
multiplexer and d-multiplexer
The truth table is not complete because it is missing the encoding for when no inputs are active. A complete truth table would include a row for all zero inputs to specify the output in that case.
The output equations are:
A0 = D7
A1 = D6 + D5 + D4 + D3
A2 = D2 + D1 + D0
This encodes the highest priority input on the lowest two bits, with the next two highest priorities on the middle bit, and any active input setting the highest bit.
Encoder
This presentation introduces encoders. It discusses that an encoder is a combinational circuit that performs the reverse operation of a decoder, with a maximum of 2n inputs and n outputs. The simplest encoder is a 2n-to-n binary encoder, where one of the 2n inputs is 1 and the output is an n-bit binary number representing the activated input. An example of an 8-to-3 binary encoder is shown, where only one of the 8 inputs can be activated at a time, and the 3 outputs represent the activated input in binary code.
Encoder decoder
The document describes the design of an encoder-decoder system in Verilog. It includes a 4-to-2 encoder, 2-to-4 decoder, and a top-level module that instantiates the encoder and decoder. The encoder and decoder are designed based on their truth tables. Verilog code and RTL schematics are provided for the encoder, decoder, and top-level modules. A full testbench and waveform are also included to test the system.
Combinational circuit
This document discusses combinational circuits. It defines a combinational circuit as a circuit whose output depends only on the current input levels and not previous states. Combinational circuits do not use memory. The document lists three categories of combinational circuits: arithmetic and logical functions, data transmission, and code conversion. It provides adder circuits as examples, defining a half adder and full adder, and including their truth tables.
a simple bcd counter project
This document describes the design and implementation of a 0-99 digital BCD counter circuit. The circuit uses a 4026 IC and 7-segment displays to display the count. It can operate in two modes - manually using a switch or automatically using a 555 timer as a clock. The circuit was designed, simulated in Proteus, built on a breadboard, and tested to meet the criteria of counting from 0-99 on two displays.
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This is the design for an 8-bit multiplier. After that 20 different values are calculated from the multiplier and then all are added at the end.
combinational-circuit (1).ppt
The document discusses combinational logic circuits including decoders, encoders, multiplexers, demultiplexers, adders, subtractors, and magnitude comparators. It provides details on their design procedures, truth tables, logic diagrams, and implementations using basic logic gates. Combinational logic circuits have outputs that depend only on the current inputs and do not have memory elements.
Arithmetic and logic unit
1. A bus is a communication system that transfers data between components inside a computer or between computers using both parallel and serial connections.
2. An Arithmetic Logic Unit (ALU) performs arithmetic and logical operations and was a core component of the earliest computer architectures proposed by John Von Neumann in 1945.
3. Logic gates are the basic building blocks of digital circuits and perform logical operations like AND, OR, and NOT on binary inputs to produce binary outputs. Common logic gates include AND, OR, NOT, NAND, NOR, XOR, and XNOR.
Lesson Week 1-2.pptx
Combinational circuits are digital logic circuits whose outputs depend only on the current inputs. They include half adders, full adders, decoders, encoders, and multiplexers. A half adder performs addition of two bits and produces sum and carry outputs. A full adder can add three bits by including the previous bit's carry. Combinational circuits can be represented through truth tables, Boolean equations, or schematic diagrams. Subtraction circuits like half and full subtractors also exist to perform subtraction operations.
combinational circuit-Half Adder ,full Adder
this is a simple presentation on
Half combinational logic circuits .to implement a logic, we use logic circuits. There are two types of logic circuits – combinational logic circuits and sequential logic circuits. To implement a logic, we use logic circuits. There are two types of logic circuits – combinational logic circuits and sequential logic circuits. Combinational logic circuits are time-independent circuits that deploy boolean logic to achieve output. This output depends on the current input and nothing else. Arithmetic logic is necessary for any digital system, as we have seen earlier.To implement a logic, we use logic circuits. There are two types of logic circuits – combinational logic circuits and sequential logic circuits. Combinational logic circuits are time-independent circuits that deploy boolean logic to achieve output. This output depends on the current input and nothing else. Arithmetic logic is necessary for any digital system, as we have seen earlier.To implement a logic, we use logic circuits. There are two types of logic circuits – combinational logic circuits and sequential logic circuits. Combinational logic circuits are time-independent circuits that deploy boolean logic to achieve output. This output depends on the current input and nothing else. Arithmetic logic is necessary for any digital system, as we have seen earlier. are time-independent circuits that deploy boolean logic to achieve output. This output depends on the current input and nothing else. Arithmetic logic is necessary for any digital system, as we have seen earlier.A half adder is an arithmetic combinational logic circuit that adds two 1-bit inputs to give the sum and the carry generated as the output.A half adder is an arithmetic combinational logic circuit that adds two 1-bit inputs to give the sum and the carry generated as the output.The half adder circuit adds two single bits and ignores any carry if generated. Since any addition where a carry is present isn’t complete without adding the carry, the operation is not complete. Hence the circuit is known as a half-adder. Let’s write the truth table using general boolean logic for addition
Full Adder using Half Adder:
Compare the equations for half adder and full adder. The equation for SUM requires just an additional input EXORed with the half adder output. So we add the Y input and the output of the half adder to an EXOR gate. Similarly, for the carry output of the half adder, we need to add Y(A+B) in an OR configuration.
Half Subtractor:
Quite similar to the half adder, a half subtractor subtracts two 1-bit binary numbers to give two outputs, difference and borrow. Since it neglects any borrow inputs and essentially performs half the function of a subtractor, it is known as the half subtractor
Full Subtractor:
A full subtractor accounts for the borrow that a half subtractor neglects. Hence it has three inputs and two outputs. We will write the truth table for the full subtractor based on this info.
Half Subtractor : Combiational Circuit
The document describes building a half subtractor circuit to subtract two bits and verify the output using a truth table. The half subtractor has two inputs - minuend and subtrahend - and two outputs - the difference and borrow bit. The procedure involves connecting the circuit as shown, setting input bit streams, running the simulation, and verifying the output matches the truth table.
Digital electronics lab
The document describes experiments conducted in a digital electronics lab to study and implement various logic gates and digital circuits. It includes summaries of experiments to study logic gates and verify their truth tables, design adders and subtractors using logic gates, and design various code converters including binary to gray, gray to binary, BCD to excess-3, and excess-3 to BCD. The document provides circuit diagrams, truth tables, and procedures for designing and verifying the operation of each digital circuit using logic gates.
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Assignment#7a
- 1. Digital Technique Mrs. Sunita M Dol Page 1 HANDOUT#7a AIM: Implementation of full adder and full subtractor using 8:1 mux LEARNING OBJECTIVES: - Implement full adder and full subtractor using 8:1 multiplexer. COMPONENT REQUIRED: - Logic gates (IC) trainer kit. - Connecting patch chords. - IC 74151 Sr. No. Component Specification 1 8:1 mux IC74151 THEORY: Mutiplexer or data selector is the combinational circuit that gets one out of several inputs to a single output. In multiplexer, the input selected is controlled by a set of select lines. For selecting one out of n inputs for connection to the output, a set of m select lines is required where 2m =n. Depending upon the digital code applied at select lines, one out of n data sources is selected and transmitted to a single output channel. A strobe or enable input G is incorporated which helps in cascading and it is generally active low which means it perform its intended operation when it is low. IC 74151 Description o IC 74151 is used as 8:1 mux. It is a 16 pin IC. o Pin number 4, 3, 2, 1, 15, 14, 13, 12 acts as input signal from 0 to 7 respectively. o Pin number 9, 10, 11 are the select inputs used to set an input. o We get the output of this circuit at pin number 5. And its complement on pin number 6.
- 2. Digital Technique Mrs. Sunita M Dol Page 2 o Pin number 7 acts as a strobe which is used for cascading purpose otherwise it is connected to the ground. o Pin number 16 is the power supply that is Vcc. o The block diagram of IC 74151 is given in figure a and pin diagram of IC 74151 is given in figure b. Figure a: Block diagram
- 3. Digital Technique Mrs. Sunita M Dol Page 3 Figure b: Pin diagram Truth table: Select Input Output Y S2 S1 S0 I0 0 0 0 0 I1 0 0 1 1 I2 0 1 0 2 I3 0 1 1 3 I4 1 0 0 4 I5 1 0 1 5 I6 1 1 0 6 I7 1 1 1 7 The design procedure is given below: o Identify the decimal number corresponding to the each minterm in the expression. The input lines corresponding to these numbers are to be connected to logic 0 level. o All other input lines are to be connected to logic 0 level. o The inputs are to be applied to the select lines.
- 4. Digital Technique Mrs. Sunita M Dol Page 4 Full Adder: A half adder has only two inputs and there is no provision to add a carry coming from the lower bits when multibit addition is performed. For this purpose, a 3rd input terminal is added and this circuit is used to add An, Bn and Cn-1 where An & Bn are the nth order bit of the numbers A and B respectively and Cn-1 is the carry generated from the addition of (n-1)th order bit. This circuit is referred to as Full Adder. Truth table: An Bn Cn-1 Sn(sum) Cn(carry) 0 0 0 0 0 0 0 1 1 0 0 1 0 1 0 0 1 1 0 1 1 0 0 1 0 1 0 1 0 1 1 1 0 0 1 1 1 1 1 1 Figure a: Full Adder-Sum
- 5. Digital Technique Mrs. Sunita M Dol Page 5 Figure b: Full Adder-Carry Full Subtractor: Just like Full Adder, we require full subtractor circuit for performing multibit subtraction wherein a borrow from the previous bit position may also there. A full subtractor will have three inputs An (minuend), Bn(subtrahend) and Cn-1 (borrow from previous stage) and two outputs Dn (difference) & Cn(borrow) Truth table: An Bn Cn-1 Sn(sum) Cn(carry) 0 0 0 0 0 0 0 1 1 0 0 1 0 1 0 0 1 1 0 1 1 0 0 1 0 1 0 1 0 1 1 1 0 0 1 1 1 1 1 1
- 6. Digital Technique Mrs. Sunita M Dol Page 6 Figure c: Full Subtractor-Difference
- 7. Digital Technique Mrs. Sunita M Dol Page 7 Figure d: Full Subtractor-Borrow PROCEDURE: 1. Check the components for their working. 2. Insert the appropriate IC into the IC base. 3. Make connections as shown in the circuit diagram. 4. Provide the input data via the input switches and observe the output on output LEDs 5. Give various combinations of inputs and note down the output with help of LED for all gate ICs one by one. RESULT: Thus we have designed full adder and full subtractor using 8:1 mux