Floorplanning is a critical part of the physical design process that determines the quality of the final design. Key aspects of floorplanning include macro placement and orientation, pad locations, power distribution, and standard cell placement. Good floorplanning avoids routing congestion and meets timing closure by considering pin locations, power networks, blockages, and cell placement regions. Macro placement should be optimized through flyline analysis to minimize interconnect lengths between blocks. Standard cells should be placed in homogeneous regions to improve routability.

1. Dashboard: November Issue
Floorplanning guidelines in Physical design
Floorplanning guidelines for
Physical design
- Vijay. I. Patel

2. Dashboard: November Issue
Floorplanning guidelines for Physical design
Floorplanning guidelines for Physical design
Floorplanning is a critical part in physical design. High-quality floorplanning of
complex hierarchical design ensures accurate circuit timing and performance.
Quality of floorplanning determines the quality of final designs. Poor floorplanning
may lead to problems like design failing to meet timing closure, routing
congestion, and high power dissipation, more area, huge IR-drops and signal
integrity issues.
Floorplanning involves decision on pin/pad location, hard macro placement,
placement and routing blockage, location and area of the soft macros and its pin
locations, number of power pads and its location.
Below mentioned tips will help in making correct floorplanning decisions
• While fixing the location of the pin or pad always consider the surrounding
environment with which the block or chip is interacting. This avoids routing
congestion and also benefits in effective circuit timing.
e.g. If a chip/block containing RX_DATA bus is going to sit on right hand side,
TX_DATA bus should also be placed on the right hand side of the chip/block.
• Provide sufficient number of power/ground pads on each side of the chip for
effective power distribution. In deciding the number of power/ground pads,
Power report and IR-drop in the design should also be considered.
• Proper macro placement is the essence for the performance of any design. A
design typically contains hundreds of hard macros varying from memory, PLL
and processors. Flyline analysis should be done while placing the macros.
This analysis gives a clear idea on interconnection with other macros and IO
pins. Orientation of these macros forms an important part of floorplanning.
Figure 1 compares two approaches of macro placement, the second one
being more desirable approach.
Figure 1: Approach in Macro placement

3. Dashboard: November Issue
Floorplanning guidelines for Physical design
• Avoid spreading standard cells in several areas and creating small placement
traps. Figure 2 shows floorplan with many pockets and isolated regions
between the macros that can trap a standard cell and limit the routing access.
A physical design engineer must focus on having homogeneous standard cell
area with aligned macros as shown in Figure3.
Figure 2 Figure 3
• Create standard cell placement blockage at the corner of the macro because
this part is more prone to routing congestion. Also create standard cell
placement blockage in long thin channel between macros.
• Avoid uneven routing resources in the design by using the proper aspect ratio
(Width /Height) of the chip. For example, considering a library with four routing
layers and that the standard-cell rails are in layer 1. This arrangement reduces
the horizontal routing resources to layer 3, while vertical routing resources are
available on layers 2 and 4. Lack of horizontal routing resources can lead to
congestion on layers 1 and 3. Greater width of the chip than its height,
compounds the problem.
• For designs that have horizontal overflow, to increase utilization, cell row
separation is increased which in turn helps increase horizontal routing
resources.
• In hierarchical design, Cluster based implementation enables to place the
standard cells of the given module in predefined region. Due which interacting
cells will be sitting in close proximity and thus will help in saving routing
resource. Also the length of the routes will be small which in turn reduce the
delay of the path.
• Design that have analog block and routing blockage are not defined in any
physical library, this creates routing blockage for all layers over the analog
block. Analog block are more susceptible to noise and signal routes going
over such block cause signal integrity issues.
Time and efforts that are put in floorplanning save iterations and make design
cycle faster.