analog electronics

1. Analog IC Design
BITS Pilani
Pilani Campus ANU GUPTAp

2. BITS PilaniBITS Pilani
Pilani Campus
Analog Layout Techniques

3. Organisation
• Design rules, Schematic to layout, vice versa,
• cross-sectional diagram, big layouts
• Matched componentsp
 Over-etching errors
unit components designunit components design
design using non unit component
 Boundary condition matching Boundary condition matching
Common centroid layout, parasitic cap estimation
BITS Pilani, Pilani Campus

6. Scalable design rules-----same set can be used for next
tech generation by changing λ. Worst case values of
spacings, widths etc. are used , so can’t be an optimized
set. e. g. MOSIS design rulesg g
Absolute design rules----optimized set but same set can’t
be used for next tech gen. Entire new set is to be
created.
BITS Pilani, Pilani Campus

7. Tanner
BITS Pilani, Deemed to be University under Section 3 of UGC Act, 1956

8. 4 NAND GATES4 NAND GATES

9. CADENCE

10. MOS LAYOUT
λ
λ 2λ
2λ
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λ
5λ

12. BITS Pilani, Deemed to be University under Section 3 of UGC Act, 1956

13. Junction cap-
single transistorsingle transistor
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14. Other layouts of MOS
Annular transistor
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Elongated annular
transistor

15. BITS Pilani, Deemed to be University under Section 3 of UGC Act, 1956

16. Dense MOS layouts
metal1metal1
metal2
B t t i t
BITS Pilani, Deemed to be University under Section 3 of UGC Act, 1956
Waffle transistor Bent transistor
Compute w/L?

17. Circuit And Layout
BITS Pilani, Deemed to be University under Section 3 of UGC Act, 1956
Try more examples

18. How to reduce parasitic
capacitances?
Careful layout by junction sharing

19. CAPACITOR LAYOUTS
BITS Pilani, Deemed to be University under Section 3 of UGC Act, 1956

20. RESISTOR LAYOUT
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21. Matching Issues
Large device => many small unit devicesg y
Same boundary conditions for devices
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22. BITS Pilani, Deemed to be University under Section 3 of UGC Act, 1956

23. BITS Pilani, Deemed to be University under Section 3 of UGC Act, 1956

24. Overetching –
MOS dimensions
(W/L)u = 8um/2um= 4 desired
MOS dimensions
After over etching ---
(W/L)u = 7um/1um= 7; 0.5um= ∆e
LL
∆e
Poly layer
w Over etched Poly layer
BITS Pilani, Pilani Campus

25. Absolute dimension of MOS
Remedy---use Unit components w=L
(W/L)u = 10um/10um, RATIO=1
Remedy---use Unit components w=L
After fab. (W/L)u  8um/8um, RATIO=1
Conclusion—Abs. dimensions change, ratio does not
changechange
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26. Ratio of matched devices
• (W/L)1 = 2, (W/L)2 = 8, ratio= 4
Ratio of matched devices
( )1 , ( )2 ,
• We take unit device (W/L)u = 10um/10um
• After fab. (W/L)u  8um/8um( )u
(W/L)2 8(W/L)u
4
( )2 ( )u
(W/L)1 2(W/L)u
= =4
Thus, ratio remains same, if same unit
device is used

27. Application of technique
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28. BITS PilaniBITS Pilani
Pilani Campus
Layout of CAPACITORSLayout of CAPACITORS

29. CAPACITOR LAYOUTS
BITS Pilani, Deemed to be University under Section 3 of UGC Act, 1956

31. Over-Etching
BITS Pilani, Deemed to be University under Section 3 of UGC Act, 1956

32. Let
C1/ C2 = 3.4 = 2+1.4
= [6/3] + [1.4/1][6/3] [1.4/1]
[6/3]---can be implemented by using unit[6/3]---can be implemented by using unit
capacitors
[1 4/1]---we require non unit capacitor[1.4/1]---we require non unit capacitor
Mismatch can occur due to second term
BITS Pilani, Pilani Campus

33. No mismatch conditionNo mismatch condition
• We should design non unit cap Such thatWe should design non unit cap. Such that
ratio (1.4) remains constant even after
overetchingoveretching
H t d i ?• How to design?
• What is the condition?

34. Condition
= c1
c2c
εr1= εr2
BITS Pilani, Deemed to be University under Section 3 of UGC Act, 1956

36. Non unit sized cap dim.
estimation
= 1 4
estimation
= 1.4
BITS Pilani, Deemed to be University under Section 3 of UGC Act, 1956

39. BITS PilaniBITS Pilani
Pilani Campus
Boundary condition matchingBoundary condition matching
Common centroid layout

40. What if unit devices change randomly?g y
Since one device is facing larger change in dimension,g g g
maintaining constant ratio would be difficult.
So We should have same change in all unit devices how?So, We should have same change in all unit devices. how?
Inter-digitization

42. BITS Pilani, Deemed to be University under Section 3 of UGC Act, 1956

43. BITS Pilani, Deemed to be University under Section 3 of UGC Act, 1956

44. Reduce mismatches
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45. BITS Pilani, Deemed to be University under Section 3 of UGC Act, 1956

46. BITS Pilani, Deemed to be University under Section 3 of UGC Act, 1956

47. BITS Pilani, Deemed to be University under Section 3 of UGC Act, 1956

48. D DD
S
SS
S S

50. Bulk (backgate contact)
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52. BITS Pilani, Deemed to be University under Section 3 of UGC Act, 1956

53. RESISTOR LAYOUT
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54. Big Resistor
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55. BIG RESISTOR (unit components)
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56. BITS Pilani, Deemed to be University under Section 3 of UGC Act, 1956

57. BITS Pilani, Deemed to be University under Section 3 of UGC Act, 1956

58. Multi fingered
Common Centroid layoutCommon Centroid layout
Parasitic cap. calculation of
MOS device
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59. 20λ 6λ 6λ 6λ
5λ 5λ
BITS Pilani, Deemed to be University under Section 3 of UGC Act, 1956

60. Fingered layout
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61. View of fingered layout
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62. BITS PilaniBITS Pilani
Pilani Campus
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