This document discusses analog integrated circuit layout techniques. It covers topics like design rules, unit component design, boundary condition matching using common centroid layout, and reducing mismatches. Specific circuit elements discussed include MOS transistors, capacitors, and resistors. Layout techniques to reduce parasitic capacitances and handle over-etching errors are presented. Fingered device layouts and calculating parasitic capacitances of MOS devices are also summarized.

1. Analog IC Design
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Pilani Campus ANU GUPTAp

2. BITS PilaniBITS Pilani
Pilani Campus
Analog Layout Techniques

3. Organisation
• Design rules, Schematic to layout, vice versa,
• cross-sectional diagram, big layouts
• Matched componentsp
 Over-etching errors
unit components designunit components design
design using non unit component
 Boundary condition matching Boundary condition matching
Common centroid layout, parasitic cap estimation
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6. Scalable design rules-----same set can be used for next
tech generation by changing λ. Worst case values of
spacings, widths etc. are used , so can’t be an optimized
set. e. g. MOSIS design rulesg g
Absolute design rules----optimized set but same set can’t
be used for next tech gen. Entire new set is to be
created.
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7. Tanner
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8. 4 NAND GATES4 NAND GATES

9. CADENCE

10. MOS LAYOUT
λ
λ 2λ
2λ
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λ
5λ

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13. Junction cap-
single transistorsingle transistor
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14. Other layouts of MOS
Annular transistor
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Elongated annular
transistor

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16. Dense MOS layouts
metal1metal1
metal2
B t t i t
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Waffle transistor Bent transistor
Compute w/L?

17. Circuit And Layout
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Try more examples

18. How to reduce parasitic
capacitances?
Careful layout by junction sharing

19. CAPACITOR LAYOUTS
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20. RESISTOR LAYOUT
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21. Matching Issues
Large device => many small unit devicesg y
Same boundary conditions for devices
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23. BITS Pilani, Deemed to be University under Section 3 of UGC Act, 1956

24. Overetching –
MOS dimensions
(W/L)u = 8um/2um= 4 desired
MOS dimensions
After over etching ---
(W/L)u = 7um/1um= 7; 0.5um= ∆e
LL
∆e
Poly layer
w Over etched Poly layer
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25. Absolute dimension of MOS
Remedy---use Unit components w=L
(W/L)u = 10um/10um, RATIO=1
Remedy---use Unit components w=L
After fab. (W/L)u  8um/8um, RATIO=1
Conclusion—Abs. dimensions change, ratio does not
changechange
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26. Ratio of matched devices
• (W/L)1 = 2, (W/L)2 = 8, ratio= 4
Ratio of matched devices
( )1 , ( )2 ,
• We take unit device (W/L)u = 10um/10um
• After fab. (W/L)u  8um/8um( )u
(W/L)2 8(W/L)u
4
( )2 ( )u
(W/L)1 2(W/L)u
= =4
Thus, ratio remains same, if same unit
device is used

27. Application of technique
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28. BITS PilaniBITS Pilani
Pilani Campus
Layout of CAPACITORSLayout of CAPACITORS

29. CAPACITOR LAYOUTS
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31. Over-Etching
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32. Let
C1/ C2 = 3.4 = 2+1.4
= [6/3] + [1.4/1][6/3] [1.4/1]
[6/3]---can be implemented by using unit[6/3]---can be implemented by using unit
capacitors
[1 4/1]---we require non unit capacitor[1.4/1]---we require non unit capacitor
Mismatch can occur due to second term
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33. No mismatch conditionNo mismatch condition
• We should design non unit cap Such thatWe should design non unit cap. Such that
ratio (1.4) remains constant even after
overetchingoveretching
H t d i ?• How to design?
• What is the condition?

34. Condition
= c1
c2c
εr1= εr2
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36. Non unit sized cap dim.
estimation
= 1 4
estimation
= 1.4
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39. BITS PilaniBITS Pilani
Pilani Campus
Boundary condition matchingBoundary condition matching
Common centroid layout

40. What if unit devices change randomly?g y
Since one device is facing larger change in dimension,g g g
maintaining constant ratio would be difficult.
So We should have same change in all unit devices how?So, We should have same change in all unit devices. how?
Inter-digitization

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44. Reduce mismatches
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47. BITS Pilani, Deemed to be University under Section 3 of UGC Act, 1956

48. D DD
S
SS
S S

50. Bulk (backgate contact)
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53. RESISTOR LAYOUT
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54. Big Resistor
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55. BIG RESISTOR (unit components)
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57. BITS Pilani, Deemed to be University under Section 3 of UGC Act, 1956

58. Multi fingered
Common Centroid layoutCommon Centroid layout
Parasitic cap. calculation of
MOS device
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59. 20λ 6λ 6λ 6λ
5λ 5λ
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60. Fingered layout
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61. View of fingered layout
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62. BITS PilaniBITS Pilani
Pilani Campus
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