it is ieee based ppt used in vlsi technology or as an lectural presentation

1. VLSI TECHNOLOGY
PROJECT BY,
A.POOJA SHUKLA

2. INTRODUCTION TOPICS
Scaling
Moore’s Law
3D VLSI

3. The beginning
Microprocessors are essential to many of the productsMicroprocessors are essential to many of the products
we use every day such as TVs, cars, radios, homewe use every day such as TVs, cars, radios, home
appliances and of course, computers. Transistors areappliances and of course, computers. Transistors are
the main components of microprocessors.the main components of microprocessors.
At their most basic level, transistors may seemAt their most basic level, transistors may seem
simple. But their development actually required manysimple. But their development actually required many
years of painstaking research. Before transistors,years of painstaking research. Before transistors,
computers relied on slow, inefficient vacuum tubescomputers relied on slow, inefficient vacuum tubes
and mechanical switches to process information. Inand mechanical switches to process information. In
1958, engineers managed to put two transistors onto a1958, engineers managed to put two transistors onto a
Silicon crystal and create the first integrated circuit,Silicon crystal and create the first integrated circuit,
which subsequently led to the firstwhich subsequently led to the first
microprocessor.microprocessor.

4. Transistor Size
Scaling
MOSFET performance
improves as size is
decreased:
shorter switching time,
lower power
consumption.
2 orders of magnitude reduction in transistor size in 30 years.

5. Significant Breakthroughs
Transistor size: Intel’s research labs have recently shown the world’s smallest
transistor, with a gate length of 15nm. We continue to build smaller and smaller
transistors that are faster and faster. We've reduced the size from 70 nanometer to 30
nanometer to 20 nanometer, and now to 15 nanometer gates.
Manufacturing process: A new manufacturing process called 130 nanometer process
technology (a nanometer is a billionth of a meter) allows Intel today to manufacture
chips with circuitry so small it would take almost 1,000 of these "wires" placed side-
by-side to equal the width of a human hair. This new 130-nanometer process has
60nm gate-length transistors and six layers of copper interconnect. This process is
producing microprocessors today with millions of transistors and running at multi-
gigahertz clock speeds.
Wafer size: Wafers, which are round polished disks made of silicon, provide the base
on which chips are manufactured. Use a bigger wafer and you can reduce
manufacturing costs. Intel has begun using a 300 millimeter (about 12 inches)
diameter silicon wafer size, up from the previous wafer size of 200mm (about 8
inches).

6. Major Design Challenges
Microscopic issues
– ultra-high speeds
– power dissipation and
supply rail drop
– growing importance of
interconnect
– noise, crosstalk
– reliability,
manufacturability
– clock distribution
Macroscopic issues
– time-to-market
– design complexity
(millions of gates)
– high levels of
abstractions
– design for test
– reuse and IP,
portability
– systems on a chip
(SoC)
– tool interoperability
$360 M800800 MHz130 M Tr.0.132002
$160 M360600 MHz32 M Tr.0.181999
$120 M270500 MHz20 M Tr.0.251998
$90 M210400 MHz13 M Tr.0.351997
Staff CostsStaff SizeFrequencyComplexityTech.Year

7. Integrated Circuits
Digital logic is implemented using transistors in
integrated circuits containing many gates.
– small-scale integrated circuits (SSI) contain 10
gates or less
– medium-scale integrated circuits (MSI) contain 10-
100 gates
– large-scale integrated circuits (LSI) contain up to 104
gates
– very large-scale integrated circuits (VLSI) contain
>104
gates
Improvements in manufacturing lead to ever
smaller transistors allowing more per chip.
– >107
gates/chip now possible; doubles every 18

8. What are shown on previous diagrams cover only the so called front end‑What are shown on previous diagrams cover only the so called front end‑
processing fabrication steps that go towards forming the devices and‑processing fabrication steps that go towards forming the devices and‑
inter connections between these devices to produce the functioning IC's. The‑inter connections between these devices to produce the functioning IC's. The‑
end result are wafers each containing a regular array of the same IC chip orend result are wafers each containing a regular array of the same IC chip or
die. The wafer then has to be tested and the chips diced up and the good chipsdie. The wafer then has to be tested and the chips diced up and the good chips
mounted and wire bonded in different types of IC package and tested again‑mounted and wire bonded in different types of IC package and tested again‑
before being shipped out.before being shipped out.
From Howe, Sodini: Microelectronics:An
Integrated Approach, Prentice Hall

9. Moore’s Law
Gordon E. Moore - Chairman Emeritus of Intel Corporation
1965 - observed trends in industry - # of transistors on ICs vs.
release dates:
– Noticed number of transistors doubling with release of
each new IC generation
– release dates (separate generations) were all 18-24
months apart
Moore’s Law:
– The number of transistors on an integrated circuit will
double every 18 months
The level of integration of silicon technology as measured in terms of
number of devices per IC
This comes about in two ways – size reduction of the individual
devices and increase in the chip or dice size
As an indication of size reduction, it is interesting to note that feature
size was measured in mils (1/1000 inch, 1 mil = 25 mm) up to early
1970’s, whereas now all features are measured in mm’s (1 mm = 10-6
-4

10. • In 1965, Gordon Moore predicted that the number of transistors that can beIn 1965, Gordon Moore predicted that the number of transistors that can be
integrated on a die would double every 18 to 14 monthsintegrated on a die would double every 18 to 14 months
• i.e., grow exponentially with timei.e., grow exponentially with time
• Amazing visionary – million transistor/chip barrier was crossed in the 1980’s.Amazing visionary – million transistor/chip barrier was crossed in the 1980’s.
– 2300 transistors, 1 MHz clock (Intel 4004) - 19712300 transistors, 1 MHz clock (Intel 4004) - 1971
– 42 Million, 2 GHz clock (Intel P4) - 200142 Million, 2 GHz clock (Intel P4) - 2001
– 140 Million transistor (HP PA-8500)140 Million transistor (HP PA-8500)
Moore’s LawMoore’s Law
Source: Intel web page (www.intel.com)

11. Moore’s Law
From Intel’s 4040 (2300 transistors) to
Pentium II (7,500,000 transistors) and
beyond
Relative sizes of ICs in graph

12. Ever since the invention of integrated circuit, the smallest feature size has
been reducing every year. Currently (2002) the smallest feature size is about
0.13 micron. At the same time the number transistors per chip is increasing
due to feature size reduction and increase in chip area. Classic example is
the case of memory chips: Gordon Moore of Intel in early 1970s found that:
“density” (bits per chip) growing at the rate of four times in 3 to 4 years -
often referred to as Moore’s Law. In subsequent years, the pace slowed
down a bit, data density has doubled approximately every 18 months –
current definition of Moore’s Law.

13. Limits of Moore’s Law?
Growth expected until 30 nm gate length (currently: 180 nm)
– size halved every 18 mos. - reached in
2001 + 1.5 log2((180/30)2
) = 2009
– what then?
Paradigm shift needed in fabrication process

14. Technological Background of the
Moore’s Law
To accommodate this change, the size of the
silicon wafers on which the integrated circuits are
fabricated have also increased by a very significant
factor – from the 2 and 3 in diameter wafers to the
8 in (200 mm) and 12 in (300 mm) diameter wafers
The latest catch phrase in semiconductor
technology (as well as in other material science) is
nanotechnology – usually referring to GaAs devices
based on quantum mechanical phenomena
These devices have feature size (such as film
thickness, line width etc) measured in nanometres
or 10-9
metres

15. Recurring Costs
cost of die + cost of die test + costof packagingvariable cost =----------------------------------------------------------------
final test yield
cost of wafercost of die = -----------------------------------dies per wafer × die yield
π × (wafer diameter/2)2
π × wafer diameter
dies per wafer = ---------------------------------- −---------------------------
die area √ 2 × die area
die yield = (1 + (defects per unit area × die area)/α)-α

16. Yield Example
 Example
wafer size of 12 inches, die size of 2.5 cm2
, 1 defects/cm2
,
α = 3 (measure of manufacturing process complexity)
252 dies/wafer (remember, wafers round & dies square)
die yield of 16%
252 x 16% = only 40 dies/wafer die yield !
 Die cost is strong function of die area
 proportional to the third or fourth power of the die area

17. Intel 4004 Microprocessor

18. Intel Pentium (IV)
Microprocessor

19. Die Size Growth
4004
8008
8080
8085
8086
286
386
486 Pentium ® proc
P6
1
10
100
1970 1980 1990 2000 2010
Year
Diesize(mm)
~7% growth per year
~2X growth in 10 years
Die size grows by 14% to satisfy Moore’s LawDie size grows by 14% to satisfy Moore’s Law
Courtesy, Intel

20. Clock Frequency
Lead microprocessors frequency doubles every 2 yearsLead microprocessors frequency doubles every 2 years
P6
Pentium ® proc
486
386
2868086
8085
8080
8008
4004
0.1
1
10
100
1000
10000
1970 1980 1990 2000 2010
Year
Frequency(Mhz)
2X every 2 years
Courtesy, Intel

21. Examples of Cost Metrics (1994)
$4179%402961.5$15000.803Pentium
$27213%482561.6$17000.703Super
SPARC
$14919%532341.2$15000.703DEC
Alpha
$7327%661961.0$13000.803HP PA
7100
$5328%1151211.3$17000.804PowerPC
601
$1254%181811.0$12000.803486DX2
$471%360431.0$9000.902386DX
Die
cost
YieldDies/
wafer
Area
(mm2
)
Defects/
cm2
Wafer
cost
Line
width
Metal
layers
Chip

22. VLSI
Very Large Scale Integration
– design/manufacturing of extremely small,
complex circuitry using modified
semiconductor material
– integrated circuit (IC) may contain millions
of transistors, each a few µm in size
– applications wide ranging: most electronic
logic devices

23. Origins of VLSI
Much development motivated by WWII
need for improved electronics,
especially for radar
1940 - Russell Ohl (Bell Laboratories) -
first pn junction
1948 - Shockley, Bardeen, Brattain (Bell
Laboratories) - first transistor
– 1956 Nobel Physics Prize
Late 1950s - purification of Si advances
to acceptable levels for use in

24. Origins of VLSI (Cont.)
1959 - Jack St. Claire Kilby (Texas
Instruments) - first integrated circuit - 10
components on 9 mm2
1959 - Robert Norton Noyce (founder,
Fairchild Semiconductor) - improved
integrated circuit
1968 - Noyce, Gordon E. Moore found
Intel
1971 - Ted Hoff (Intel) - first
microprocessor (4004) - 2300

25. Three Dimensional VLSI
The fabrication of a single integrated circuit
whose functional parts (transistors, etc)
extend in three dimensions
The vertical orientation of several bare
integrated circuits in a single package

26. Advantages of 3D VLSI
Speed - the time required for a signal to travel between the functional
circuit blocks in a system (delay) reduced.
– Delay depends on resistance/capacitance of interconnections
– resistance proportional to interconnection length

27. Advantages of 3D VLSI
Noise - unwanted disturbances on a useful
signal
– reflection noise (varying impedance along interconnect)
– crosstalk noise (interference between interconnects)
– electromagnetic interference (EMI) (caused by current in
pins)
3D chips
– fewer, shorter interconnects
– fewer pins

28. Advantages of 3D VLSI
Power consumption
– power used charging an interconnect capacitance
» P = fCV2
– power dissipated through resistive material
» P = V2
/R
– capacitance/resistance proportional to length
– reduced interconnect lengths will reduce power

29. Advantages of 3D VLSI
Interconnect capacity (connectivity)
– more connections between chips
– increased functionality, ease of design

30. Advantages of 3D VLSI
Printed circuit board size/weight
– planar size of PCB reduced with negligible IC height increase
– weight reduction due to more circuitry per package/smaller PCBs
– estimated 40-50 times reduction in size/weight

31. 3D VLSI - Challenges and
Solutions
Challenge: Thermal management
– smaller packages
– increased circuit density
– increased power density
Solutions:
– circuit layout (design stage)
» high power sections uniformly distributed
– advancement in cooling techniques (heat pipes)

32. Influential Participants -
Industry
Mitsubishi, TI, Intel, CTS Microelectronics, Hitachi, Irvine Sensors,
others...
– high density memories
AT&T
– high density “multiprocessor”
Many other applications/participants

33. Three Dimensional VLSI
Moore’s Law approaching physical limit
Increased performance expected by market
Paradigm shift needed - 3D VLSI
– many advantages over 2D VLSI
– economic limitations of fabrication overhaul will
be overcome by market demand
Three Dimensional VLSI may be the savior
of Moore’s Law