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“We are just an advanced breed of monkeys on a
minor planet of a very average star. But we can
understand the Universe. That makes us something
very special.”
- Stephen Hawking.
FinFET Architecture Analysis and
Fabrication Mechanism
M.A.Qadeer
Department of Electronics
and Communication
Mahatma Gandhi Institute of
Technology
Sai Sujith
Seelam
Department of Electronics
and Communication
Mahatma Gandhi Institute of
Topics
 Introduction
 Why FinFET??????
 Evaluation and comparison of FinFET
technology.
 What are FinFET’s???
 Structure & Architecture Analysis
 Recent FinFET Development
 Fabrication Mechanism
 Advantages and Limitations of FinFET
circuit design tradeoff’s
 Applications of FinFET Technology
The term “FINFET”
describes a non-planar,
double gate transistor built
on an SOI substrate,
based on the single gate
transistor design.
The important
characteristics of FINFET is
that the conducting
channel is wrapped by a
thin Si “fin”, which forms
the body of the device.
The thickness of the fin
determines the effective
channel length of the
device.
To summarize, in FinFET due to dual gate
structure it has better controlling over
several short channel effect such as VT
roll off, DIBL, subthreshold swing, gate
direct tunnelling leakage and hot carrier
effects compare to the planner MOSFET
FinFET has higher integration density
compare to the planner MOSFET. Also
fabrication of the FinFET is easiest
[1] NTUEE SEMINAR CHUNG HSUN LI
[2]Yang kayo-Choi, Leland Chang, Pushkar Ranade, Jeong-Soo
Lee, Daewoo Ha, Siam Balasubramanian,
Aditya Agarwal, Mike Ameen, Tus-Jae King and Jeffrey Boor.
“FinFET Process Refinements for Improved for Mobility and Gate
Work Function Engineering,” pp. 259-262, in IEDM Tech., 2002.
[3] Jovanovich, T. Sligo, P. Biljanović, L.K. Naiver, “FinFET
technology for wide-channel devices with ultra-thin silicon body”.
[4] Bin Yu, Leland Chang*, Shelby Ahmed, Haiphong Wang, Scott
Bell, Chih-Yuh Yang, Cyrus Tabery,Chau Ho, Qi Xiang, Tzu-Jae
King*, Jeffrey Boor*, Chamming Hu*, Ming-Ren Lin, and David
Kyser, “FinFET Scaling to 10nm Gate Length,” IEEE-2002.
[5] Venkatnarayan Hariharan, 2005, “EEs801 Seminar report
FinFETs,” http://www.ee.iitb.ac.in
[6] Asif I. Khan and Muhammad K. Ashraf, “Study of Electron
Distribution of Undoped Ultra Thin Body Symmetric Double Gate
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Finfets

  • 1. “We are just an advanced breed of monkeys on a minor planet of a very average star. But we can understand the Universe. That makes us something very special.” - Stephen Hawking.
  • 2. FinFET Architecture Analysis and Fabrication Mechanism M.A.Qadeer Department of Electronics and Communication Mahatma Gandhi Institute of Technology Sai Sujith Seelam Department of Electronics and Communication Mahatma Gandhi Institute of
  • 3. Topics  Introduction  Why FinFET??????  Evaluation and comparison of FinFET technology.  What are FinFET’s???  Structure & Architecture Analysis  Recent FinFET Development  Fabrication Mechanism  Advantages and Limitations of FinFET circuit design tradeoff’s  Applications of FinFET Technology
  • 4. The term “FINFET” describes a non-planar, double gate transistor built on an SOI substrate, based on the single gate transistor design. The important characteristics of FINFET is that the conducting channel is wrapped by a thin Si “fin”, which forms the body of the device. The thickness of the fin determines the effective channel length of the device.
  • 5.
  • 6.
  • 7.
  • 8.
  • 9.
  • 10.
  • 11.
  • 12.
  • 13.
  • 14.
  • 15.
  • 16.
  • 17.
  • 18.
  • 19.
  • 20.
  • 21.
  • 22.
  • 23.
  • 24.
  • 25.
  • 26.
  • 27.
  • 28. To summarize, in FinFET due to dual gate structure it has better controlling over several short channel effect such as VT roll off, DIBL, subthreshold swing, gate direct tunnelling leakage and hot carrier effects compare to the planner MOSFET FinFET has higher integration density compare to the planner MOSFET. Also fabrication of the FinFET is easiest
  • 29. [1] NTUEE SEMINAR CHUNG HSUN LI [2]Yang kayo-Choi, Leland Chang, Pushkar Ranade, Jeong-Soo Lee, Daewoo Ha, Siam Balasubramanian, Aditya Agarwal, Mike Ameen, Tus-Jae King and Jeffrey Boor. “FinFET Process Refinements for Improved for Mobility and Gate Work Function Engineering,” pp. 259-262, in IEDM Tech., 2002. [3] Jovanovich, T. Sligo, P. Biljanović, L.K. Naiver, “FinFET technology for wide-channel devices with ultra-thin silicon body”. [4] Bin Yu, Leland Chang*, Shelby Ahmed, Haiphong Wang, Scott Bell, Chih-Yuh Yang, Cyrus Tabery,Chau Ho, Qi Xiang, Tzu-Jae King*, Jeffrey Boor*, Chamming Hu*, Ming-Ren Lin, and David Kyser, “FinFET Scaling to 10nm Gate Length,” IEEE-2002. [5] Venkatnarayan Hariharan, 2005, “EEs801 Seminar report FinFETs,” http://www.ee.iitb.ac.in [6] Asif I. Khan and Muhammad K. Ashraf, “Study of Electron Distribution of Undoped Ultra Thin Body Symmetric Double Gate

Editor's Notes

  1. The term “FINFET” describes a non-planar, double gate transistor built on an SOI substrate, based on the single gate transistor design. The important characteristics of FINFET is that the conducting channel is wrapped by a thin Si “fin”, which forms the body of the device. The thickness of the fin determines the effective channel length of the device. FINFET is a transistor design first developed by Chenming Hu and his colleagues at the University of California at Berkeley, which tries to overcome the worst types of SCE(Short Channel Effect). Originally, FINFET was developed for use on Silicon-On-Insulator(SOI). SOI FINFET with thick oxide on top of fin are called “Double-Gate” and those with thin oxide on top as well as on sides are called “Triple-Gate” FINFETs.