The document discusses techniques for achieving device matching in microelectronics, focusing on MOS transistors. It outlines methods to minimize voltage and current mismatches, factors affecting transistor matching such as device size, orientation, and thermal effects, and introduces the common centroid layout technique for effective matching. Additionally, it briefly covers electrostatic discharge (ESD) protection measures relevant to integrated circuits.

1. Presentation - 3
TALLINN UNIVERSITY OF TECHNOLOGY
Course : Communicative Electronics
Subject : Microelectronics (IED3030)
Harish Kumar Singh – 177319IVEM

2. Matching
Pair of device having same property
- Resistor Matching
- Capacitor Matching
- Bipolar Transistor Matching
- Diodes Matching
- MOS Transistor Matching

3. MOS Transistor Matching
Analog Circuits use Matched transistor ! Where?
• Differential pair want voltage matching
• Current mirrors want current matching
MOS transistor can be optimized either for
voltage matching or for current matching, but
not for both ! Why?

4. Voltage Matching
Consider M1 and M2 operate equal drain
current. Then possible voltage mismatch:
Offset Voltage:
Vt : difference between threshold voltages of two transistor
k : difference between two transistor transconductances
Vgst: effective gate voltage of first transistor
k2 : 2nd device transconductance
To minimize offset voltage:
- Use large W/l and low operating current
- Vgst < 0.1 volts preferable

5. Current matching
Mismatch between ID1 and ID2:
To minimize mismatch:
- Use Vgst > 0.3 volt

6. Geometric Effects on Matching
• Increased Gate Area minimizes impact of local
fluctuations
 Large transistors match more precisely.
• Longer channels reduce line width variations
and channel length modulation
 Long-channel transistors match more precisely.
• Gate Area, Oxide thickness, Channel length
modulation, Orientation.

7. • Threshold Voltage mismatch
Svt : Standard deviation of Vt
Cvt : Constant
Weff, Leff : Effective channel dimensions
• Transconductance Mismatch
As the area of device increase, mismatch with pair
reduce

8. Orientation
• Si wafer is under stress due to processing.
• The stress produces anisotropic effect on the carrier
mobility, etc.
• Different orientation cause different stress effect on
the transconductance
• Stress-induced mobility variation by several %
• For example, tilted wafer induce as much as 5% in
matching errors.

9. Contact Placement Effect on Matching
• Contacts in the active Gate region cause
mismatch in Vt !
• Reason : Metal silicide penetrate through gate
region and enter to oxide, alert the function of
gate electrode
• Solution: Gate contacts must be outside the
active region, on thick field-oxide.

10. Thermal Effects
• Current matching primly depends on
Transconductance matching.
• Transconducatance directly proportional to
carrier mobility, which exhibit large temperature
coefficient.
• Use of common-centroid layout technique to
over come this effect.
• Locating match component
equal distance from power
dissipating component
improve matching

11. Stress Effect
• The fabrication under high temperatures may
leave residual stresses in chip
• Packaging can cause stress in chip
• Different orientation have cause different stress
on device
• Solutions
 Keep critical matched devices in centre of chip or on
centerlines
 Avoid using corners for matched devices
 Use common-centroid layout technique

12. Common Centroid Technique
• We have to match two components A and B (
A and B can be anything like capacitor, resistor
or transistor). Lets split A and B into 4 small
components i.e. A1-A4 and B1-B4.
• Common centroid Technique: Placing
components such that bothcomponents have
same centroid.

13. Example of common centroid technique
(W/L)M1= 2(W/L)
An alternative approach of M1 M1 M2 M2 M1
M1

14. Checklist of Matching Techniques
• 1. Same dimensions
• 2. Same structure (do not match nFETs with
pFETs)
• 3. As large as possible
• 4. Close to one another
• 5. Same orientation
• 6. Laid out in a common-centroid arrangement
• 7. Surrounding circuits should be similar
• 8. Same temperature

15. Contact Placement for Matching
• Contacts shift relative to the device result in
device mismatch
• Example : Horseshoe layout for resistors cause
mismatch if contacts shift horizontally, one
resistor increases while the other decreases.

16. Buried Layer Shift
• The buried layer is diffused into the substrate
prior to the growing of the epitaxial layer.
• Due to anisotropic growth of the epi, alignment
marks shift.
• Solution:
 Higher temperatures to obtain more isotropic growth
 Lower deposition rates
 Lower pressure

17. Resistor Placement
• Base resistor in epi tube are influenced by adjacent
diffusions.
• R1 and R4 have isolation well next to them.
• R2 and R3 have other base resistor next to them,
provide symmetrical environment
• Value of R1 and R4 will mismatch to R3 and R4
• Use dummy resistor. R1 and R4 is dummy resistor for
R2 and R3

18. Tub Bias Affects Resistor Match
• Voltage of a resistor relative to its epi tub
influences resistance.
• Two resistor in same tub will mismatch if are
at different voltage.
• Example:

19. Contact Resistance Upsets Matching
• Contact resistance can upset resistor matching when
resistor values differ
R = Rd + 2Rc
• Contact resistance becomes significant when resistance
values are small
• Large resistor ratios, where one of the resistor values is
small, can be cause mismatch by contact resistance.
• Example : Consider R1 >> R2, resistor ratio is given by
If R1 >> Rc
Thee ratio depends on the contact resistance RC.

20. • Matching of large resistor ratios is improved
by composing the larger resistor from
segments of smaller resistor.
• Example: If R1 = N(Rd2 + 2Rc)
Resistor ration,
• The ratio equals 1/N, independent of the
contact resistance.

21. What is ESD

22. Electrostatic Discharge Protection
(ESD)
• The human body capacitance of 150 pF is
charged to 4 KV
• Oxide damage is becoming more of a concern
as gate oxide thickness and it breaks down at
a few tens of volts.
• Integrated circuits may have to pass the
human body model (HBM) test.

23. • ESD current is absorbed by a large
transistor triggered by a low voltage
zener. Zener capacitor speeds turn
on in response to fast ESD transients.
• The n-type deep buried layer and the p-type
isolation (iso) form a pn junction that breaks
down at about 12 V and can carry the large
ESD currents.

24. Aitäh