1. Special Assignment
Subjects:
- Digital VLSI Design
Topic:
“A four-bit comparator with a six-bit output Y(5:0). Bit 5 of Y is for "equals:' bit 4 is
for "not equal to," bit 3 is for "greater than," bit 2 is for "less than," bit 1 for "greater
than or equal to: ' and bit 0 for "less than or equal to." With minimum hardware
requirements.”
Department of Electrical Engineering
Electronics & Communication Engineering Program
Master of Technology - VLSI
Institute of Technology, Nirma University
Ahmedabad-382481
Prepared By,
Axay Patel (14MECV14)
Guided By,
Dr. Usha S Mehta
Prof. Vaishali Dhare

2. 1. Specification and Architecture definition
1.1 4-bit Magnitude Comparator:
Our aim is to minimize hardware area as much as possible. So first we derive two outputs,
equal and greater. Then others (lesser, greater or equal, not equal, less or equal) will be
derived using simple gate structure followed by those two outputs. This is explained below
Two 4-bit data
퐴 = 퐴3퐴2 퐴1퐴0, 퐵 = 퐵3퐵2퐵1퐵0
푋3 = 퐴3 푥푛표푟 퐵3
푋2 = 퐴2 푥푛표푟 퐵2
푋1 = 퐴1 푥푛표푟 퐵1
푋0 = 퐴0 푥푛표푟 퐵0
퐸푞푢푎푙 (퐸) = 푋3푋2푋1푋0
퐺푟푒푎푡푒푟 (퐺) = 퐴3 퐵3 ′
+ 푋3퐴2퐵2 ′
+ 푋3푋2퐴1퐵1 ′
+ 푋3푋2푋1퐴0퐵0 ′
퐺푟푒푎푡푒푟 (퐺) = 퐴3 퐵3 ′
+ 푋3(퐴2퐵2 ′
For lesser area we reduce the equation
+ 푋2(퐴1퐵1 ′
+ 푋1퐴0퐵0 ′
))
푁표푡 푒푞푢푎푙 (푁퐸) = 퐸̅
퐺푟푒푎푡푒푟 표푟 푒푞푢푎푙 (퐺퐸) = 퐺 + 퐸
퐿푒푠푠 (퐿) = ̅퐺̅̅퐸̅
퐿푒푠푠 표푟 푒푞푢푎푙 (퐿퐸) = 퐺̅

3. Output is in form of 6-bit,
 Y(5:0)={E,NE,G,L,GE,LE}
 For example, 1) A=0101 and B=0010 then 2) A=1010 and B=1010 then
Y=011010 Y=100011

4. 2. RTL Schematic

5. 3. Gate Level Schematic
Tool Used: DSCH 2.7f
Here we have tried to put all universal gates and NOT gate so we can easily implement all
gate into transistor level schematic.
So, area can be reduced.
We have equations
 푋3 = 퐴3 푥푛표푟 퐵3, 푋2 = 퐴2 푥푛표푟 퐵2, 푋1 = 퐴1 푥푛표푟 퐵1, 푋0 = 퐴0 푥푛표푟 퐵0
푋푛 = 퐴푛′
퐵푛′
+ 퐴푛 퐵푛 → 푋푛 = [(퐵푛′
+ 퐴푛 )′ + (퐴푛′
+ 퐵푛)′ ]′ -- NOR and NOT structure
 퐺푟푒푎푡푒푟 (퐺) = 퐴3 퐵3 ′
+ 푋3(퐴2퐵2 ′
+ 푋2(퐴1퐵1 ′
+ 푋1퐴0퐵0 ′
))
is manipulated as
′ ∙ [푋3 ∙ [푚2
G = [푚3
′ ∙ [푋2 ∙ [푚1
′ ∙ (푋1 ∙ 푚0)′ ]′ ]′ ]′]′ ]′ -- NAND and NOT structure
푤ℎ푒푟푒 푚3 = 퐴3 퐵3 ′
, 푚2 = 퐴2퐵2 ′
, 푚1 = 퐴1퐵1 ′
, 푚0 = 퐴0퐵0 ′
,
 E = 푋3푋2푋1푋0 -> E = ((푋3푋2푋1)′ + 푋0 ′
)′ --NAND ,NOR and NOT structure
(maximum 3 input NAND or NOR gate is used)
 퐿 = (퐺 + 퐸)′ -> GE = L’
 LE =G’

6. Verilog Code:
module comparator_4_bit(
A0,B0,B3,A3,A2,B2,B1,A1,
E,NE,G,LE,L,GE);
input A0,B0,B3,A3,A2,B2,B1,A1;
output E,NE,G,LE,L,GE;
nor or(w3,w1,A0);
not inv(w4,A0);
not inv(w1,B0);
nor or(w6,B0,w4);
nor or(w7,w3,w6);
nor or(w11,w9,w10);
nor or(w10,B3,w12);
not inv(NE,E);
not inv(w12,A3);
nor or(w9,w16,A3);
nor or(w19,w17,A2);
not inv(w20,A2);
not inv(w17,B2);
nor or(w22,B2,w20);
nor or(w23,w19,w22);
nor or(w27,w25,w26);
nor or(w26,B1,w28);
not inv(w29,B1);
not inv(w28,A1);
nor or(w25,w29,A1);
nand and(w31,w11,w23,w27);
nor or(E,w31,w32);
not inv(w32,w7);
not inv(w16,B3);
nand and(w33,w6,w27);
not inv(w34,w26);
not inv(w35,w22);
nand and(w36,w33,w34);
nand and(w37,w36,w23);
nand and(w38,w37,w35);
not inv(w39,w10);
nand and(w40,w38,w11);
nand and(G,w40,w39);
not inv(LE,G);
nor or(L,E,G);
not inv(GE,L);
endmodule
TOTAL Transistor used: 116 transistors

7. 4. Transistor level schematic for each gate
Total Transistor calculated = 112 transistors (including nmos and pmos)

8. Verilog Code:
module Transistor Scm_comp(
B0,A3,B3,B2,A2,A1,B1,A0,
NE,LE,G,E,L,GE);
input B0,A3,B3,B2,A2,A1,B1,A0;
output NE,LE,G,E,L,GE;
nmos nmos(E,vss,NE); // 1.0u 0.12u
pmos pmos(w4,vdd,A0); // 2.0u 0.12u
pmos pmos(w6,vdd,w5); // 2.0u 0.12u
pmos pmos(w8,w6,w7); // 2.0u 0.12u
nmos nmos(w8,vss,w5); // 1.0u 0.12u
nmos nmos(w8,vss,w7); // 1.0u 0.12u
nmos nmos(w5,vss,B0); // 1.0u 0.12u
nmos nmos(w5,vss,w4); // 1.0u 0.12u
pmos pmos(w5,w10,B0); // 2.0u 0.12u
pmos pmos(w10,vdd,w4); // 2.0u 0.12u
pmos pmos(w12,vdd,w11); // 2.0u 0.12u
pmos pmos(w7,w12,A0); // 2.0u 0.12u
nmos nmos(w7,vss,w11); // 1.0u 0.12u
nmos nmos(w7,vss,A0); // 1.0u 0.12u
nmos nmos(w11,vss,B0); // 1.0u 0.12u
pmos pmos(w11,vdd,B0); // 2.0u 0.12u
nmos nmos(w14,vss,A3); // 1.0u 0.12u
pmos pmos(w16,vdd,B3); // 2.0u 0.12u
nmos nmos(w16,vss,B3); // 1.0u 0.12u
nmos nmos(w17,vss,A3); // 1.0u 0.12u
nmos nmos(w17,vss,w16); // 1.0u 0.12u
pmos pmos(w17,w18,A3); // 2.0u 0.12u
pmos pmos(w18,vdd,w16); // 2.0u 0.12u
pmos pmos(w19,vdd,w14); // 2.0u 0.12u
pmos pmos(w20,w19,B3); // 2.0u 0.12u
nmos nmos(w20,vss,w14); // 1.0u 0.12u
nmos nmos(w20,vss,B3); // 1.0u 0.12u
nmos nmos(w21,vss,w17); // 1.0u 0.12u
nmos nmos(w21,vss,w20); // 1.0u 0.12u
pmos pmos(w21,w22,w17); // 2.0u
0.12u
pmos pmos(w22,vdd,w20); // 2.0u 0.12u
pmos pmos(w14,vdd,A3); // 2.0u 0.12u
pmos pmos(w24,vdd,A2); // 2.0u 0.12u
pmos pmos(w26,vdd,w25); // 2.0u 0.12u
pmos pmos(w28,w26,w27); // 2.0u
0.12u
nmos nmos(w28,vss,w25); // 1.0u 0.12u
nmos nmos(w28,vss,w27); // 1.0u 0.12u
nmos nmos(w25,vss,B2); // 1.0u 0.12u
nmos nmos(w25,vss,w24); // 1.0u 0.12u
pmos pmos(w25,w30,B2); // 2.0u 0.12u
pmos pmos(w30,vdd,w24); // 2.0u 0.12u
pmos pmos(w32,vdd,w31); // 2.0u 0.12u
pmos pmos(w27,w32,A2); // 2.0u 0.12u
nmos nmos(w27,vss,w31); // 1.0u 0.12u
nmos nmos(w27,vss,A2); // 1.0u 0.12u
nmos nmos(w31,vss,B2); // 1.0u 0.12u
pmos pmos(w31,vdd,B2); // 2.0u 0.12u
nmos nmos(w24,vss,A2); // 1.0u 0.12u
nmos nmos(w34,vss,A1); // 1.0u 0.12u
pmos pmos(w36,vdd,B1); // 2.0u 0.12u
nmos nmos(w36,vss,B1); // 1.0u 0.12u
nmos nmos(w37,vss,A1); // 1.0u 0.12u
nmos nmos(w37,vss,w36); // 1.0u 0.12u
pmos pmos(w37,w38,A1); // 2.0u 0.12u
pmos pmos(w38,vdd,w36); // 2.0u 0.12u
pmos pmos(w39,vdd,w34); // 2.0u 0.12u
pmos pmos(w40,w39,B1); // 2.0u 0.12u
nmos nmos(w40,vss,w34); // 1.0u 0.12u
nmos nmos(w40,vss,B1); // 1.0u 0.12u
nmos nmos(w41,vss,w37); // 1.0u 0.12u
nmos nmos(w41,vss,w40); // 1.0u 0.12u
pmos pmos(w41,w42,w37); // 2.0u
0.12u
pmos pmos(w42,vdd,w40); // 2.0u 0.12u
pmos pmos(w34,vdd,A1); // 2.0u 0.12u
nmos nmos(w4,vss,A0); // 1.0u 0.12u
pmos pmos(NE,vdd,w41); // 2.0u 0.12u
pmos pmos(NE,vdd,w28); // 2.0u 0.12u
pmos pmos(NE,vdd,w8); // 2.0u 0.12u
pmos pmos(NE,vdd,w21); // 2.0u 0.12u
nmos nmos(w43,vss,w8); // 1.0u 0.12u
nmos nmos(w44,w43,w41); // 1.0u
0.12u
nmos nmos(w45,w44,w28); // 1.0u
0.12u
nmos nmos(NE,w45,w21); // 1.0u 0.12u
pmos pmos(E,vdd,NE); // 2.0u 0.12u
nmos nmos(w46,vss,w8); // 1.0u 0.12u
nmos nmos(w47,w46,w5); // 1.0u 0.12u
pmos pmos(w47,vdd,w5); // 2.0u 0.12u
pmos pmos(w47,vdd,w8); // 2.0u 0.12u
nmos nmos(w48,vss,w20); // 1.0u 0.12u
pmos pmos(w48,vdd,w20); // 2.0u 0.12u
nmos nmos(w49,vss,w25); // 1.0u 0.12u
pmos pmos(w49,vdd,w25); // 2.0u 0.12u
nmos nmos(w50,vss,w40); // 1.0u 0.12u
pmos pmos(w50,vdd,w40); // 2.0u 0.12u

9. pmos pmos(LE,vdd,G); // 2.0u 0.12u
pmos pmos(w53,vdd,w47); // 2.0u 0.12u
pmos pmos(w53,vdd,w50); // 2.0u 0.12u
nmos nmos(w53,w54,w50); // 1.0u
0.12u
nmos nmos(w54,vss,w47); // 1.0u 0.12u
nmos nmos(w56,vss,w55); // 1.0u 0.12u
nmos nmos(G,w56,w48); // 1.0u 0.12u
pmos pmos(G,vdd,w48); // 2.0u 0.12u
pmos pmos(G,vdd,w55); // 2.0u 0.12u
pmos pmos(w57,vdd,w28); // 2.0u 0.12u
pmos pmos(w57,vdd,w53); // 2.0u 0.12u
nmos nmos(w57,w58,w53); // 1.0u
0.12u
nmos nmos(w58,vss,w28); // 1.0u 0.12u
nmos nmos(w59,vss,w57); // 1.0u 0.12u
nmos nmos(w60,w59,w49); // 1.0u
0.12u
pmos pmos(w60,vdd,w49); // 2.0u 0.12u
pmos pmos(w60,vdd,w57); // 2.0u 0.12u
pmos pmos(w55,vdd,w60); // 2.0u 0.12u
pmos pmos(w55,vdd,w21); // 2.0u 0.12u
nmos nmos(w55,w61,w21); // 1.0u
0.12u
nmos nmos(w61,vss,w60); // 1.0u 0.12u
nmos nmos(GE,vss,L); // 1.0u 0.12u
pmos pmos(GE,vdd,L); // 2.0u 0.12u
nmos nmos(LE,vss,G); // 1.0u 0.12u
pmos pmos(w64,vdd,E); // 2.0u 0.12u
pmos pmos(L,w64,G); // 2.0u 0.12u
nmos nmos(L,vss,E); // 1.0u 0.12u
nmos nmos(L,vss,G); // 1.0u 0.12u
endmodule
As we can see that if we implement transistor level schematic using switch level coding
in micro-wind, it increases wiring costs. Very less numbers of transistors are reduced.
So we will prefer previous layout style.

10. 5. W/L ratio of transistor
Technology used: 0.12 micron
For pMOS W=2 micron
L=0.12 micron
W/L = 2/0.12 = 16.67
For nMOS W=1 micron
L= 0.12 micron
W/L = 1/0.12 = 8.34

12. Stick Diagram:
 Transistor level schematic of above module

13. Here we need to design fully combinational circuit and moreover hardware should be
minimized. For combinational circuit we have 8 inputs and 6 non registered outputs. So we
can use PROM or PLA or PAL.
1) PROM: Programmable read only memory
In PROM, decoder is followed by programmable OR plane. So, unnecessary
hardware consumed in decoder as well as in programmable OR plane. So, this is not
suitable choice for design.
2) PLA: Programmable Logic Array
PLA consist two programmable arrays. One is OR plane and second is AND plane.
Here we need three output (G, E, and GE) should be fed back to the input. This
facility is not easily available with PLA structure. If we use PLA structure we need to
implement all equation separately and it consumes more hardware. So PLA would
not be suitable choice for our design.
3) PAL: Programmable Array Logic
PAL is having one programmable AND plane and fixed OR plane.
We know that PAL could be our suitable choice. Now we will find particular device
in PAL.
 We need three output fed back to input.
 8 input
 6 output
So we can use PLA 22CEV10 for our design.
Now our aim is implement this design on FPGA kit. We will use SPARTAN 3E starter board
for our design.
Xilinx XC3S500E Spartan-3E FPGA
• Up to 232 user-I/O pins
• 320-pin FBGA package
• Over 10,000 logic cells

14. • Xilinx 4 Mbit Platform Flash configuration PROM
6. Synthesis
============================================================
* Design Summary *
============================================================
Top Level Output File Name : magnitude_comparator.ngc
Primitive and Black Box Usage:
------------------------------
# BELS : 9
# LUT4 : 3
# LUT5 : 4
# LUT6 : 2
# IO Buffers : 14
# IBUF : 8
# OBUF : 6
Device utilization summary:
---------------------------
Selected Device : 6slx45csg324-3
Slice Logic Utilization:
Number of Slice LUTs: 9 out of 27288 0%
Number used as Logic: 9 out of 27288 0%
Slice Logic Distribution:

15. Number of LUT Flip Flop pairs used: 9
Number with an unused Flip Flop: 9 out of 9 100%
Number with an unused LUT: 0 out of 9 0%
Number of fully used LUT-FF pairs: 0 out of 9 0%
Number of unique control sets: 0
IO Utilization:
Number of IOs: 14
Number of bonded IOBs: 14 out of 218 6%
6.1 Synthesis Report

16. 7. Technology Schematic

17. 8. RTL Schematic

18. 7.1 Basic difference between two schematics
RTL View
Viewing an RTL schematic opens an NGR file that can be viewed as a gate-level schematic.
This schematic is generated after the HDL synthesis phase of the synthesis process. It
shows a representation of the pre-optimized design in terms of generic symbols, such as
adders, multipliers, counters, AND gates, and OR gates, that are independent of the targeted
Xilinx device.
Technology View
Viewing a Technology schematic opens an NGC file that can be viewed as an architecture-specific
schematic.
This schematic is generated after the optimization and technology targeting phase of the
synthesis process. It shows a representation of the design in terms of logic elements
optimized to the target Xilinx device or "technology"; for example, in terms of of LUTs,
carry logic, I/O buffers, and other technology-specific components. Viewing this schematic
allows you to see a technology-level representation of your HDL optimized for a specific
Xilinx architecture, which might help you discover design issues early in the design
process.
9. Test Bench

19. module comp_stm;
// Inputs
reg [3:0] A;
reg [3:0] B;
// Outputs
wire [5:0] Y;
// Instantiate the Unit Under Test (UUT)
magnitude_comparator uut (
.A(A),
.B(B),
.Y(Y)
);
initial begin
// Initialize Inputs
A = 0;
B = 0;
// Wait 100 ns for global reset to finish
#100
A=4'b0101;
B=4'b0011;
#10
A=4'b1111;
B=4'b1111;
#10
A=4'b0001;
B=4'b0010;
end
endmodule

20. 8.1 Post PNR Simulation
Data Sheet report:
-----------------
All values displayed in nanoseconds (ns)
Pad to Pad
---------------+---------------+---------+
Source Pad |Destination Pad| Delay |
---------------+---------------+---------+
A<0> |Y<0> | 7.936|
A<0> |Y<1> | 8.506|
A<0> |Y<2> | 8.047|
A<0> |Y<3> | 8.173|
A<0> |Y<4> | 7.661|
A<0> |Y<5> | 7.794|
A<1> |Y<0> | 7.803|
A<1> |Y<1> | 8.366|
A<1> |Y<2> | 7.907|
A<1> |Y<3> | 8.040|
A<1> |Y<4> | 7.521|
A<1> |Y<5> | 7.654|
A<2> |Y<0> | 7.356|
A<2> |Y<1> | 8.667|
A<2> |Y<2> | 8.208|
A<2> |Y<3> | 7.593|
A<2> |Y<4> | 7.643|
A<2> |Y<5> | 7.955|
A<3> |Y<0> | 7.111|
A<3> |Y<1> | 8.791|
A<3> |Y<2> | 8.332|
A<3> |Y<3> | 7.353|
A<3> |Y<4> | 7.767|
A<3> |Y<5> | 8.079|
B<0> |Y<0> | 8.081|
B<0> |Y<1> | 8.619|
B<0> |Y<2> | 8.127|
B<0> |Y<3> | 8.318|
B<0> |Y<4> | 7.741|
B<0> |Y<5> | 7.874|
B<1> |Y<0> | 8.005|
B<1> |Y<1> | 8.543|
B<1> |Y<2> | 8.078|
B<1> |Y<3> | 8.242|

21. B<1> |Y<4> | 7.692|
B<1> |Y<5> | 7.825|
B<2> |Y<0> | 7.091|
B<2> |Y<1> | 8.566|
B<2> |Y<2> | 8.107|
B<2> |Y<3> | 7.328|
B<2> |Y<4> | 7.542|
B<2> |Y<5> | 7.854|
B<3> |Y<0> | 6.033|
B<3> |Y<1> | 8.296|
B<3> |Y<2> | 7.837|
B<3> |Y<3> | 6.862|
B<3> |Y<4> | 7.272|
B<3> |Y<5> | 7.584|
---------------+---------------+---------+
Analysis completed Wed Oct 29 11:08:49 2014