Phase-locked Loops - Theory and Design

Phase Locked Loops
Theory and Design
Chien-Jung Li
Department of Electronic Engineering
National Taipei University of Technology

Outline
• Frequency Synthesis Techniques
• Frequency Synthesizers based on the
Phase-Locked-Loop (PLL)
• Loop Analysis and Stability
• Components in a PLL
• Noise Analysis
• PLL Architectures
• Simulation Examples
Department of Electronic Engineering, NTUT2/140

Generic Transceiver Front End
Bandpass Filter
LNA
Duplexer
Antenna
v
Frequency
Synthesizer
LO
PA
• Local oscillator (LO) provides the carrier signal for both the receive
and transmit paths.
• If the LO output contains phase noise, both downconverted and
upconverted signals are corrupted.

Effect of Phase Noise in Receivers
f
0f
Wanted Signal
LO Output
Wanted Signal
Downconverted
Signal
f
Downconverted
Signals
ff
0f
Wanted Signal
LO Output Interferer
• Reciprocal Mixing

Effect of Phase Noise in Transmitters
f
1f
Wanted Signal
Nearby Transmitter
2f
f
0f
Multi-carrier signal (or OFDM)
f
0f
• Receiver Desensitization
• Orthogonality

Frequency Synthesis
 v t
t
• Meaning of frequency synthesis
Generation of a frequency or frequencies that are exact multiples of a
reference frequency. Usually the reference is very precise and the synthesized
frequencies are selectable over some range of whole-number multiples of a
submultiple of the frequency at
out ref
n
f f
M

where n and M are integers, n varies from Nmin to Nmax, and M is constant.
1T
1
1
f
 V f
f
1f
• Meaning of frequency
reff

Transformation to and from Voltage or Current
A B1f
Frequency
Discriminator

C D
d
dt
Voltage Controlled Oscillator
(VCO)
Phase Detector Phase Modulator
1 1v Af
2 1f Bv
  1 1f dt 2 1v C  2 2Dv
3 2
d
f
dt
V/Hz Hz/V
V/rad or V/cycle rad/V or cycle/V

Demonstration of the Transfer Functions
 
 
      
 
rms rms rms rms rms
1 rad 2 V rad rad 1
1 V 2 V 2 V V 0.32 V
V cycle cycle 2 rad
AV
Phase Modulator
1 rad/V
Phase Detector
2 V/Cycle
220 MHz VCO
1.5 MHz/V
1 k
200 MHz ICO
1 MHz/mA
100 MHz
signal
Low-pass Filter
50 MHz Cut-off
Frequency
Discriminator
5 V/MHz
A
B
D
• RMS voltage at point A:
Modulation voltage
(1 Vrms at 10 kHz)
   1 rms
MHz
0.32 V 1.5 0.48 MHz
V
f    

rms
2
0.32 V MHz
1 0.32 MHz
1 k mA
f
    rms
5 V
0.48 MHz-0.32 MHz 0.8 V
MHz
DV
C

Mathematical Operations on Frequency (I)
• Addition and Subtraction: The Mixer RF
LO
IF
   cos 2RF RF RFv t A f t  
         cos 2 cos 2IF RF LO RF RF LO LOv t v t v t A f t B f t        
For the practical mixer with nonlinear operation:
IF RF LOf mf nf 
   cos 2LO LO LOv t B f t  
        cos 2 cos 2
2
RF LO RF LO RF LO RF LO
AB
f f t f f t                  
      cos2 cos2 for 0
2
RF LO RF LO RF LO
AB
f f t f f t        
   , cosIF m nv t K m n   2 RF RFf t    2 LO LOf t   where and
or we can say the intermediate frequency is:

Mathematical Operations on Frequency (II)
• Frequency Dividers
 Subharmonically synchronized oscillators
 Digital dividers
• Frequency Multiplier
 Full-wave rectifier (frequency doubler)
 Harmonically tuned class-C amplifier
 Step-recovery diode (SRD)
1
powerG
N

10/140 Department of Electronic Engineering, NTUT

Frequency Synthesis Techniques
• Direct Analog Synthesis (DAS)
• Direct Digital Synthesis (DDS)
• Indirect Synthesis
- Phase-Locked Loops (PLLs)
• Hybrid DDS/PLL

Direct Analog Synthesis (DAS) I
• Frequency generated by mixed frequencies
1f
2f
3f
2Nf
1Nf
Nf
outf
filter1
filter2
filter3
filterN-2
filterN-1
filterN
out a bf mf nf 

Direct Analog Synthesis (DAS) II
• More stages are required for flexibly frequency planning.
1f
2f
3f
2Nf
1Nf
Nf
filter1
filter2
filter3
filterN-2
filterN-1
filterN
filter1
filter2
filter3
filterN-2
filterN-1
filterN
outf
1f 2f 3f 
 2Nf 
 1Nf Nf

Direct Digital Synthesis (DDS) I
• Waveform construction is based on the lookup table (LUT)
and a digital to analog converter (DAC)
• Direct synthesis
• Generated frequency is lower than input frequency
ref cf f

Direct Digital Synthesis (DDS) II
• Hardware technique to reduce the spur level of a DDS
• Reduce bandwidth
1000MHz
100-150MHz 1100-1150MHz 110-115MHz
div-by-10
DDS Filter
Frequency
Divider
0f
outf
BW=50MHz BW=15MHz
reff

Hybrid DDS/DAS
• Scheme to increase a DDS output bandwidth
1f 2f 3f 
 2Nf 
 1Nf Nf
outf
filter1
filter2
filter3
filterN-2
filterN-1
filterN
DDS
Frequency
Divider
reff

Indirect Frequency Synthesis (PLL) II
PFD LPF
Frequency Divider
reff outf
/N
• The main goal of the PLL is to sync the divided oscillator
frequency with the reference frequency outf N reff
 out reff N f out reff N f 
VCO

Fractional-N Frequency Synthesis
• Lower division ratio N to reduce inband phase-noise gain
• Effectively produce a fractional division value
• Generally employee a delta-sigma modulator for division ratio
dithering
PFD LPF
Dual-modulus
Frequency Divider
reff outf
/N, (N+1)
FCW

Principle of PLL Operation
vco
con
out reff f
• The main goal of the PLL is to sync the divided oscillator
signal with the reference signal (usually a pure sinusoid).

The Phase-Locked Loop
• PFD: Phase Frequency Detector
• LPF: Loop Filter
• VCO: Voltage Controlled Oscillator
PFD LPF
Frequency Divider
reff outf
/N
VCO
• /N: Divied-by-N Frequency Divider

Feedback System
 iV s  oV s  G s
 H s
error
         o i oV s V s V s H s G s   
         i oG s V s V s G s H s 
 
 
 
   1
o
i
V s G s
V s G s H s


Closed-loop
transfer function
G(s)H(s) is the
open-loop transfer function

Loop Analysis – Use Frequency as I/O
Frequency Divider
 reff s  outf s
1
s
pK  F s
vK
1
N
Phase differenceFrequency difference
 outf s
N
• Relation between Input and Output Frequencies
   p
v
K
G s F s K
s

 
1
H s
N

 
 
 
   
 
 
11
1
p
v
out
pref
v
K
F s Kf s G s s
Kf s G s H s
F s K
N s
 



Loop Analysis – Use Phase as I/O
Frequency Divider
 ref s  out s pK  F s
vK
s
1
N
• Relation between Input and Output Phases
Phase difference Frequency to Phase
    v
p
K
G s K F s
s

 
1
H s
N

 
 
 
   
 
 
11 1
v
p
out
vref
p
K
K F ss G s s
Ks G s H s K F s
N s


 
 

Loop Transfer Functions
 
 
 
 
 
 
   
0 0
0 01 1
p po
i p p
K F s K s K F s K G s
T s
K F s K Ns Ns K F s K G s H s


   
  
 T(s) : closed-loop PLL transfer function
 G(s) : forward-path transfer function
 F(s) : loop filter transfer function
 Kp: phase detector gain
 K0/s: VCO transfer function
   1 0G s H s 
• A PLL is unstable when
    1 0 dB@ 180G s H s      
The condition of unity open loop gain and a phase angle of 180 degrees must
be avoided.
 H(s) : feedback-path transfer function
 G(s)H(s) : open-loop transfer function
or

PLL Response without a Loop Filter (I)
  0 0
0 01
F
p LPFo
Fi p LPF
K
K K K s NT s N N
KK K K Ns ss
N
 
 
   
 
• 3 dB cutoff frequency is KF/N = KpKLPFKo/N
  LPFF s K
• Without the loop filter, the feedback loop is equivalent to a DC gain of
N plus a low-pass filter with cutoff at .0
log
dB
0
FK
N
  
20logN
3 dB
0

PLL Response without a Loop Filter (II)
• The open loop gain has a slope of -6dB/octave or -20dB/decade for
all frequencies.
• The phase angle is always -90 degrees at all frequencies. Hence
with no low-pass filter, the PLL is always stable. But the main
drawback is that designers loose control over the loop.
• The simplest PLL is called a type-I loop because the open-loop gain
has one pole at DC (pure integration). It is also a first-order loop
because the open-loop gain has one significant pole.
   
 p vK F s K
G s H s
Ns


Single Pole Loop Filter
• The function of the LPF is to filter out any high frequency harmonics in
the loop that might cause the loop to go out of lock, and also to
stabilize the loop.
• Adding a LPF also affects the loop response including parameters such
as the loop time response, bandwidth, and the damping factor.
 
 1
LPF
p
K
F s
s 


• If we add a low-pass filter with a pole located at , the loop will be
still type-I, but it will become a second-order loop.
   
1 1
p LPF v F
p p
K K K K
N NG s H s
s s
s s
 
 
   
       
   
p

Bode Plot of Forward-path Transfer Function
minL
log m
 mG 
6 dB/oct
1020log FK
10 max20log N
10 min20log N
maxL
p1m 
90 
135 
180 
 mG 
12 dB/oct
• Where the curves cross, the open-loop gain equals unity.
   
 
1
G s
G s H s
N
   G s N (forward-loop gain )

Bode Plot of Open-loop Transfer Function
log m
   m mG H 
6 dB/oct
1020log FK
N
0 dB
L
p1m 
90 
135 
180 
 mG 
12 dB/oct
• Where the curves cross, the open-loop gain equals unity.
   
 
1
G s
G s H s
N
   G s N (forward-loop gain )
Phase margin

Natural Frequency and Damping ratio
 
 
   
 
 
0
0
1
1 1 1 1
1
F
ppo F
Fi p
F
p
p
K
ss
K F s K sG s NK
T s
KG s H s K F s K Ns sNs K
sNs




 
 
     
          
 
0
F p
n p
K
N

   
0
1 1 1
2 2 2
p p
p
n F
N
K
 
 
 
  
is geometric mean of the loop bandwidth in the absence
of a filter and the filter corner frequency.
2
2 2 2 2
2 2 2
p F p F n
p F n n n n
p
K K
N
K s s s s
s s
N
  
    

  
   
 
Characteristics equation
• Prototype second-order equation
•Natural frequency
•Damping ratio

Closed-Loop Gain for Large Damping Ratio
As long as damping ratio is greater than one, the poles are real and a
tangential plot of closed loop gain looks
20logN
6 dB/oct
12 dB/oct
log m
 out
ref
f
s
f
2 2
0 2 1 1 1      
 
2
1 1 1
2
p
    
 
The characteristics are similar to the case with no loop filter, except for the
increasing rate of attenuation in fout/fref beyond approximately the filter
corner frequency .
2
1p n ns      • The poles of the closed-loop function are located at
0
p
p

Close-loop Responses
0
F p
n p
K
N

   
0
1 1 1
2 2 2
p p
p
n F
N
K
 
 
 
  
• As decreases toward , the damping ratio decreases and the phase shift
at increases. Correspondingly, the transient response of the loop becomes
less damped (more ringing) and the response peaks near .
p 0
0
n
m n  0m 
• For large damping, the response is similar to that for no filter but, as the
damping ratio decreases, the response peaks and the peak moves to a lower
frequency relative to .0

Relative Stability – Phase Margin
• Left figure shows the phase margin
(relative stability) as a function of the
damping factor. More highly damped
loops are safer, in that more
parameter variation is allowable
before instability occurs.
log m
   m mG H 
6 dB/oct
1020log FK
N
0 dB
L
p1m 
90 
135 
180 
 mG 
12 dB/oct
Phase margin
• With a single-pole low-pass filter, the
loop is inherently stable, sine -180o
phase shift cannot be attained for any
finite frequency. (not always true practically)

Transient Response
reff outf  G s
1 N
e
1N
2N
1 refN f
2 refN f
 2 1N N
e
1
2
1 ref
N
f
N
 
 
 
t
0t  t
oldf
newf
Synthesizer
output frequency
A
B
C
D
Overshot
Ringing • Lower damping ratio brings
a higher percent overshoot
can cause the loop to go
out of lock. (more unstable)
• Narrower bandwidth with
smaller damping ratio and
longer settling time.

Settling Time
• Settling Time
The frequency error changes one decade approximately each 2.3 time constant,
that is,
 
 0
02.3
log
f
T
f T



oldf
newf
 0f
0t  t T
 f T
• Example (no filter)
3 -1
1 MHz/cycle 10 secFK  
10 kHzreff 
11 MHz 10 MHzoutf  
Find the settling time for the output frequency of 10.1 MHz is attained.
6
0
10
1000
1000
FK
N
   
0
2.3 1
log 2.3 ms
0.1
T



A Pole-Zero Filter
• A pole-zero filter is a low pass filter with a pole frequency and a
zero frequency . The addition of a pole in the transfer function
causes the transfer function slope to drop at a rate of 6 dB per octave
whereas the addition of a zero in the PLL transfer function has the
opposite effect. The pole-zero filter transfer response is given by
 
 
 





1
1
z
p
s
F s
s
• The open loop transfer function is:
   
   
 
1
1
p v zp v
p
K K sK F s K
G s H s
Ns Ns s


   
  
p
z
6 dB/oct
12 dB/oct
log m
zp
6 dB/oct
• The closed-loop transfer function is:
 
 
 
0
01
po
i p
K F s K s
T s
K F s K Ns


 


Open-Loop Gain with a Pole-Zero LPF
• In this case, the location of the pole is always before the zero
frequency. Given the pole frequency location, a zero can be placed
after the so as to avoid the magnitude from crossing the unity gain
axis at a slope of 12 dB per octave, and therefore avoiding
instability. To determine the closed loop response, simply plot T(s),
 
 
2
1
1
p F
z
p F p F
p
z
K
s
NT s N
K K
s s
N N


 




 
   
 
0
F
n p p
K
N
    
1
2
p n
n z
 

 
 
  
 
6 dB/oct
12 dB/oct
log m
zp
6 dB/oct
 2
2 2
1
2
z
n
n n
s
N
s s


 


 

Open-Loop Gain with a Pole-Zero LPF
• From the results, selecting the pole frequency sets the natural
frequency (and subsequently the loop bandwidth) and selecting the
zero (based on the pole location in the open loop gain response)
determines the desired percentage overshoot. Therefore, a pole-zero
filter allows the designer to select the loop bandwidth and the
damping factor independently and still achieve stability.
0
F
n p p
K
N
    
1
2
p n
n z
 

 
 
  
 

Phase Detector (PD) – Mixer
 1 2cosd dv A   
2i i if   
 1 2coss sv A   
• The balanced mixer
IF d sv v v 
   1 2 1 1 2cos cos 4IF d sv A A f t        
1 2f fFor filtered-out by the LPF
 1 2 
2
 1 2
2

     
IF dv A    
and is very small
1 1 12 f   
2 2 22 f   
IFv
Phase of signal 1
Phase of signal 2

A B C
0 0 0
0 1 1
1 0 1
1 1 0
Phase Detector (PD) – EXOR
A
B
C
1
0
1
0
T

A
B
ppV C A B 
average
value
of
v(C)
ppV
1.0 0.5 0 0.5 1.0
T
• The exclusive-OR
1
0
1
0
T
A
B
ppV C A B 

Phase Detector (PD) – SR-FF
S
R
QA
B
C
T
Av
Bv
ppV

Cv
0 1 2
average
value
of
v(C)
T
ppV
A B C
0 0 N
0 1 0
1 0 1
1 1 X
• S-R Flip-Flops

Phase/Frequency Detector (PFD)
A lagging B ( same )
• Detectable range : -2π~ 2π
CLK
D
Q
CLR
Q
D
CLR
CLK
A
B
1
QA
QB
A
B
QA
QB
A BQ Q
2 4
24

 A leading B ( same )
A
B
QA
QB


Two General Types of PFD
T
t
ref(t)
div(t)
ref/2(t)
div/2(t)
e(t)
1
-1
• XOR-Based PFD
ref(t)
div(t)
up(t)
dn(t)
e(t)
1
0
-1 T
t
• Tri-state PFD

Typical Dead-Zone for Various PFDs
Type Dead Zone
Conventional ~800ps
NC-PFD ~160ps
TSPC-PFD ~210ps
MPTPFD ~10ps
• Commercial product Motorola MC4044 using conventional PFD
introduce 30 degree dead-zone@20MHz (~400ps).
• The first XOR-based dead-zone free design was proposed by Analog
Device (AD9901).
1f
2f
UP
UP
DN
DN

Dead-zone Problem of PFDs
• In a PLL, the contribution of every block is essential to the
total phase noise if a high-quality frequency synthesizer is
the goal.
• If the input frequency reference to be compared is as high as
several MHz, the linearity of the phase detector becomes
essential.
• In the passband of the PLL, the output phase noise depends
on noise contribution from the phase detector, loop filter and
frequency divider.
• In charge pump based PLL, there are more problems.

The Principle of PFD and Dead-Zone Problem
• The PFD operates as a frequency detector initially and as
phase detector finally to achieve loop lock.
• The dead-zone problem:
－ When two signals have the same frequency and almost identical
phase, the PFD block is not able to generate a proper output signal
so that an identical phase may be obtain.
－ This uncertainty leads to phase noise (jitter in time domain) and
generation of spurious at the output of VCO.
AND gate switch threshold
ref(t)
div(t)
up(t) dn(t)
1
0
1
0
ref(t)
div(t)
up(t)
1
0
1
0
dn(t)
ref(t)
div(t)
1
0
1
0
up(t)
dn(t)



Solve the Dead-Zone Problem
• Delayed reset path
• Inphase operation
• Need accurate timing analysis
• Low spurious tones
• Bad linearity
• Alternatively current output
• Non-inphase operation
• More power consumption at lock state
• Current mismatch with CP is the issue
• High spurious tones
• Good linearity
• XOR-Based PFD
• Tri-state PFD

Improvement of PFD Linearity
22
2 0
 0
22 0

Charge-Pump Phase Detector
• The most popular phase-detector type is both a charge-pump (CP)
detector and a phase-frequency detector (PFD), the terms, the
charge-pump PD and PFD, are sometimes interchangeably.
• The PFD acts as a phase detector during lock and provides a
frequency-sensitive signal to aid acquisition when the loop is out of
lock.
• The charge pump is so named because it is supposed to deliver a
charge proportional to phase error to the loop filter.
PFD
Charge
Pump
Switched Output
(analog)
Charge Up
Charge Down
CU (digital)
CD (digital)
RD
VD

Charge Pump PFD
PFD
AQ
BQ pC
DDV
A leading B ( same )
RD
VD
QA
QB

VCP
VCP
t
RD
VD

Charging Current
RD
VD
CU
CD
Current Out

Charge Pump (Current Source and Sink)
PFD
AQ
BQ
DDV
RD
VD
LZ
oV
DDV
R
1M 2M
1
1
W
L
2
2
W
L
2D oI I1DI
GSV
oV
sink current
 
21
1
2
DD GS
D GS thn
V V
I V V
R
 
  
 
22
2
2
D GS thnI V V

 
2 2 2 2 2
1 1 1 1 1
D
D
I W L W
I W L W


  
DDV
R
1M 2M1
1
W
L
2
2
W
L
2D oI I
1DI
SGV
oV
source current
 
2
1
1
2
DD SG
D SG thp
V V
I V V
R
 
  
 
2
2
2
2
D SG thpI V V

 
2 2 2 2 2
1 1 1 1 1
D
D
I W L W
I W L W


  
• Saturation region:
DS GS thnV V V 
GS thnV V
• Saturation region:
SD SG thpV V V 
SG thpV V

Early Effect
DDV
R
1M 2M
1
1
W
L
2
2
W
L
2D oI I1DI
GSV
oV
sink current
   22
2 ,1
2
D GS thn DS DS satI V V V V

     
1
L
 
• Channel length modulation and Early effect
DI
DS oV V
(prefer a long channel length)
2
1 1A
o
D o D
V
r
I I I 
   (prefer a high output resistance)

Cascode Connection and Switch
 3 3 2 21o o m o oR r g r r  
DI
DS oV V
• Cascode connection increases
output resistance
PFD
AQ
BQ
DDV
RD
VD
LZ
oV
DDV
R
1M 2M
1
1
W
L
2
2
W
L
2D oI I1DI
GSV
oV
sink current
BQ
switch
3M
2 thnV V 
• Need excess gate-source
voltage V
BQ is a digital signal (0~VDD)
thnV
Cascoded (with switch)

Current Mismatch
DI
DS oV V

Spurs and CP Non-ideal Effect
tsource
toff
tsink
Isink
Isource
tcomp
• Reference Spurs
- current leakage
- current source mismatch
(a) current mismatch with different
output node voltage
(b) unequal switching time
• Non-reference Spurs
- crosstalk
(a) dual loop
(b) interferences
- non-crosstalk
(a) fractional spurs
(b) interferences
(c) dual loop references mixing
(d) prescaler miss counting

Charge-Pump Switching Time
• When the charge-pump(CP) based PLL is used, the CP is
also the bottle neck since the PFD can’t distinguish input
edges separated by less than the CP switching time.
CPI
CPI
PFD
PFD
CP
CP

Dead-Zone Elimination and Spurs
• In conventional PFD, the problem of the CP current sources mismatch
is amplified by the number of additional delays in the reset path.
ref(t)
div(t)
1
0
1
0
up(t)
dn(t)


ref(t)
div(t)
1
0
1
0
up(t) dn(t)


periodic output!
+ICP
-ICP

Dead-Zone Issues
• In charge pump based PLL, the dead-zone problem is not
only considered in PFD design but charge pump.
• As reference frequency goes higher, the dead-zone issue is
more serious, because the linearity highly depends on the
dead-zone.
• In charge pump design, it’s hard to achieve low power
consumption, fast current switching and perfect current
mismatch.

Frequency Divider
PFD LPFreff outf
/N
VCO
divf inf
 / 1M M 
Prescaler
P
S
inf
divf
Program counter
Swallow counter
Reset
Modulus control
Channel selection
•Pulse Swallow Frequency Divider
1
in
in
T
f
 1 inM T
 1 inS M T
  inP S MT
     1div in in inT S M T P S MT S PM T     
(1) Start with divided-by-(M+1)
Total counts of program counter = P cycles
(2) Change to divided-by-M
1
div
div
T
f

 
1 1
div in inf f f
S PM N
 

2, 8, 4 4 8 2 20M P S N       

Asynchronous Divider
J Q
K
C
J Q
K
C
J Q
K
C
1
1
1
1
1
1
inf
2
inf
4
inf
8
inf
inf
2inf
4inf
8inf
outf
inf
2inf
4inf
8inf
outf

Synchronous Divider (2 versions)
J Q
K
C
J Q
K
C
J Q
K
C
J Q
K
C
J Q
K
C
1
1
2inf 4inf
8inf
16inf
16inf

Spikes in Synchronous Divider
2inf
4inf
8inf
outf
2inf
4inf
8inf
outf
2inf late
8inf early
• Racing in synchronous divider producing output spikes

Synchronous Divider w/ Enable
J Q
K
C
J Q
K
C
J Q
K
C
J Q
K
C
J Q
K
C
J Q
K
C
1
1
J Q
K
C
J Q
K
C
J Q
K
C
J Q
K
C
J Q
K
C
J Q
K
C
1
1
•Parallel Enable
•Serial Enable

Direct Variable Frequency Divider

Type and Order of the Loop
Frequency Divider
 ref s  out s pK  F s
vK
s
1
N
 
 
   
 
 1
G s N s
T s
G s H s D s
 

• The simplest PLL is the type-I loop because the open-loop gain has
one pole at DC (pure integration). It is also a first-order loop because
the open-loop gain has one significant pole.
  1
1 0
n n
n nN s a s a s a
   
  1
1 0
m m
m mD s b s b s b
   
Order = m (m roots)
Type = n (n roots at DC)

Filter First-order Type 1
• First order, type I (no filter)
1R
iv ov
2R
L
log m0 dB
G
6 / .dB oct
2
1 2
o
LPF
i
v R
G
v R R
 

A
3R
iv
4R
ov
 A
4
3
o
LPF
i
v R
G
v R

   

Filter Second-order Type I
• Second order, type I (Lag-and-lead filter)
1R
iv ov
2R
1C
A
3R
iv
5R
ov
2C
4R
L
log m0 dB
G
12 / .dB oct
6 / .dB oct
zp





1
1
z
LPF
p
s
G
s
 
2 1
1
z
R C 1 2 1
1
p
R R C
 

1
1
z
LPF
p
s
G
s




 


4 5
2
4 5
1
z
R R
C
R R
 

 
5 2
1
p
R C

Filter Second-order Type 1
• Second order, type I (Lag filter)
1R
iv ov
2R 1C
L
log m0 dB
G
6 / .dB oct
p
12 / .dB oct
A
3R
iv
4R
ov
2C
 A



 
2
1 2
1
1
LPF
p
R
G
sR R

  


4
3
1
1
LPF
p
R
G
sR

 
  
 1 1 2
1 1 1
p
C R R
 
4 2
1
p
R C

Filter Second-order Type II
• Second order, type II (Integrator and lead filter)
L
log m0 dB
G
12 / .dB oct
6 / .dB oct
z
A
1R
iv
2R
ov
C
 A


  
1 1
1
1 z
LPF
s
G
R C s
 
2
1
z
R C

Filter Third-order Type II
• Third order, type II (Integrator plus lead-lag filter)
L
log m0 dB
G
12 / .dB oct
p
12 / .dB oct
6 / .dB oct
z
A
1R
iv
2R
ov
2C
1C
 A
A
3R
iV
4R
oV
3C
5R
4C A
1 1
1
1
1
z
LPF
p
s
G
R C s
s



  
 
  
 




  
 
   
3 3
1
1
1
z
LPF
p
s
G
R C s
s
 
 
2 1 2
1
z
R C C
 
2 2
1
p
R C
 
4 3
1
z
R C
 
5 4
1
p
R C

Filter Third-order Type II
• Third order, type I (imperfect integrator plus lead-lag filter)
L
log m0 dB
G
6 / .dB oct
 2p
12 / .dB oct
6 / .dB oct
z 1p
12 / .dB oct
A
1oA R
A
 A

Oscillator
• Oscillator provides a sinusoidal signal
 v t
t
1
1
f
 V f
f
1f
 v t
t
1
1
f
 V f
f
1f

Voltage Controlled Oscillator (VCO)
• VCO is an oscillator of which frequency is controlled by a
tuning voltage
• VCO is a simple FM modulator
vcof
tuneV
tuneV

VCO Sensitivity and Tuning Linearity
• Frequency Range
• Frequency tuning characteristics
- Sensitivity (Hz/Volt)
- Linearity
VK f V  
vcof
tunev
,0tv
0f
maxf
minf
,mintv ,maxtv
v
f
Ideal (perfect)
Piecewise good
Piecewise good
Poor

Important Figures
• Output Power (@50 Ohm)
• Frequency Stability: frequency drifting
• Pushing and Pulling Figures
• Harmonics
• Phase Noise (Jitter)

Phase Noise and Jitter
 
   1 Hz
10log 10log dBc Hz
2
noise
carrier
S fP
L f
P
 
  
• Phase Noise
• Jitter
 Cycle jitter
cn nT T T    
2
1
1
lim
N
c cn
n
n
T
N



 
 Cycle-to-cycle jitter
1ccn n nT T T    
2
1
1
lim
N
c ccn
n
n
T
N



 
 Absolute jitter (long-term jitter, accumulated jitter) of N cycles
     
1 1
N N
abs n cn
n n
T N T T T
 
       
2
1
1
lim
N
c ccn
n
n
T
N



 
for white noise sources   0
2
abs cc
f
T t t    and 2cc c 

Relation of Phase Noise and Jitter
• Relationship between the SSB phase noise and the rms cycle jitter:
(Weigandt et al.)
 
 
3 2
0
2
cf
L f
f

 

• Relationship between the SSB phase noise and the rms cycle jitter:
(Herzel and Razavi)
 
 
   
3 2
0
22 3 4
0
4
8
cc
cc
L
  

   
 
 
• Self-referred jitter and phase noise with white noise:
(Demir et al.)
 
 
2
0
2 2 4 2
0
f c
L f
f f c
 
 
 2
t t c     20
2
cc
f
c 

Oscillator Design (I)
• Feedback : Barkhausen’s Criteria
 
 
( )
( )
1 ( ) ( )
o
f
i
V G s
G s
V G s H s
 ( ) ( ) 1G s H s (Phase is 0 deg. or multiple of 360 deg.)

Oscillator Design (II)
  '
11 1G S
  '
22 1L S
If the two-port network is oscillating at one port, it must be simultaneously
oscillating at the other port.
• Two Port Reflection
Sine the resonator is passive, thus 1G 

Oscillator Design (III)
0)()(   DRR
0)()(   DXX
• One-port Negative Resistance

Common Oscillator Configurations
bi
ci
C
E
B
1C
2C
3L
bi
ci
C
E
B
1L
2L
3C
bi
ci
C
E
B
1C
2C
3L
bi
ci
C
E
B
1C
2C
3L
Colpitts Hartley
Clapp Siler

Effects of Internal Noise Source
• The nonlinearities in the circuit cause K1 or K2 to have a value such
that the loop gain is unity, a condition for stable oscillation.
• The other condition is that there be 360o phase shift around the loop.
This occurs at the resonant frequency of the tank circuit.
2K
RC L1 2i K v

1v
nv
2v
• If no feedback, the noise will appear at the output, amplified by K2.

Small Noise Introduced
• But what effect does the feedback have?
(1) Far from spectral center: the output contains amplified circuit noise
(2) Close to spectral center: the feedback has an important effect


 
 
  
 
1
1 1
i
T
v
Z
i
j C
R L
Phase shift of this factor is
 

   
   
  
1 1
tanT R C
L
2K
RC L1 2i K v

1v
nv
2v

Tank Phase Shift
0 0
2Td Q
d 

 
 
Q is the loaded quality factor of the frequency-determining circuit.
• For modulation rates small compared to one-half of
the resonant bandwidth of ZT, a change in
frequency causes a phase change in the
transfer function, where the two changes are
2
osc
Q

   
0
1
0
0
1
tan 0T R C
L 
 



  
    
  

0
 
T
0
TH
1



Phase Perturbations
• The loop responds to a phase perturbation of by producing an
equal and opposite phase change to maintain the required zero phase
shift around the loop in the presence of modulation due to noise. This
is done by shift the frequency.
• A phase modulation with peak deviation due to noise vn
necessitates frequency modulation of the oscillator output with peak
deviation by

  
2
osc
n n
Q
n
n
0
T
n
n
n

Closed-Loop Noise

 
 

   2
2
oscn
n
m mQ
where is the noise modulation frequency.

2
osc
Q 
1
m
 n
 n
 2
• The phase noise would ordinarily appear at the output due to circuit
noise is accentuated by a factor . 2osc mf Qf
m
2
osc
m
f
f
Q

log mf
Open loop
Closed loop
logS
 2
rad Hz

Oscillator Phase Noise
f
0f mff 0
1 Hz
R
P
V avs
avsRMS 
R
FkT
VnRMS 11 Hz
R
FkT
VnRMS 2
• The input phase noise in a 1-Hz bandwidth at any frequency
from the carrier produces a phase deviation.
0 mf f
sP
nP

Noise

Noise Caused Phase Deviation
  1nRMS
peak
avsRMS avs
V FkT
V P
 1
1
2
RMS
avs
FkT
P
 RMS total
avs
FkT
P
Noise
 2
1
2
RMS
avs
FkT
P
(total phase deviation)
12 nRMSV
m
2 avsRMSV
0
 peak

Lesson’s Model (I)
avs
RMSm
P
FkTB
fS  2
)( 
1)(BdBm/Hz174 kTB
S
cf
mf
avsP
FkTB
1)(B1)( 






m
c
avs
m
f
f
P
FkTB
fS
• The spectral density of phase noise :
(theoretical noise floor of the amplifier)
• Flicker Noise
The purity of signal is degraded by the flicker noise at the frequencies close to
the carrier.
noise floor
flicker noise

Lesson’s Model (II)
)
2
(1
1
)(
0


loadm
m
Qj
L



in
Equivalent lowpass for
resonator
out
+
)( min f
)(
2
0
min
mL
f
Qj









• The oscillator may be modeled as an amplifier with feedback
0
1
( )
2
1
L m
L m
H
Q
j




 
  
 
0
2 2L
B
Q


0
( ) 1 ( )
2
out m in m
L m
f f
j Q

 

 
     
 
2
0
2
1
( ) 1 ( )
2
out m in m
m L
f
S f S f
f Q
 
  
    
   
( ) 1 c
in m
avs m
fFkTB
S f
P f

 
   
 
( )L mH

Lesson’s Model (III)
2
2
3 2 2
1 1
L( ) 1
2 4 2
o c o c
m
avs m L m L m
f f f fFkTB
f
P f Q f Q f
  
     
   
Up-convert 1/f
noise
Thermal FM
noise
Flicker noise
Thermal noise floor
• Lesson’s Oscillator Model:
slope
f
cf
f
1
Thermal Noise Floor
1/f noise at carrier
0f
C

  
    
   
2
0
2
1 1
L( ) 1 ( )
2 2
m in m
m L
f
f S f
f Q 
 
   
 
( ) 1 c
in m
avs m
fFkTB
S f
P f
Open-loop amp.Closed-loop with resonator

Lesson’s Model (IV)
1
mf
1
mf 0
mf
3
mf
1
mf
2
mf
3
mf
0
mf
cf
cf
cf
cf
Q
fo
2 Q
fo
2
avsP
FkTB
avsP
FkTB
2
avsP
FkTB
High Q Oscillator
Phase perturbation
Low Q Oscillator
Phase perturbation
Resulting phase noise Resulting phase noise

PLL Phase Noise Model
Frequency Divider
,ref n
out
1
N
PFD   LPF
,pfd nV ,op nV

,vco n

,div n
VCO
Xtal

Noise Transfer Functions (I)
 
      , , , , , ,out n pfd n op n ref n div n e vco n
d
T s
V V T s H s
K
       
 
 
   1
G s
T s
G s H s


 
   
1
1
eH s
G s H s


 
 
     
for
for1
c
c
NG s
T s
G sG s H s
 
 

  
 
 
   
 
for1
for1
1
c
e
c
N
G sH s
G s H s
 
 


  
 


Noise Transfer Functions (II)
c
log m
 
   1
G s
G s H s
N
 G s
Transfer function multiplying all sources except VCO
c
log m
   
1
1 G s H s
1
   
1
G s H s
Transfer function for VCO
c
log m
20logN
 G s
 dB
0

Typical VCO and PLL Noise Performance

PLL Design with Sheets
http://www.peregrine-semi.com

Phase-Locked Loop Architectures
• Integer-N PLL
• Fractional-N PLL
• Offset PLL
• DDS Offset PLL
• Dual Loop PLL
• Multi-Loop PLL

Offset PLL
out ref offsetf N f f  
?
PFD LPF
Frequency Divider
reff outf
/N
offsetf
• Extend bandwidth with different offsetf
• Avoid LO pulling

Dual-Loop PLL (I)
PFD LPF
Frequency Divider
reff outf
/N
offsetf
PFD LPF outf
/M
2nd loop

Dual-loop PLL (II)
PFD LPF
Frequency Divider
1reff
outf/N
1f
PFD LPF
2f
/M
2nd loop
2reff

Multi-Loop PLL
3rd loop
2nd loop
foffset1
PFD LPF
/N
foutVCOfref
PFD LPF
/M
VCO
foffset2
PFD LPF
/P
VCO
foffset3

DDS Offset PLL
PFD LPF
Frequency Divider
reff outf
/N
offsetf
DDS

Fractional-N Frequency Synthesis
• Effectively produce a fractional division value
• Generally employee a delta-sigma modulator for division
ratio dithering
PFD LPF
Dual-modulus
Frequency Divider
reff outf
/N, (N+1)
FCW

DDS-Driven Fractional-N Synthesizer
• DDS acts a reference source or phase/frequency modulator
• A variable reference frequency source can drive a fractional
frequency output.
PFD LPF
Frequency Divider
reff outf
/N
DDS
FCW
Hybrid DDS/PLL

DDS-Feedback Fractional-N Synthesizer
• DDS acts a frequency divider
• DDS output frequency
Hybrid DDS/PLL
PFD LPF
Frequency Divider
reff outf
DDS
FCW
2
out ref offsetn
M
f f f  

Comparison of Frequency Synthesizers
DDS
Single-Loop
PLL
Multi-Loop
PLL
DDS/DAS
DDS Offset
PLL
DDS Driven
PLL
BW
(output)
Narrow
< 100MHz
Broad
> 1GHz
Broad
> 1GHz
Broad
> DDS
Broad
(carefully
design)
Broad
Resolution
Extremely
Fine
< 0.02 Hz
Very Course
> 250kHz
(typical)
Medium
> 1kHz
(typical)
Extremely
Fine
< 0.01 Hz
Extremely
Fine
< 0.01 Hz
Extremely
Fine
< 1Hz
Switching
Time
Very Fast
< 100 ns
Fast
< 100us
(typical)
Very Slow
> 1ms
(typical)
Very Fast
< 1us
(limited by
RF switch)
Fast
< 100us
(typical)
Trade-off vs
close-in
spurious
tones
Spurious
Noise
< 75dBc
(limited by
DAC)
Very Good
Good
(carefully
design)
Minimum
Close-in
Spurious
Minimum
Close-in
Spurious
Excellent
over Broad
Bandwidth
Phase
Noise
Better than
clock
reference
Very Good Very Good Very Good Very Good Good
Circuitry Simple Simple Very Complex Moderate Moderate Moderate

PLL Simulation
• ADS Circuit Envelope Simulation Basics
• Integer-N Frequency Synthesizer Simulation
• Fractional-N Frequency Synthesizer Simulation
• Closed-In Phase Noise Characteristics

Circuit Envelope Simulation Technique
• Time samples the modulation envelope (not carrier)
• Compute the spectrum at each time sample
• Output a time-varying spectrum
• Use equations on the data
• Faster than HB or SPICE in many case
• Integrates with System Simulation & HP Ptolemy

What Test Can it Perform?
• Test circuits with realistic signals
Simulation can include:
• Adjacent Channel Power Ratio
• Noise Power Ratio
• Error Vector Magnitude
• Power Added Efficiency
• Bit Error Rate
Also, it can be used for PLL simulation:
• Locking time
• Spurious signal
• Modulation in the loop
• Phase noise
Features of Circuit Envelope Simulation

• Time sample the envelope and then perform Harmonic
Balance on the samples. V(t) can be complex – am, fm or
pm
Circuit Envelope Sampling

Spectrum Computation

Envelope
Env1
Step=1 nsec
Stop=100 nsec
Order[1]=3
Freq[1]=1.0 GHz
ENVELOPETime step
– Determines bandwidth of Circuit Envelope simulation
– Small enough to capture highest modulation frequency
Stop time
– Determines resolution bandwidth of output spectrum
– Large enough to resolve spectral components of interest
Frequency Span and Resolution Bandwidth

Vin Vout
Envelope
Env1
Step=1 nsec
Stop=50 nsec
Order[1]=1
Freq[1]=900 MHz
ENVELOPE
R
R1
R=50 Ohm
PtRF_Pulse
PORT1
Period=100 nsec
Width=30 nsec
Fall=10 nsec
Rise=5 nsec
Delay=0 nsec
OffRatio=0
Freq=900 MHz
P=dbmtow(0)
Z=50 Ohm
Num=1 Amplifier
AMP1
S12=0
S22=dbpolar(-50,0)
S11=dbpolar(-50,0)
S21=dbpolar(10,0)
Circuit Envelope Simulation Example (I)

m2
time=5.000nsec
real(Vout[1])=1.000
m1
time=0.0000 sec
real(Vout[1])=0.000
m2
time=5.000nsec
real(Vout[1])=1.000
m1
time=0.0000 sec
real(Vout[1])=0.000
10 20 30 400 50
-0.5
0.0
0.5
-1.0
1.0
time, nsec
real(Vin[1])
real(Vout[1])
m2
m1
ts(Vout),V
m2
time=5.000nsec
real(Vout[1])=1.000
m1
time=0.0000 sec
real(Vout[1])=0.000
m2
time=5.000nsec
real(Vout[1])=1.000
m1
time=0.0000 sec
real(Vout[1])=0.000
10 20 30 400 50
-0.5
0.0
0.5
-1.0
1.0
time, nsec
real(Vin[1])
real(Vout[1])
m2
m1
ts(Vout),V
m2
time=10.00nsec
real(Vout[1])=1.000
m1
time=0.0000 sec
real(Vout[1])=0.000
m2
time=10.00nsec
real(Vout[1])=1.000
m1
time=0.0000 sec
real(Vout[1])=0.000
10 20 30 400 50
-0.5
0.0
0.5
-1.0
1.0
time, nsec
real(Vin[1])
real(Vout[1])
m2
m1
ts(Vout),V
m2
time=0.0000 sec
real(Vout[1])=0.000
m1
time=0.0000 sec
real(Vout[1])=0.000
m2
time=0.0000 sec
real(Vout[1])=0.000
m1
time=0.0000 sec
real(Vout[1])=0.000
10 20 30 40 500 60
-0.5
0.0
0.5
-1.0
1.0
time, nsec
real(Vin[1])
real(Vout[1])
m2m1
ts(Vout),V
Circuit Envelope Simulation Example (II)
Tstep = 1 ns Tstep = 5 ns
Tstep = 10 ns Tstep = 20 ns

Integer-N Frequency Synthesizer

    0out ch reff f k f M f    0out ch reff f k f M f
For channel 1 (k=0)
  0out L reff f M f
   , 0,1,2, ,LM M k k N
ch reff fch reff f
Architecture of Integer-N Frequency Synthesizer
1 MHzreff 
0 2.4 GHzf 
2400N 

vtune
VCOfreq
VCOout
Envelope
Env1
Other=
Step=Tstep
Stop=4000*Tstep
SweepOffset=0
StatusLevel=2
Order[1]=1
Freq[1]=fvco
ENVELOPE
V_1Tone
SRC3
Freq=1 MHz
V=polar(1,-90) V
VAR
VAR1
Tstep=1/(5*fref)
DeltaN=(fvco+Deltaf)/fref -N0
Deltaf=0 MHz
N0=fvco/fref
fref=1 MHz
fvco=2.4 GHz
Eqn
Var VtStep
SRC4
Rise=1/fref
Delay=0 nsec
Vhigh=DeltaN V
Vlow=0 Vt
MeasEqn
meas2
VCOfreqGHz=real(VCOfreq[0])
VCOphase=phase(VCOout[1])
fund=VCOout[1]
Vtune=real(vtune[0])
Eqn
Meas
VCO_DivideByN
VCO1
Delay=0
Power=dbmtow(10)
Rout=50 Ohm
N=N0
F0=fvco
VCO_Freq=50 MHz * _v1
f r eq
VCO
.
vcon
- N.
VCO
t une
dN
C
C3
C=100 pF
R
R3
R=50 Ohm
R
R4
R=50 Ohm
ResetSwitch
SWITCH1
t>0
t=0
C
C2
C=16.4 nF
R
R1
R=3.3 kOhmC
C1
C=1 nF
R
R2
R=15 kOhmPhaseFreqDetCP
PFD1
Ilow=1 mA
Ihigh=1 mA
FREQ/CP
I low
I high
PHASE/
VCO
r ef
Schematic of Integer-N Frequency Synthesizer
PFD LPF VCO & Divider
Output load
Modulus
Divided signal

-2 -1 0 1 2-3 3
-100
-50
0
-150
50
freq, MHz
spectrum
Reference Spurs (I)
Reference spurs

Reference Spurs (II)
A
B
UP
DN
A
B
AQ
BQ
Gate Delay (comparison transition)

100 200 300 400 500 600 7000 800
2.3999995
2.4000000
2.4000005
2.3999990
2.4000010
time, usec
VCOfreqGHz
0 100
-0.000015
-0.000010
-0.000005
0.000000
0.000005
0.000010
-0.000020
0.000015
time, usec
Vtune
Improper LPF Design and Discrete Effect

m1
time=570.0000000usec
VCOfreqGHz=2.401000000
m1
100 200 300 400 5000 600
2.40
2.41
2.42
2.43
2.39
2.44
time, usec
VCOfreqGHz
m1
100 200 300 400 5000 600
0.0
0.2
0.4
0.6
-0.2
0.8
time, usec
Vtune
Eqn spectrum=dBm(fs(fund))
m2
freq=1000.kHz
spectrum=10.00
m2
freq=1000.kHz
spectrum=10.00
-2 -1 0 1 2-3 3
-150
-100
-50
0
-200
50
freq, MHz
spectrum
m2
VCO output spectrum at steady-state,
jump from fcenter at 2.4GHz to 2.401GHz
  1 MHzf
PLL Transient Response (I)

m1
m1
100 200 300 400 5000 600
2.41
2.42
2.43
2.40
2.44
time, usec
VCOfreqGHz
m1
100 200 300 400 5000 600
0.2
0.4
0.6
0.0
0.8
time, usec
Vtune
m1
m1
100 200 300 400 5000 600
2.42
2.44
2.46
2.48
2.40
2.50
time, usec
VCOfreqGHz
m1
100 200 300 400 5000 600
0.5
1.0
1.5
0.0
2.0
time, usec
Vtune
  10 MHzf   80 MHzf
PLL Transient Response (II)

Fractional-N Frequency Synthesizer

( 1) ( )A N M A N A
N
M M
    
 
( ) ( )out ref ref
A
f N f N f
M
     
Architecture of Fractional-N Frequency Synthesizer

deltaN
vtune
VCOfreq
VCOout
VAR
VAR1
Tstep=1/(5*fref)
Num=Denom*fraction
Denom=20
fraction=DeltaN-intDeltaN
intDeltaN=int(DeltaN)
DeltaN=(fvco+Deltaf)/fref -N0
Deltaf=0.75 MHz
N0=fvco/fref
fref=1 MHz
fvco=2.4 GHz
Eqn
Var
MeasEqn
meas2
VCOfreqGHz=real(VCOfreq[0])
VCOphase=phase(VCOout[1])
fund=VCOout[1]
Vtune=real(vtune[0])
Eqn
Meas
Envelope
Env1
Other=
Step=Tstep
Stop=4000*Tstep
SweepOffset=0*Tstep
StatusLevel=2
Order[1]=1
Freq[1]=fvco
ENVELOPE
C
C3
C=100 pF
R
R2
R=15 kOhm
R
R1
R=3.3 kOhm
C
C2
C=16.4 nF
V_1Tone
SRC3
Freq=1 MHz
V=polar(1,-90) V
VtPulse
SRC5
Period=Denom/fref
Width=Num/fref
Edge=linear
Delay=(Denom-Num)/fref
Vhigh=1 V
Vlow=0 V
t
PhaseFreqDetCP
PFD1
Ilow=1 mA
Ihigh=1 mA
FREQ/CP
I low
I high
PHASE/
VCO
ref
VCO_DivideByN
VCO1
Delay=0
Power=dbmtow(10)
Rout=50 Ohm
N=N0
F0=fvco
VCO_Freq=50 MHz * _v1
f r eq
VCO
.
vcon
- N.
VCO
t une
dN
C
C1
C=1 nF
R
R3
R=50 Ohm
R
R4
R=50 Ohm
ResetSwitch
SWITCH1
t>0
t=0
Schematic of Fractional-N Frequency Synthesizer

Denom (M)
Num (A)
VtPulse
SRC5
Period=Denom/fref
Width=Num/fref
Delay=(Denom-Num)/fref
Vhigh=1 V
Vlow=0 V
t
VCO_DivideByN
VCO1
freq
VCO
.
vcon
- N.
VCO
tune
dN
The Simulation Method

m1
time=227.000usec
VCOfreqGHz=2.40005
100 200 300 400 500 600 7000 800
2.40
2.41
2.42
2.39
2.43
time, usec
VCOfreqGHz
m1
 0.5 MHz 0.5 MHzreff f  
PLL Transient Response

m2
freq=100.0kHz
spectrum=-7.185
m1
freq=50.00kHz
spectrum=9.827
m3
freq=150.0kHz
spectrum=-28.277
m2
freq=100.0kHz
spectrum=-7.185
m1
freq=50.00kHz
spectrum=9.827
m3
freq=150.0kHz
spectrum=-28.277
-2 -1 0 1 2-3 3
-80
-60
-40
-20
0
-100
20
f req, MHz
spectrum
m2
m1
m3
100 200 300 400 500 600 7000 800
2.40004
2.40005
2.40006
2.40003
2.40007
time, usec
VCOfreqGHz
m2
freq=800.0
spectrum=
m1
freq=750.0
spectrum=
m3
freq=850.0
spectrum=
-2 -1 0 1 2-3 3
-60
-40
-20
0
-80
20
freq, MHz
spectrum
m2m1
m3
100 200 300 400 500 600 7000 800
2.40070
2.40075
2.40080
2.40065
2.40085
time, usec
VCOfreqGHz
Fractional Spurs

Closed-In Phase Noise Characteristics

m1
freq=10.00kHz
PN_Loop_Div_only=-87.846
m2
freq=100.0kHz
10.00 100.0 1.000k 10.00k 100.0k 1.000M1.000 10.00M
-240
-220
-200
-180
-160
-140
-120
-100
-80
-60
-260
-40
freq, Hz
PN_Loop_Div_only
m1
m2
m1
freq=10.00kHz
m2
freq=100.0kHz
10.00 100.0 1.000k 10.00k 100.0k 1.000M1.000 10.00M
-240
-220
-200
-180
-160
-140
-120
-100
-80
-60
-260
-40
freq, Hz
PN_Loop_Div_only
m1
m2
m1
freq=10.00kHz
m2
freq=100.0kHz
10.00 100.0 1.000k 10.00k 100.0k 1.000M1.000 10.00M
-240
-220
-200
-180
-160
-140
-120
-100
-80
-60
-260
-40
freq, Hz
PN_Loop_Div_only
m1
m2
(1)
(2) (3)
(1) Loop BW = 1 kHz
(2) Loop BW =10 kHz
(3) Loop BW =100 kHz
Phase Noise with Loop Divider Only

(1)
(2) (3)
(1) Loop BW = 1 kHz
(2) Loop BW =10 kHz
m1
freq=10.00kHz
PN_PFD_only=-79.177
m2
freq=100.0kHz
PN_PFD_only=-78.781
10.00 100.0 1.000k 10.00k 100.0k 1.000M1.000 10.00M
-220
-200
-180
-160
-140
-120
-100
-80
-240
-60
freq, Hz
PN_PFD_only
m1 m2
m1
freq=10.00kHz
PN_PFD_only=-103.531
m2
freq=100.0kHz
10.00 100.0 1.000k 10.00k 100.0k 1.000M1.000 10.00M
-220
-200
-180
-160
-140
-120
-100
-80
-240
-60
freq, Hz
PN_PFD_only
m1
m2
m1
freq=10.00kHz
PN_PFD_only=-78.768
m2
freq=100.0kHz
10.00 100.0 1.000k 10.00k 100.0k 1.000M1.000 10.00M
-220
-200
-180
-160
-140
-120
-100
-80
-240
-60
freq, Hz
PN_PFD_only
m1
m2
Phase Noise with PFD Only

(1)
(2) (3)
m1
freq=10.00kHz
PN_Ref_only=-88.246
m2
freq=100.0kHz
PN_Ref_only=-92.857
10.00 100.0 1.000k 10.00k 100.0k 1.000M1.000 10.00M
-240
-220
-200
-180
-160
-140
-120
-100
-80
-60
-40
-260
-20
freq, Hz
PN_Ref_only
m1
m2
m1
freq=10.00kHz
PN_Ref_only=-112.600
m2
freq=100.0kHz
10.00 100.0 1.000k 10.00k 100.0k 1.000M1.000 10.00M
-240
-220
-200
-180
-160
-140
-120
-100
-80
-60
-40
-260
-20
freq, Hz
PN_Ref_only
m1
m2
m1
freq=10.00kHz
PN_Ref_only=-87.837
m2
freq=100.0kHz
10.00 100.0 1.000k 10.00k 100.0k 1.000M1.000 10.00M
-240
-220
-200
-180
-160
-140
-120
-100
-80
-60
-40
-260
-20
freq, Hz
PN_Ref_only
m1
m2
(1) Loop BW = 1 kHz
(2) Loop BW =10 kHz
Phase Noise with Reference Osc. Only

(1)
(2) (3)
m1
freq=10.00kHz
PN_VCO_only=-126.536
m2
freq=100.0kHz
10.00 100.0 1.000k 10.00k 100.0k 1.000M1.000 10.00M
-195
-190
-185
-180
-175
-170
-165
-160
-155
-150
-145
-140
-135
-130
-125
-120
-115
-110
-105
-100
-95
-90
-85
-80
-75
-200
-70
freq, Hz
PN_VCO_only
m1
m2
m1
freq=10.00kHz
PN_VCO_only=-96.380
m2
freq=100.0kHz
10.00 100.0 1.000k 10.00k 100.0k 1.000M1.000 10.00M
-195
-190
-185
-180
-175
-170
-165
-160
-155
-150
-145
-140
-135
-130
-125
-120
-115
-110
-105
-100
-95
-90
-85
-80
-75
-200
-70
freq, Hz
PN_VCO_only
m1
m2
m1
freq=10.00kHz
PN_VCO_only=-96.443
m2
freq=100.0kHz
10.00 100.0 1.000k 10.00k 100.0k 1.000M1.000 10.00M
-195
-190
-185
-180
-175
-170
-165
-160
-155
-150
-145
-140
-135
-130
-125
-120
-115
-110
-105
-100
-95
-90
-85
-80
-75
-200
-70
freq, Hz
PN_VCO_only
m1
m2
(1) Loop BW = 1 kHz
(2) Loop BW =10 kHz
Phase Noise with VCO Only

(1)
(2) (3)
m1
freq=1.000kHz
PNTotal=-75.603
m2
freq=10.00kHz
PNTotal=-78.205
m3
freq=1.000kHz
m4
freq=10.00kHz
10.00 100.0 1.000k 10.00k 100.0k 1.000M1.000 10.00M
-140
-120
-100
-80
-60
-40
-20
0
-160
20
f req, Hz
PNTotal
m1 m2
PN_VCO_only
m3
m4PN_VCO_FreeRun
m1
freq=1.000kHz
PNTotal=-70.960
m2
freq=10.00kHz
PNTotal=-93.347
m3
freq=1.000kHz
PN_VCO_only=-76.978
m4
freq=10.00kHz
PN_VCO_only=-96.380
10.00 100.0 1.000k 10.00k 100.0k 1.000M1.000 10.00M
-140
-120
-100
-80
-60
-40
-20
0
-160
20
f req, Hz
PNTotal
m1
m2
PN_VCO_only
m3
m4
PN_VCO_FreeRun
m1
freq=1.000kHz
PNTotal=-75.282
m2
freq=10.00kHz
PNTotal=-76.852
m3
freq=1.000kHz
m4
freq=10.00kHz
PN_VCO_only=-96.443
10.00 100.0 1.000k 10.00k 100.0k 1.000M1.000 10.00M
-140
-120
-100
-80
-60
-40
-20
0
-160
20
f req, Hz
PNTotal
m1 m2
PN_VCO_only
m3
m4
PN_VCO_FreeRun
(1) Loop BW = 1 kHz
(2) Loop BW =10 kHz
VCO in Loop vs. VCO Free-Running

(1) N = 2400
(2) N= 1400
m1
freq=1.000kHz
PNTotal=-75.282
m2
freq=10.00kHz
PNTotal=-76.852
m3
freq=1.000kHz
m4
freq=10.00kHz
PN_VCO_only=-96.443
10.00 100.0 1.000k 10.00k 100.0k 1.000M1.000 10.00M
-140
-120
-100
-80
-60
-40
-20
0
-160
20
f req, Hz
PNTotal
m1 m2
PN_VCO_only
m3
m4
PN_VCO_FreeRun
m1
freq=1.000kHz
PNTotal=-83.041
m2
freq=10.00kHz
PNTotal=-83.673
m3
freq=1.000kHz
m4
freq=10.00kHz
10.00 100.0 1.000k 10.00k 100.0k 1.000M1.000 10.00M
-140
-120
-100
-80
-60
-40
-20
0
-160
20
f req, Hz
PNTotal
m1 m2
PN_VCO_only
m3
m4
PN_VCO_FreeRun
Phase Noise with Various Modulus N

Phase-locked Loops - Theory and Design

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