vlsi-unit-2-ppt.pdf for electronics engineering

Department of Electronics and Communication Engineering, VBIT
UNIT - 2
VLSI CIRCUIT DESIGN
PROCESSES
P.VIDYA SAGAR ( ASSOCIATE PROFESSOR)
VLSI

SYLLABUS
UNIT II
VLSI CIRCUIT DESIGN PROCESSES: VLSI Design Flow, MOS Layers, Stick Diagrams, Design
Rules and Layout, 2 m CMOS Design rules for wires, Contacts and Transistors Layout Diagrams for
NMOS and CMOS Inverters and Gates, Scaling of MOS circuits.
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CONTENTS:
➢ VLSI design flow
➢ MOS layers
➢ Stick Diagrams
➢ Design Rules and Layout diagrams
➢ 2µm Design Rules
➢ Layout Diagrams for Inverter, Logic gates
➢ Scaling of MOS
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➢VLSI design flow
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MOS Layers :
There are 4 layers
• N-diffusion
• P-diffusion
• Poly Si
• Metal
•These layers are isolated by one another by thick or thin silicon dioxide insulating layers.
• Thin oxide mask region includes n-diffusion / p-diffusion and transistor channel.
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Stick Diagrams :
➢ A stick diagram is a cartoon of a layout.
➢ Does show all components/ vias (except possibly tub ties), relative
placement.
➢ Does not show exact placement, transistor sizes, wire lengths, wire
widths, tub boundaries
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• Key idea: "Stick figure cartoon" of a layout
• Useful for planning layout
 relative placement of transistors
 assignment of signals to layers
 connections between cells
 cell hierarchy
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Stick Diagrams
Metal
poly
ndiff
pdiff
Can also draw in shades
of gray/line style.
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Rules for Drawing Stick Diagrams :
• Metal 1
• Poly Si
• N-diffusion
• P-diffusion
Rule 1:
• When two or more sticks of the same type cross or touch other that
represents electrical contact.
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Rule 2:
• When two or more sticks of different type cross or touch other there is no
electrical contact.(if contact is needed show explicitly)
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Rule 3: When a poly crosses diffusion it represents MOSFET. If contact is
shown it is not transistor.
nMOSFET pMOSFET nMOSFET
(Depletion Mode)
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STICK DIAGRAMS
P- Diffusion
n- Diffusion
Poly silicon
Metal 1
Contact cut
N implant
Demarcation line
Substrate contact
PMOS Enhancement Transistor
NMOS Enhancement Transistor
NMOS Depletion transistor
NPN Bipolar Transistor
Buried Contact
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Stick diagram
Encodings for a simple single metal nMOS process
COLOR STICK ENCODING LAYERS MASK LAYOUT ENCODING
CIF LAYER
Caltech
Intermediate Form
MONOCROME MONOCROME
GREEN
RED
BLUE
BLACK
GRAY
n-diffusion
n+active
Thniox
Polysilicon
Metal 1
Contact cut
Overglass
NOT APPLICABLE
nMOS
ONLY
YELLOW
Implant
Buried
contact
nMOS ONLY
BROWN
ND
NP
NM
NC
NG
NI
NB
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nMOS Design Style:
Step 1:Draw metal VDD and GND rails in parallel leaving sufficient space for
circuit components between them.
VDD
GND
Step 2: Thinox (green) paths are drawn between rails for inverter &
inverter logic.
Vin
VOUT
VDD
GND
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Step 3: Connect poly over thinox wherever transistor required.
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Step 4: Connect metal wherever is required and create contact for connection.
Vout
Vin
Vin
VOUT
VDD
GND
Depletion
mode nMOS
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VDD
GND
NMOS INVERTER STICK DIAGRAM
D
A
B
S
D
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5 V
Dep
Vout
Enh
0V

5 V
Dep
Vout
Enh
0V
Vin
5 v
0 V
Vin
5 v
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VDD
GND
CMOS INVERTER STICK DIAGRAM
FIG 1 Supply rails
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VDD
GN
D
PMOS
NMOS
S
S
D
D
Fig 2 Drawing Pmos and Nmos Transistors between Supply rails
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VDD
GND
PMOS
NMOS
A
S
S
D
D
Fig 3 Combining Gate of Pmos and Nmos Transistors and giving common input With same gate poly silicon metal
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VDD
GND
PMOS
NMOS
A
D
S
S D
Fig 4 Combining Drain pf Pmos and Nmos Transistors to take output with metal 1
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VDD
GND
PMOS
NMOS
D
A
S
S D
B
Fig 5 Take the output with the poly silicon metal
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VDD
GND
PMOS
NMOS
D
A
S
S D
B
Fig 6 Connect the source of Pmos to VDD and Nmos to GND
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VDD
GND
PMOS
NMOS
D
A
S
S D
B
CONTACT
Fig 7 Connect the contact cuts where the different metals are connected
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VDD
GND
PMOS
NMOS
D
A
S
S D
B
CONTACT
Fig 8 Final CMOS Inverter
Substrate contact
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Alternate Layout of NOT Gate
Gnd
Vp
x
x
X
x
Vp
Gnd
X
x
X
X
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NAND GATE
Schematic Stick diagram Layout
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VDD
GND
CMOS NAND GATE STICK DIAGRAM
FIG 9 Supply rails
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VDD
GND
Fig 10 Drawing P and N Diffusion between Supply rails
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VDD
GND
S
S
S
D
D
D
D
S
A B
C
Fig 11 Drawing the poly silicon for two different inputs and
identify the source and drain
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VDD
GND
S
S
S
D
D
D
D
S
A B
C
Fig 12 Connect the source of Pmos to VDD and Nmos to GND and
subtrate contacts of both
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VDD
GND
S
S
S
D
D
D
D
S
A B
C
Fig 13 Draw the output connections
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VDD
GND
S
S
S
D
D
D
D
S
A B
C
Fig 14 Connect the contact cuts where the different metals are connected
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Gnd
Vp
b
a.
a b

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Vdd contact
Vss contact
Vdd
Vss
Demarcation Line
Vout(A nand B)
A
Ploy(G)
Ploy(G)
Ploy(G)
Ploy(G)
s
s
s s
D
D
D
D
B
Cmos Nor GATE
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Cmos Nor GATE
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Department of Electronics and Communication Engineering, VBIT VIDYA SAGAR P
38
Power
Ground
B
C
Out
A

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BiCmos inverter
Vss contact
Vdd
Vss
Demarcation
Line Vout
Vdd contact

Encodings for NMOS process:
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Encodings for CMOS process:
•Figure shows when a n-transistor is
formed: a transistor is formed when a
green line (n+ diffusion) crosses a red
line (poly) completely.
•Figure also shows when a p-
transistor is formed: a transistor is
formed when a yellow line(p+
diffusion) crosses a red line (poly)
completely
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Encoding for BJT and MOSFETs:
layers in an nMOS chip consists of
 a p-type substrate
 paths of n-type diffusion
 a thin layer of silicon dioxide
 paths of polycrystalline silicon
 a thick layer of silicon dioxide
 paths of metal (usually aluminium)
 a further thick layer of silicon dioxide
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LAYOUT
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1.Scalable Design Rules (e.g. SCMOS, λ-based design rules):
In this approach, all rules are defined in terms of a single parameter λ.
The rules are so chosen that a design can be easily ported over a cross section of industrial
process ,making the layout portable .Scaling can be easily done by simply changing the
value .
2.Absolute Design Rules (e.g. μ-based design rules ) :
In this approach, the design rules are expressed in absolute dimensions (e.g.0.75μm) and
therefore can exploit the features of a given process to a maximum degree.
There are primarily two approaches in describing the design rules
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What is Via?
It is used to connect higher level metals from metal1 connection
The direct connections between metal, polysilicon, and diffusion use
intermediate layers such as the contact-cut and the buried-contact layers.
The entire chip is typically covered with a layer of protective coating called
overglass
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46
Buried contacts:
The buried contact is a method to make direct ohmic contact between the polysilicon gate material and
the junctions, in silicon-gate integrated circuits.
With this method – requiring an additional masking layer – it was possible to use the polysilicon as an
additional layer of interconnection, greatly improving the circuit density, particularly in random logic
circuits.
Here gate length is dependent upon the alignment of the buried contact mask relative to the poly silicon
and therefore vary by ± λ.
Butting contact:
The gate and source of a depletion device can be connected by a method known as butting contact.
Here metal makes contact to both the diffusion forming the source of the depletion transistor and to the
poly silicon forming this device’s gate.
Its advantage is that no buried contact mask is required and it avoids associated processing.

CMOS Process Layers
Layer
Polysilicon
Metal1
Metal2
Contact To Poly
Contact To Diffusion
Via
Well (p,n)
Active Area (n+,p+)
Color Representation
Yellow
Green
Red
Blue
Magenta
Black
Black
Black
Select (p+,n+) Green
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2λ
2λ
1λ
2λ
3λ
P diffusion N diffusion
P diffusion
P diffusion N diffusion
P diffusion
METAL 1
METAL 1
4λ
4λ
3λ
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Intra-Layer Design Rules
Metal2
4
3
10
9
0
Well
Active
3
3
Polysilicon
2
2
Different Potential
Same Potential
Metal1
3
3
2
Contact
or Via
Select
2
or
6
2
Hole
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Transistor Layout
1
2
5
3
Transistor
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Via’s and Contacts
1
2
1
Via
Metal to
Poly Contact
Metal to
Active Contact
1
2
5
4
3 2
2
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Select Layer
1
3 3
2
2
2
Well
Substrate
Select
3
5
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2λ
4λ
4λ
1λ 2λ 4λ
4λ
1λ
2λ
3λ
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2λ
2λ
2λ
2λ
2λ
2λ
2λ
2λ
2λ
2λ
6λ x 6λ
2λ
2λ
2λ
2λ
2λ
NMOS
ENHANCEMENT
PMOS
ENHANCEMENT
NMOS
DEPLETION
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LAMBDA BSED RULES
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Lambda based Design Rules:
Design rules include width rules and spacing rules.
Mead and Conway developed a set of simplified scalable λ -based design rules, which
are valid for a range of fabrication technologies.
In these rules, the minimum feature size of a technology is characterized as 2 λ .
 All width and spacing rules are specified in terms of the parameter λ .
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Design rules for the diffusion layers and metal layers
Figure shows the design rule n diffusion, p diffusion, poly, metal1 and metal 2. The n and p
diffusion lines is having a minimum width of 2λ and a minimum spacing of 3λ. Similarly
it shows for other layers.
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Design rules for transistors and gate over hang distance
Figure shows the design rule for the transistor, and it also shows that the poly should extend
for a minimum of 2λ beyond the diffusion boundaries.(gate over hang distance)
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Via
VIA is used to connect higher level metals from metal1 connection.
Figure shows the design rules for
contact cuts and Vias. The design rule
for contact is minimum 2λx2λ and
same is applicable for a Via.
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Buried contact and Butting contact
Buried contact is made down
each layer to be joined
Butting contact
The layers are butted together in such a way
the two contact cuts become contiguous
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CMOS LAMBDA BASED DESIGN RULES:
Figure shows the rules to be followed in CMOS well processes to accommodate both n
and p transistors
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CMOS Inverter Layout
A A’
n
p-substrate Field
Oxide
p+
n+
In
Out
GND VDD
(a) Layout
(b) Cross-Section along A-A’
A A’
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SCHEMATIC AND LAYOUT OF BASIC GATES
a) CMOS INVERTER NOT GATE
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The CMOS NOT Gate
X
X
X
X
Vp
Gnd
x
Gnd
n-well
Vp
x x
x
Contact Cut
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Alternate Layout of NOT Gate
Gnd
Vp
x
x
X
x
Vp
Gnd
X
x
X
X
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b) NAND GATE
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NAND2 Layout
Gnd
Vp
b
a.
a b
X
Vp
Gnd
X X
X X
a b
b
a.
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NOR2 Layout
Gnd
Vp
b
a
a b
X
Vp
Gnd
X X
X X
a b
b
a 
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TRANSMISSION GATE
Symbol schematic stick diagram
layout
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Example: Inverter
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Inverter, contd..
Layout using Electric
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Example: NAND3
•Horizontal N-diffusion and p-diffusion strips
•Vertical polysilicon gates
•Metal1 VDD rail at top
•Metal1 GND rail at bottom
•32 by 40
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NAND3 (using Electric), contd.
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Scaling
• VLSI technology is constantly evolving towards smaller line widths
• Reduced feature size generally leads to
– better / faster performance
– More gate / chip
• More accurate description of modern technology is ULSI (ultra large
scale integration
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Scaling Factors
• In our discussions we will consider 2 scaling factors, α and β
• 1/ β is the scaling factor for VDD and oxide thickness D
• 1/ α is scaling factor for all other linear dimensions
• We will assume electric field is kept constant
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Scaling Factors for Device Parameters
Simple derivations showing the effects of scaling are derived in Pucknell and Eshraghian pages 125 - 129
It is important that you understand how the following parameters are effected by scaling.
 Gate Area
 Gate Capacitance per unit area
 Gate Capacitance
 Charge in Channel
 Channel Resistance
 Transistor Delay
 Maximum Operating Frequency
 Transistor Current
 Switching Energy
 Power Dissipation Per Gate (Static and Dynamic)
 Power Dissipation Per Unit Area
 Power - Speed Product
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MOSFET Scaling
❑ Constant Field Scaling
❑ Constant Voltage Scaling
❑ Lateral Scaling
❑SCALING - refers to ordered reduction in dimensions of the MOSFET and other VLSI features
❑Reduce Size of VLSI chips.
❑Change operational characteristics of MOSFETs and parasitic.
❑Physical limits restrict degree of scaling that can be achieved.
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Constant Field Scaling
❑ The electric field E is kept constant, and the scaled device is obtained by applying a dimensionless scale-
factor α (such that E is unchanged):
❑ all dimensions, including those vertical to the surface (1/α)
❑ device voltages (1/α)
❑ the concentration densities (α).
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Constant Voltage Scaling
❑ Vdd is kept constant.
❑ All dimensions, including those vertical to the surface are scaled.
❑ Concentration densities are scaled.
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Lateral Scaling
❑ Only the gate length is scaled L = 1/α (gate-shrink).
❑ Year Feature Size(μm)
1980 5.0
1983 3.5
1985 2.5
1987 1.75
1989 1.25
1991 1.0
1993 0.8
1995 0.6
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PARAMETER SCALING MODEL
Constant Constant Lateral
Field Voltage
Length (L) 1/α 1/α 1/α
Width (W) 1/α 1/α 1
Supply Voltage (V) 1/α 1 1
Gate Oxide thickness (tox) 1/α 1/α 1
Junction depth (Xj) 1/α 1/α 1
Current (I) 1/α α α
Power Dissipation (P) 1/α2 α α
Electric Field 1 α 1
Load Capacitance (C) 1/α 1/α 1/α
Gate Delay (T) 1/α 1/α2 1/α2
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Scaling of Interconnects
• Resistance of track R ~ L / wt
• R (scaled) ~ (L / α) / ( (w/ α )* (t
/α))
• R(scaled) = αR
• therefore resistance increases with
scaling
t w L
A
B
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Scaling - Time Constant
• Time constant of track connected to gate,
• T = R * Cg
• T(scaled) = α R * (β / α2) *Cg = (β / α) *R*Cg
• Let β = α, therefore T is unscaled!
• Therefore delays in tracks don’t reduce with scaling
• Therefore as tracks get proportionately larger, effect gets worse
• Cross talk between connections gets worse because of reduced spacing
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Scaling of MOS and circuit parameter
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