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vlsi-unit-2-ppt.pdf for electronics engineering

This document contains lecture slides on VLSI circuit design processes from the Department of Electronics and Communication Engineering at VBIT. It discusses topics like VLSI design flow, MOS layers, stick diagrams, design rules, layout diagrams for basic gates like inverters, and scaling of MOS circuits. The document provides illustrations and explanations of concepts like stick diagrams, nMOS and CMOS inverter layout, NAND gate layout, and encodings for representing different layers in VLSI design.

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Department of Electronics and Communication Engineering, VBIT Department of Electronics and Communication Engineering, VBIT UNIT - 2 VLSI CIRCUIT DESIGN PROCESSES P.VIDYA SAGAR ( ASSOCIATE PROFESSOR) VLSI
Department of Electronics and Communication Engineering, VBIT Department of Electronics and Communication Engineering, VBIT SYLLABUS UNIT II VLSI CIRCUIT DESIGN PROCESSES: VLSI Design Flow, MOS Layers, Stick Diagrams, Design Rules and Layout, 2 m CMOS Design rules for wires, Contacts and Transistors Layout Diagrams for NMOS and CMOS Inverters and Gates, Scaling of MOS circuits. 2 VIDYA SAGAR P
Department of Electronics and Communication Engineering, VBIT Department of Electronics and Communication Engineering, VBIT CONTENTS: ➢ VLSI design flow ➢ MOS layers ➢ Stick Diagrams ➢ Design Rules and Layout diagrams ➢ 2µm Design Rules ➢ Layout Diagrams for Inverter, Logic gates ➢ Scaling of MOS 3 VIDYA SAGAR P
Department of Electronics and Communication Engineering, VBIT Department of Electronics and Communication Engineering, VBIT ➢VLSI design flow 4 VIDYA SAGAR P
Department of Electronics and Communication Engineering, VBIT Department of Electronics and Communication Engineering, VBIT 5 VIDYA SAGAR P
Department of Electronics and Communication Engineering, VBIT Department of Electronics and Communication Engineering, VBIT MOS Layers : There are 4 layers • N-diffusion • P-diffusion • Poly Si • Metal •These layers are isolated by one another by thick or thin silicon dioxide insulating layers. • Thin oxide mask region includes n-diffusion / p-diffusion and transistor channel. 6 VIDYA SAGAR P
Department of Electronics and Communication Engineering, VBIT Department of Electronics and Communication Engineering, VBIT Stick Diagrams : ➢ A stick diagram is a cartoon of a layout. ➢ Does show all components/ vias (except possibly tub ties), relative placement. ➢ Does not show exact placement, transistor sizes, wire lengths, wire widths, tub boundaries 7 VIDYA SAGAR P
Department of Electronics and Communication Engineering, VBIT Department of Electronics and Communication Engineering, VBIT • Key idea: "Stick figure cartoon" of a layout • Useful for planning layout  relative placement of transistors  assignment of signals to layers  connections between cells  cell hierarchy 8 VIDYA SAGAR P
Department of Electronics and Communication Engineering, VBIT Stick Diagrams Metal poly ndiff pdiff Can also draw in shades of gray/line style. VIDYA SAGAR P 9
Department of Electronics and Communication Engineering, VBIT Department of Electronics and Communication Engineering, VBIT Rules for Drawing Stick Diagrams : • Metal 1 • Poly Si • N-diffusion • P-diffusion Rule 1: • When two or more sticks of the same type cross or touch other that represents electrical contact. 10 VIDYA SAGAR P
Department of Electronics and Communication Engineering, VBIT Department of Electronics and Communication Engineering, VBIT Rule 2: • When two or more sticks of different type cross or touch other there is no electrical contact.(if contact is needed show explicitly) 11 VIDYA SAGAR P
Department of Electronics and Communication Engineering, VBIT Department of Electronics and Communication Engineering, VBIT Rule 3: When a poly crosses diffusion it represents MOSFET. If contact is shown it is not transistor. nMOSFET pMOSFET nMOSFET (Depletion Mode) 12 VIDYA SAGAR P
Department of Electronics and Communication Engineering, VBIT Department of Electronics and Communication Engineering, VBIT STICK DIAGRAMS P- Diffusion n- Diffusion Poly silicon Metal 1 Contact cut N implant Demarcation line Substrate contact PMOS Enhancement Transistor NMOS Enhancement Transistor NMOS Depletion transistor NPN Bipolar Transistor Buried Contact 13 VIDYA SAGAR P
Department of Electronics and Communication Engineering, VBIT Stick diagram Encodings for a simple single metal nMOS process COLOR STICK ENCODING LAYERS MASK LAYOUT ENCODING CIF LAYER Caltech Intermediate Form MONOCROME MONOCROME GREEN RED BLUE BLACK GRAY n-diffusion n+active Thniox Polysilicon Metal 1 Contact cut Overglass NOT APPLICABLE nMOS ONLY YELLOW Implant Buried contact nMOS ONLY BROWN ND NP NM NC NG NI NB VIDYA SAGAR P 14
Department of Electronics and Communication Engineering, VBIT Department of Electronics and Communication Engineering, VBIT nMOS Design Style: Step 1:Draw metal VDD and GND rails in parallel leaving sufficient space for circuit components between them. VDD GND Step 2: Thinox (green) paths are drawn between rails for inverter & inverter logic. Vin VOUT VDD GND 15 VIDYA SAGAR P
Department of Electronics and Communication Engineering, VBIT Department of Electronics and Communication Engineering, VBIT Step 3: Connect poly over thinox wherever transistor required. 16 VIDYA SAGAR P
Department of Electronics and Communication Engineering, VBIT Department of Electronics and Communication Engineering, VBIT Step 4: Connect metal wherever is required and create contact for connection. Vout Vin Vin VOUT VDD GND Depletion mode nMOS 17 VIDYA SAGAR P
Department of Electronics and Communication Engineering, VBIT Department of Electronics and Communication Engineering, VBIT VDD GND NMOS INVERTER STICK DIAGRAM D A B S D 18 VIDYA SAGAR P 5 V Dep Vout Enh 0V
Department of Electronics and Communication Engineering, VBIT 5 V Dep Vout Enh 0V Vin 5 v 0 V Vin 5 v 19 VIDYA SAGAR P
Department of Electronics and Communication Engineering, VBIT Department of Electronics and Communication Engineering, VBIT VDD GND CMOS INVERTER STICK DIAGRAM FIG 1 Supply rails 20 VIDYA SAGAR P
Department of Electronics and Communication Engineering, VBIT Department of Electronics and Communication Engineering, VBIT VDD GN D PMOS NMOS S S D D CMOS INVERTER STICK DIAGRAM Fig 2 Drawing Pmos and Nmos Transistors between Supply rails 21 VIDYA SAGAR P
Department of Electronics and Communication Engineering, VBIT Department of Electronics and Communication Engineering, VBIT VDD GND PMOS NMOS A S S D D CMOS INVERTER STICK DIAGRAM Fig 3 Combining Gate of Pmos and Nmos Transistors and giving common input With same gate poly silicon metal 22 VIDYA SAGAR P
Department of Electronics and Communication Engineering, VBIT Department of Electronics and Communication Engineering, VBIT VDD GND PMOS NMOS A D S S D CMOS INVERTER STICK DIAGRAM Fig 4 Combining Drain pf Pmos and Nmos Transistors to take output with metal 1 23 VIDYA SAGAR P
Department of Electronics and Communication Engineering, VBIT Department of Electronics and Communication Engineering, VBIT VDD GND PMOS NMOS D A S S D B CMOS INVERTER STICK DIAGRAM Fig 5 Take the output with the poly silicon metal 24 VIDYA SAGAR P
Department of Electronics and Communication Engineering, VBIT Department of Electronics and Communication Engineering, VBIT VDD GND PMOS NMOS D A S S D B CMOS INVERTER STICK DIAGRAM Fig 6 Connect the source of Pmos to VDD and Nmos to GND 25 VIDYA SAGAR P
Department of Electronics and Communication Engineering, VBIT Department of Electronics and Communication Engineering, VBIT VDD GND PMOS NMOS D A S S D B CONTACT CMOS INVERTER STICK DIAGRAM Fig 7 Connect the contact cuts where the different metals are connected 26 VIDYA SAGAR P
Department of Electronics and Communication Engineering, VBIT Department of Electronics and Communication Engineering, VBIT VDD GND PMOS NMOS D A S S D B CONTACT CMOS INVERTER STICK DIAGRAM Fig 8 Final CMOS Inverter Substrate contact 27 VIDYA SAGAR P
Department of Electronics and Communication Engineering, VBIT Alternate Layout of NOT Gate Gnd Vp x x X x Vp Gnd X x X X 28 VIDYA SAGAR P
Department of Electronics and Communication Engineering, VBIT NAND GATE Schematic Stick diagram Layout VIDYA SAGAR P 29
Department of Electronics and Communication Engineering, VBIT Department of Electronics and Communication Engineering, VBIT VDD GND CMOS NAND GATE STICK DIAGRAM FIG 9 Supply rails 30 VIDYA SAGAR P
Department of Electronics and Communication Engineering, VBIT Department of Electronics and Communication Engineering, VBIT VDD GND CMOS NAND GATE STICK DIAGRAM Fig 10 Drawing P and N Diffusion between Supply rails 31 VIDYA SAGAR P
Department of Electronics and Communication Engineering, VBIT Department of Electronics and Communication Engineering, VBIT VDD GND S S S D D D D S A B C CMOS NAND GATE STICK DIAGRAM Fig 11 Drawing the poly silicon for two different inputs and identify the source and drain 32 VIDYA SAGAR P
Department of Electronics and Communication Engineering, VBIT Department of Electronics and Communication Engineering, VBIT VDD GND S S S D D D D S A B C CMOS NAND GATE STICK DIAGRAM Fig 12 Connect the source of Pmos to VDD and Nmos to GND and subtrate contacts of both 33 VIDYA SAGAR P
Department of Electronics and Communication Engineering, VBIT Department of Electronics and Communication Engineering, VBIT VDD GND S S S D D D D S A B C CMOS NAND GATE STICK DIAGRAM Fig 13 Draw the output connections 34 VIDYA SAGAR P
Department of Electronics and Communication Engineering, VBIT Department of Electronics and Communication Engineering, VBIT VDD GND S S S D D D D S A B C CMOS NAND GATE STICK DIAGRAM Fig 14 Connect the contact cuts where the different metals are connected 35 VIDYA SAGAR P Gnd Vp b a. a b
Department of Electronics and Communication Engineering, VBIT Department of Electronics and Communication Engineering, VBIT 36 Vdd contact Vss contact Vdd Vss Demarcation Line Vout(A nand B) A Ploy(G) Ploy(G) Ploy(G) Ploy(G) s s s s D D D D B Cmos Nor GATE VIDYA SAGAR P
Department of Electronics and Communication Engineering, VBIT Cmos Nor GATE VIDYA SAGAR P 37
Department of Electronics and Communication Engineering, VBIT VIDYA SAGAR P 38 Power Ground B C Out A
Department of Electronics and Communication Engineering, VBIT VIDYA SAGAR P 39 BiCmos inverter Vss contact Vdd Vss Demarcation Line Vout Vdd contact
Department of Electronics and Communication Engineering, VBIT Department of Electronics and Communication Engineering, VBIT Encodings for NMOS process: 40 VIDYA SAGAR P
Department of Electronics and Communication Engineering, VBIT Encodings for CMOS process: •Figure shows when a n-transistor is formed: a transistor is formed when a green line (n+ diffusion) crosses a red line (poly) completely. •Figure also shows when a p- transistor is formed: a transistor is formed when a yellow line(p+ diffusion) crosses a red line (poly) completely 41 VIDYA SAGAR P
Department of Electronics and Communication Engineering, VBIT Encoding for BJT and MOSFETs: layers in an nMOS chip consists of  a p-type substrate  paths of n-type diffusion  a thin layer of silicon dioxide  paths of polycrystalline silicon  a thick layer of silicon dioxide  paths of metal (usually aluminium)  a further thick layer of silicon dioxide 42 VIDYA SAGAR P
Department of Electronics and Communication Engineering, VBIT Department of Electronics and Communication Engineering, VBIT LAYOUT 43 VIDYA SAGAR P
Department of Electronics and Communication Engineering, VBIT Department of Electronics and Communication Engineering, VBIT 1.Scalable Design Rules (e.g. SCMOS, λ-based design rules): In this approach, all rules are defined in terms of a single parameter λ. The rules are so chosen that a design can be easily ported over a cross section of industrial process ,making the layout portable .Scaling can be easily done by simply changing the value . 2.Absolute Design Rules (e.g. μ-based design rules ) : In this approach, the design rules are expressed in absolute dimensions (e.g.0.75μm) and therefore can exploit the features of a given process to a maximum degree. There are primarily two approaches in describing the design rules 44 VIDYA SAGAR P
Department of Electronics and Communication Engineering, VBIT Department of Electronics and Communication Engineering, VBIT What is Via? It is used to connect higher level metals from metal1 connection The direct connections between metal, polysilicon, and diffusion use intermediate layers such as the contact-cut and the buried-contact layers. The entire chip is typically covered with a layer of protective coating called overglass 45 VIDYA SAGAR P
Department of Electronics and Communication Engineering, VBIT VIDYA SAGAR P 46 Buried contacts: The buried contact is a method to make direct ohmic contact between the polysilicon gate material and the junctions, in silicon-gate integrated circuits. With this method – requiring an additional masking layer – it was possible to use the polysilicon as an additional layer of interconnection, greatly improving the circuit density, particularly in random logic circuits. Here gate length is dependent upon the alignment of the buried contact mask relative to the poly silicon and therefore vary by ± λ. Butting contact: The gate and source of a depletion device can be connected by a method known as butting contact. Here metal makes contact to both the diffusion forming the source of the depletion transistor and to the poly silicon forming this device’s gate. Its advantage is that no buried contact mask is required and it avoids associated processing.
Department of Electronics and Communication Engineering, VBIT CMOS Process Layers Layer Polysilicon Metal1 Metal2 Contact To Poly Contact To Diffusion Via Well (p,n) Active Area (n+,p+) Color Representation Yellow Green Red Blue Magenta Black Black Black Select (p+,n+) Green 47 VIDYA SAGAR P
Department of Electronics and Communication Engineering, VBIT Department of Electronics and Communication Engineering, VBIT 2λ 2λ 1λ 2λ 3λ P diffusion N diffusion P diffusion P diffusion N diffusion P diffusion METAL 1 METAL 1 4λ 4λ 3λ 48 VIDYA SAGAR P
Department of Electronics and Communication Engineering, VBIT Intra-Layer Design Rules Metal2 4 3 10 9 0 Well Active 3 3 Polysilicon 2 2 Different Potential Same Potential Metal1 3 3 2 Contact or Via Select 2 or 6 2 Hole 49 VIDYA SAGAR P
Department of Electronics and Communication Engineering, VBIT Transistor Layout 1 2 5 3 Transistor 50 VIDYA SAGAR P
Department of Electronics and Communication Engineering, VBIT Via’s and Contacts 1 2 1 Via Metal to Poly Contact Metal to Active Contact 1 2 5 4 3 2 2 51 VIDYA SAGAR P
Department of Electronics and Communication Engineering, VBIT Select Layer 1 3 3 2 2 2 Well Substrate Select 3 5 52 VIDYA SAGAR P
Department of Electronics and Communication Engineering, VBIT Department of Electronics and Communication Engineering, VBIT 2λ 4λ 4λ 1λ 2λ 4λ 4λ 1λ 2λ 3λ 53 VIDYA SAGAR P
Department of Electronics and Communication Engineering, VBIT Department of Electronics and Communication Engineering, VBIT 2λ 2λ 2λ 2λ 2λ 2λ 2λ 2λ 2λ 2λ 6λ x 6λ 2λ 2λ 2λ 2λ 2λ NMOS ENHANCEMENT PMOS ENHANCEMENT NMOS DEPLETION 54 VIDYA SAGAR P
Department of Electronics and Communication Engineering, VBIT Department of Electronics and Communication Engineering, VBIT LAMBDA BSED RULES 55 VIDYA SAGAR P
Department of Electronics and Communication Engineering, VBIT Department of Electronics and Communication Engineering, VBIT 56 VIDYA SAGAR P
Department of Electronics and Communication Engineering, VBIT Department of Electronics and Communication Engineering, VBIT 57 VIDYA SAGAR P
Department of Electronics and Communication Engineering, VBIT Department of Electronics and Communication Engineering, VBIT 58 VIDYA SAGAR P
Department of Electronics and Communication Engineering, VBIT Department of Electronics and Communication Engineering, VBIT 59 VIDYA SAGAR P
Department of Electronics and Communication Engineering, VBIT Department of Electronics and Communication Engineering, VBIT 60 VIDYA SAGAR P
Department of Electronics and Communication Engineering, VBIT Department of Electronics and Communication Engineering, VBIT 61 VIDYA SAGAR P
Department of Electronics and Communication Engineering, VBIT Department of Electronics and Communication Engineering, VBIT 62 VIDYA SAGAR P
Department of Electronics and Communication Engineering, VBIT Department of Electronics and Communication Engineering, VBIT 63 VIDYA SAGAR P
Department of Electronics and Communication Engineering, VBIT Department of Electronics and Communication Engineering, VBIT 64 VIDYA SAGAR P
Department of Electronics and Communication Engineering, VBIT Lambda based Design Rules: Design rules include width rules and spacing rules. Mead and Conway developed a set of simplified scalable λ -based design rules, which are valid for a range of fabrication technologies. In these rules, the minimum feature size of a technology is characterized as 2 λ .  All width and spacing rules are specified in terms of the parameter λ . 65 VIDYA SAGAR P
Department of Electronics and Communication Engineering, VBIT Design rules for the diffusion layers and metal layers Figure shows the design rule n diffusion, p diffusion, poly, metal1 and metal 2. The n and p diffusion lines is having a minimum width of 2λ and a minimum spacing of 3λ. Similarly it shows for other layers. 66 VIDYA SAGAR P
Department of Electronics and Communication Engineering, VBIT Design rules for transistors and gate over hang distance Figure shows the design rule for the transistor, and it also shows that the poly should extend for a minimum of 2λ beyond the diffusion boundaries.(gate over hang distance) 67 VIDYA SAGAR P
Department of Electronics and Communication Engineering, VBIT Via VIA is used to connect higher level metals from metal1 connection. Figure shows the design rules for contact cuts and Vias. The design rule for contact is minimum 2λx2λ and same is applicable for a Via. 68 VIDYA SAGAR P
Department of Electronics and Communication Engineering, VBIT Buried contact and Butting contact Buried contact is made down each layer to be joined Butting contact The layers are butted together in such a way the two contact cuts become contiguous 69 VIDYA SAGAR P
Department of Electronics and Communication Engineering, VBIT CMOS LAMBDA BASED DESIGN RULES: Figure shows the rules to be followed in CMOS well processes to accommodate both n and p transistors 70 VIDYA SAGAR P
Department of Electronics and Communication Engineering, VBIT Department of Electronics and Communication Engineering, VBIT CMOS Inverter Layout A A’ n p-substrate Field Oxide p+ n+ In Out GND VDD (a) Layout (b) Cross-Section along A-A’ A A’ 71 VIDYA SAGAR P
Department of Electronics and Communication Engineering, VBIT SCHEMATIC AND LAYOUT OF BASIC GATES a) CMOS INVERTER NOT GATE Schematic Stick diagram Layout 72 VIDYA SAGAR P
Department of Electronics and Communication Engineering, VBIT The CMOS NOT Gate X X X X Vp Gnd x Gnd n-well Vp x x x Contact Cut 73 VIDYA SAGAR P
Department of Electronics and Communication Engineering, VBIT Department of Electronics and Communication Engineering, VBIT Alternate Layout of NOT Gate Gnd Vp x x X x Vp Gnd X x X X 74 VIDYA SAGAR P
Department of Electronics and Communication Engineering, VBIT b) NAND GATE Schematic Stick diagram Layout 75 VIDYA SAGAR P
Department of Electronics and Communication Engineering, VBIT NAND2 Layout Gnd Vp b a. a b X Vp Gnd X X X X a b b a. 76 VIDYA SAGAR P
Department of Electronics and Communication Engineering, VBIT 77 VIDYA SAGAR P
Department of Electronics and Communication Engineering, VBIT NOR2 Layout Gnd Vp b a a b X Vp Gnd X X X X a b b a  78 VIDYA SAGAR P
Department of Electronics and Communication Engineering, VBIT TRANSMISSION GATE Symbol schematic stick diagram layout 79 VIDYA SAGAR P
Department of Electronics and Communication Engineering, VBIT Example: Inverter 80 VIDYA SAGAR P
Department of Electronics and Communication Engineering, VBIT Department of Electronics and Communication Engineering, VBIT Inverter, contd.. Layout using Electric 81 VIDYA SAGAR P
Department of Electronics and Communication Engineering, VBIT Example: NAND3 •Horizontal N-diffusion and p-diffusion strips •Vertical polysilicon gates •Metal1 VDD rail at top •Metal1 GND rail at bottom •32 by 40 82 VIDYA SAGAR P
Department of Electronics and Communication Engineering, VBIT Department of Electronics and Communication Engineering, VBIT NAND3 (using Electric), contd. 83 VIDYA SAGAR P
Department of Electronics and Communication Engineering, VBIT Department of Electronics and Communication Engineering, VBIT 84 VIDYA SAGAR P
Department of Electronics and Communication Engineering, VBIT Department of Electronics and Communication Engineering, VBIT Scaling • VLSI technology is constantly evolving towards smaller line widths • Reduced feature size generally leads to – better / faster performance – More gate / chip • More accurate description of modern technology is ULSI (ultra large scale integration 85 VIDYA SAGAR P
Department of Electronics and Communication Engineering, VBIT Department of Electronics and Communication Engineering, VBIT Scaling Factors • In our discussions we will consider 2 scaling factors, α and β • 1/ β is the scaling factor for VDD and oxide thickness D • 1/ α is scaling factor for all other linear dimensions • We will assume electric field is kept constant 86 VIDYA SAGAR P
Department of Electronics and Communication Engineering, VBIT Department of Electronics and Communication Engineering, VBIT Scaling Factors for Device Parameters Simple derivations showing the effects of scaling are derived in Pucknell and Eshraghian pages 125 - 129 It is important that you understand how the following parameters are effected by scaling.  Gate Area  Gate Capacitance per unit area  Gate Capacitance  Charge in Channel  Channel Resistance  Transistor Delay  Maximum Operating Frequency  Transistor Current  Switching Energy  Power Dissipation Per Gate (Static and Dynamic)  Power Dissipation Per Unit Area  Power - Speed Product 87 VIDYA SAGAR P
Department of Electronics and Communication Engineering, VBIT Department of Electronics and Communication Engineering, VBIT MOSFET Scaling ❑ Constant Field Scaling ❑ Constant Voltage Scaling ❑ Lateral Scaling ❑SCALING - refers to ordered reduction in dimensions of the MOSFET and other VLSI features ❑Reduce Size of VLSI chips. ❑Change operational characteristics of MOSFETs and parasitic. ❑Physical limits restrict degree of scaling that can be achieved. 88 VIDYA SAGAR P
Department of Electronics and Communication Engineering, VBIT Department of Electronics and Communication Engineering, VBIT Constant Field Scaling ❑ The electric field E is kept constant, and the scaled device is obtained by applying a dimensionless scale- factor α (such that E is unchanged): ❑ all dimensions, including those vertical to the surface (1/α) ❑ device voltages (1/α) ❑ the concentration densities (α). 89 VIDYA SAGAR P
Department of Electronics and Communication Engineering, VBIT Department of Electronics and Communication Engineering, VBIT Constant Voltage Scaling ❑ Vdd is kept constant. ❑ All dimensions, including those vertical to the surface are scaled. ❑ Concentration densities are scaled. 90 VIDYA SAGAR P
Department of Electronics and Communication Engineering, VBIT Department of Electronics and Communication Engineering, VBIT Lateral Scaling ❑ Only the gate length is scaled L = 1/α (gate-shrink). ❑ Year Feature Size(μm) 1980 5.0 1983 3.5 1985 2.5 1987 1.75 1989 1.25 1991 1.0 1993 0.8 1995 0.6 91 VIDYA SAGAR P
Department of Electronics and Communication Engineering, VBIT Department of Electronics and Communication Engineering, VBIT PARAMETER SCALING MODEL Constant Constant Lateral Field Voltage Length (L) 1/α 1/α 1/α Width (W) 1/α 1/α 1 Supply Voltage (V) 1/α 1 1 Gate Oxide thickness (tox) 1/α 1/α 1 Junction depth (Xj) 1/α 1/α 1 Current (I) 1/α α α Power Dissipation (P) 1/α2 α α Electric Field 1 α 1 Load Capacitance (C) 1/α 1/α 1/α Gate Delay (T) 1/α 1/α2 1/α2 92 VIDYA SAGAR P
Department of Electronics and Communication Engineering, VBIT Department of Electronics and Communication Engineering, VBIT Scaling of Interconnects • Resistance of track R ~ L / wt • R (scaled) ~ (L / α) / ( (w/ α )* (t /α)) • R(scaled) = αR • therefore resistance increases with scaling t w L A B 93 VIDYA SAGAR P
Department of Electronics and Communication Engineering, VBIT Department of Electronics and Communication Engineering, VBIT Scaling - Time Constant • Time constant of track connected to gate, • T = R * Cg • T(scaled) = α R * (β / α2) *Cg = (β / α) *R*Cg • Let β = α, therefore T is unscaled! • Therefore delays in tracks don’t reduce with scaling • Therefore as tracks get proportionately larger, effect gets worse • Cross talk between connections gets worse because of reduced spacing 94 VIDYA SAGAR P
Department of Electronics and Communication Engineering, VBIT Department of Electronics and Communication Engineering, VBIT Scaling of MOS and circuit parameter 95 VIDYA SAGAR P
Department of Electronics and Communication Engineering, VBIT 96 VIDYA SAGAR P

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vlsi-unit-2-ppt.pdf for electronics engineering

  • 1.
    Department of Electronicsand Communication Engineering, VBIT Department of Electronics and Communication Engineering, VBIT UNIT - 2 VLSI CIRCUIT DESIGN PROCESSES P.VIDYA SAGAR ( ASSOCIATE PROFESSOR) VLSI
  • 2.
    Department of Electronicsand Communication Engineering, VBIT Department of Electronics and Communication Engineering, VBIT SYLLABUS UNIT II VLSI CIRCUIT DESIGN PROCESSES: VLSI Design Flow, MOS Layers, Stick Diagrams, Design Rules and Layout, 2 m CMOS Design rules for wires, Contacts and Transistors Layout Diagrams for NMOS and CMOS Inverters and Gates, Scaling of MOS circuits. 2 VIDYA SAGAR P
  • 3.
    Department of Electronicsand Communication Engineering, VBIT Department of Electronics and Communication Engineering, VBIT CONTENTS: ➢ VLSI design flow ➢ MOS layers ➢ Stick Diagrams ➢ Design Rules and Layout diagrams ➢ 2µm Design Rules ➢ Layout Diagrams for Inverter, Logic gates ➢ Scaling of MOS 3 VIDYA SAGAR P
  • 4.
    Department of Electronicsand Communication Engineering, VBIT Department of Electronics and Communication Engineering, VBIT ➢VLSI design flow 4 VIDYA SAGAR P
  • 5.
    Department of Electronicsand Communication Engineering, VBIT Department of Electronics and Communication Engineering, VBIT 5 VIDYA SAGAR P
  • 6.
    Department of Electronicsand Communication Engineering, VBIT Department of Electronics and Communication Engineering, VBIT MOS Layers : There are 4 layers • N-diffusion • P-diffusion • Poly Si • Metal •These layers are isolated by one another by thick or thin silicon dioxide insulating layers. • Thin oxide mask region includes n-diffusion / p-diffusion and transistor channel. 6 VIDYA SAGAR P
  • 7.
    Department of Electronicsand Communication Engineering, VBIT Department of Electronics and Communication Engineering, VBIT Stick Diagrams : ➢ A stick diagram is a cartoon of a layout. ➢ Does show all components/ vias (except possibly tub ties), relative placement. ➢ Does not show exact placement, transistor sizes, wire lengths, wire widths, tub boundaries 7 VIDYA SAGAR P
  • 8.
    Department of Electronicsand Communication Engineering, VBIT Department of Electronics and Communication Engineering, VBIT • Key idea: "Stick figure cartoon" of a layout • Useful for planning layout  relative placement of transistors  assignment of signals to layers  connections between cells  cell hierarchy 8 VIDYA SAGAR P
  • 9.
    Department of Electronicsand Communication Engineering, VBIT Stick Diagrams Metal poly ndiff pdiff Can also draw in shades of gray/line style. VIDYA SAGAR P 9
  • 10.
    Department of Electronicsand Communication Engineering, VBIT Department of Electronics and Communication Engineering, VBIT Rules for Drawing Stick Diagrams : • Metal 1 • Poly Si • N-diffusion • P-diffusion Rule 1: • When two or more sticks of the same type cross or touch other that represents electrical contact. 10 VIDYA SAGAR P
  • 11.
    Department of Electronicsand Communication Engineering, VBIT Department of Electronics and Communication Engineering, VBIT Rule 2: • When two or more sticks of different type cross or touch other there is no electrical contact.(if contact is needed show explicitly) 11 VIDYA SAGAR P
  • 12.
    Department of Electronicsand Communication Engineering, VBIT Department of Electronics and Communication Engineering, VBIT Rule 3: When a poly crosses diffusion it represents MOSFET. If contact is shown it is not transistor. nMOSFET pMOSFET nMOSFET (Depletion Mode) 12 VIDYA SAGAR P
  • 13.
    Department of Electronicsand Communication Engineering, VBIT Department of Electronics and Communication Engineering, VBIT STICK DIAGRAMS P- Diffusion n- Diffusion Poly silicon Metal 1 Contact cut N implant Demarcation line Substrate contact PMOS Enhancement Transistor NMOS Enhancement Transistor NMOS Depletion transistor NPN Bipolar Transistor Buried Contact 13 VIDYA SAGAR P
  • 14.
    Department of Electronicsand Communication Engineering, VBIT Stick diagram Encodings for a simple single metal nMOS process COLOR STICK ENCODING LAYERS MASK LAYOUT ENCODING CIF LAYER Caltech Intermediate Form MONOCROME MONOCROME GREEN RED BLUE BLACK GRAY n-diffusion n+active Thniox Polysilicon Metal 1 Contact cut Overglass NOT APPLICABLE nMOS ONLY YELLOW Implant Buried contact nMOS ONLY BROWN ND NP NM NC NG NI NB VIDYA SAGAR P 14
  • 15.
    Department of Electronicsand Communication Engineering, VBIT Department of Electronics and Communication Engineering, VBIT nMOS Design Style: Step 1:Draw metal VDD and GND rails in parallel leaving sufficient space for circuit components between them. VDD GND Step 2: Thinox (green) paths are drawn between rails for inverter & inverter logic. Vin VOUT VDD GND 15 VIDYA SAGAR P
  • 16.
    Department of Electronicsand Communication Engineering, VBIT Department of Electronics and Communication Engineering, VBIT Step 3: Connect poly over thinox wherever transistor required. 16 VIDYA SAGAR P
  • 17.
    Department of Electronicsand Communication Engineering, VBIT Department of Electronics and Communication Engineering, VBIT Step 4: Connect metal wherever is required and create contact for connection. Vout Vin Vin VOUT VDD GND Depletion mode nMOS 17 VIDYA SAGAR P
  • 18.
    Department of Electronicsand Communication Engineering, VBIT Department of Electronics and Communication Engineering, VBIT VDD GND NMOS INVERTER STICK DIAGRAM D A B S D 18 VIDYA SAGAR P 5 V Dep Vout Enh 0V
  • 19.
    Department of Electronicsand Communication Engineering, VBIT 5 V Dep Vout Enh 0V Vin 5 v 0 V Vin 5 v 19 VIDYA SAGAR P
  • 20.
    Department of Electronicsand Communication Engineering, VBIT Department of Electronics and Communication Engineering, VBIT VDD GND CMOS INVERTER STICK DIAGRAM FIG 1 Supply rails 20 VIDYA SAGAR P
  • 21.
    Department of Electronicsand Communication Engineering, VBIT Department of Electronics and Communication Engineering, VBIT VDD GN D PMOS NMOS S S D D CMOS INVERTER STICK DIAGRAM Fig 2 Drawing Pmos and Nmos Transistors between Supply rails 21 VIDYA SAGAR P
  • 22.
    Department of Electronicsand Communication Engineering, VBIT Department of Electronics and Communication Engineering, VBIT VDD GND PMOS NMOS A S S D D CMOS INVERTER STICK DIAGRAM Fig 3 Combining Gate of Pmos and Nmos Transistors and giving common input With same gate poly silicon metal 22 VIDYA SAGAR P
  • 23.
    Department of Electronicsand Communication Engineering, VBIT Department of Electronics and Communication Engineering, VBIT VDD GND PMOS NMOS A D S S D CMOS INVERTER STICK DIAGRAM Fig 4 Combining Drain pf Pmos and Nmos Transistors to take output with metal 1 23 VIDYA SAGAR P
  • 24.
    Department of Electronicsand Communication Engineering, VBIT Department of Electronics and Communication Engineering, VBIT VDD GND PMOS NMOS D A S S D B CMOS INVERTER STICK DIAGRAM Fig 5 Take the output with the poly silicon metal 24 VIDYA SAGAR P
  • 25.
    Department of Electronicsand Communication Engineering, VBIT Department of Electronics and Communication Engineering, VBIT VDD GND PMOS NMOS D A S S D B CMOS INVERTER STICK DIAGRAM Fig 6 Connect the source of Pmos to VDD and Nmos to GND 25 VIDYA SAGAR P
  • 26.
    Department of Electronicsand Communication Engineering, VBIT Department of Electronics and Communication Engineering, VBIT VDD GND PMOS NMOS D A S S D B CONTACT CMOS INVERTER STICK DIAGRAM Fig 7 Connect the contact cuts where the different metals are connected 26 VIDYA SAGAR P
  • 27.
    Department of Electronicsand Communication Engineering, VBIT Department of Electronics and Communication Engineering, VBIT VDD GND PMOS NMOS D A S S D B CONTACT CMOS INVERTER STICK DIAGRAM Fig 8 Final CMOS Inverter Substrate contact 27 VIDYA SAGAR P
  • 28.
    Department of Electronicsand Communication Engineering, VBIT Alternate Layout of NOT Gate Gnd Vp x x X x Vp Gnd X x X X 28 VIDYA SAGAR P
  • 29.
    Department of Electronicsand Communication Engineering, VBIT NAND GATE Schematic Stick diagram Layout VIDYA SAGAR P 29
  • 30.
    Department of Electronicsand Communication Engineering, VBIT Department of Electronics and Communication Engineering, VBIT VDD GND CMOS NAND GATE STICK DIAGRAM FIG 9 Supply rails 30 VIDYA SAGAR P
  • 31.
    Department of Electronicsand Communication Engineering, VBIT Department of Electronics and Communication Engineering, VBIT VDD GND CMOS NAND GATE STICK DIAGRAM Fig 10 Drawing P and N Diffusion between Supply rails 31 VIDYA SAGAR P
  • 32.
    Department of Electronicsand Communication Engineering, VBIT Department of Electronics and Communication Engineering, VBIT VDD GND S S S D D D D S A B C CMOS NAND GATE STICK DIAGRAM Fig 11 Drawing the poly silicon for two different inputs and identify the source and drain 32 VIDYA SAGAR P
  • 33.
    Department of Electronicsand Communication Engineering, VBIT Department of Electronics and Communication Engineering, VBIT VDD GND S S S D D D D S A B C CMOS NAND GATE STICK DIAGRAM Fig 12 Connect the source of Pmos to VDD and Nmos to GND and subtrate contacts of both 33 VIDYA SAGAR P
  • 34.
    Department of Electronicsand Communication Engineering, VBIT Department of Electronics and Communication Engineering, VBIT VDD GND S S S D D D D S A B C CMOS NAND GATE STICK DIAGRAM Fig 13 Draw the output connections 34 VIDYA SAGAR P
  • 35.
    Department of Electronicsand Communication Engineering, VBIT Department of Electronics and Communication Engineering, VBIT VDD GND S S S D D D D S A B C CMOS NAND GATE STICK DIAGRAM Fig 14 Connect the contact cuts where the different metals are connected 35 VIDYA SAGAR P Gnd Vp b a. a b
  • 36.
    Department of Electronicsand Communication Engineering, VBIT Department of Electronics and Communication Engineering, VBIT 36 Vdd contact Vss contact Vdd Vss Demarcation Line Vout(A nand B) A Ploy(G) Ploy(G) Ploy(G) Ploy(G) s s s s D D D D B Cmos Nor GATE VIDYA SAGAR P
  • 37.
    Department of Electronicsand Communication Engineering, VBIT Cmos Nor GATE VIDYA SAGAR P 37
  • 38.
    Department of Electronicsand Communication Engineering, VBIT VIDYA SAGAR P 38 Power Ground B C Out A
  • 39.
    Department of Electronicsand Communication Engineering, VBIT VIDYA SAGAR P 39 BiCmos inverter Vss contact Vdd Vss Demarcation Line Vout Vdd contact
  • 40.
    Department of Electronicsand Communication Engineering, VBIT Department of Electronics and Communication Engineering, VBIT Encodings for NMOS process: 40 VIDYA SAGAR P
  • 41.
    Department of Electronicsand Communication Engineering, VBIT Encodings for CMOS process: •Figure shows when a n-transistor is formed: a transistor is formed when a green line (n+ diffusion) crosses a red line (poly) completely. •Figure also shows when a p- transistor is formed: a transistor is formed when a yellow line(p+ diffusion) crosses a red line (poly) completely 41 VIDYA SAGAR P
  • 42.
    Department of Electronicsand Communication Engineering, VBIT Encoding for BJT and MOSFETs: layers in an nMOS chip consists of  a p-type substrate  paths of n-type diffusion  a thin layer of silicon dioxide  paths of polycrystalline silicon  a thick layer of silicon dioxide  paths of metal (usually aluminium)  a further thick layer of silicon dioxide 42 VIDYA SAGAR P
  • 43.
    Department of Electronicsand Communication Engineering, VBIT Department of Electronics and Communication Engineering, VBIT LAYOUT 43 VIDYA SAGAR P
  • 44.
    Department of Electronicsand Communication Engineering, VBIT Department of Electronics and Communication Engineering, VBIT 1.Scalable Design Rules (e.g. SCMOS, λ-based design rules): In this approach, all rules are defined in terms of a single parameter λ. The rules are so chosen that a design can be easily ported over a cross section of industrial process ,making the layout portable .Scaling can be easily done by simply changing the value . 2.Absolute Design Rules (e.g. μ-based design rules ) : In this approach, the design rules are expressed in absolute dimensions (e.g.0.75μm) and therefore can exploit the features of a given process to a maximum degree. There are primarily two approaches in describing the design rules 44 VIDYA SAGAR P
  • 45.
    Department of Electronicsand Communication Engineering, VBIT Department of Electronics and Communication Engineering, VBIT What is Via? It is used to connect higher level metals from metal1 connection The direct connections between metal, polysilicon, and diffusion use intermediate layers such as the contact-cut and the buried-contact layers. The entire chip is typically covered with a layer of protective coating called overglass 45 VIDYA SAGAR P
  • 46.
    Department of Electronicsand Communication Engineering, VBIT VIDYA SAGAR P 46 Buried contacts: The buried contact is a method to make direct ohmic contact between the polysilicon gate material and the junctions, in silicon-gate integrated circuits. With this method – requiring an additional masking layer – it was possible to use the polysilicon as an additional layer of interconnection, greatly improving the circuit density, particularly in random logic circuits. Here gate length is dependent upon the alignment of the buried contact mask relative to the poly silicon and therefore vary by ± λ. Butting contact: The gate and source of a depletion device can be connected by a method known as butting contact. Here metal makes contact to both the diffusion forming the source of the depletion transistor and to the poly silicon forming this device’s gate. Its advantage is that no buried contact mask is required and it avoids associated processing.
  • 47.
    Department of Electronicsand Communication Engineering, VBIT CMOS Process Layers Layer Polysilicon Metal1 Metal2 Contact To Poly Contact To Diffusion Via Well (p,n) Active Area (n+,p+) Color Representation Yellow Green Red Blue Magenta Black Black Black Select (p+,n+) Green 47 VIDYA SAGAR P
  • 48.
    Department of Electronicsand Communication Engineering, VBIT Department of Electronics and Communication Engineering, VBIT 2λ 2λ 1λ 2λ 3λ P diffusion N diffusion P diffusion P diffusion N diffusion P diffusion METAL 1 METAL 1 4λ 4λ 3λ 48 VIDYA SAGAR P
  • 49.
    Department of Electronicsand Communication Engineering, VBIT Intra-Layer Design Rules Metal2 4 3 10 9 0 Well Active 3 3 Polysilicon 2 2 Different Potential Same Potential Metal1 3 3 2 Contact or Via Select 2 or 6 2 Hole 49 VIDYA SAGAR P
  • 50.
    Department of Electronicsand Communication Engineering, VBIT Transistor Layout 1 2 5 3 Transistor 50 VIDYA SAGAR P
  • 51.
    Department of Electronicsand Communication Engineering, VBIT Via’s and Contacts 1 2 1 Via Metal to Poly Contact Metal to Active Contact 1 2 5 4 3 2 2 51 VIDYA SAGAR P
  • 52.
    Department of Electronicsand Communication Engineering, VBIT Select Layer 1 3 3 2 2 2 Well Substrate Select 3 5 52 VIDYA SAGAR P
  • 53.
    Department of Electronicsand Communication Engineering, VBIT Department of Electronics and Communication Engineering, VBIT 2λ 4λ 4λ 1λ 2λ 4λ 4λ 1λ 2λ 3λ 53 VIDYA SAGAR P
  • 54.
    Department of Electronicsand Communication Engineering, VBIT Department of Electronics and Communication Engineering, VBIT 2λ 2λ 2λ 2λ 2λ 2λ 2λ 2λ 2λ 2λ 6λ x 6λ 2λ 2λ 2λ 2λ 2λ NMOS ENHANCEMENT PMOS ENHANCEMENT NMOS DEPLETION 54 VIDYA SAGAR P
  • 55.
    Department of Electronicsand Communication Engineering, VBIT Department of Electronics and Communication Engineering, VBIT LAMBDA BSED RULES 55 VIDYA SAGAR P
  • 56.
    Department of Electronicsand Communication Engineering, VBIT Department of Electronics and Communication Engineering, VBIT 56 VIDYA SAGAR P
  • 57.
    Department of Electronicsand Communication Engineering, VBIT Department of Electronics and Communication Engineering, VBIT 57 VIDYA SAGAR P
  • 58.
    Department of Electronicsand Communication Engineering, VBIT Department of Electronics and Communication Engineering, VBIT 58 VIDYA SAGAR P
  • 59.
    Department of Electronicsand Communication Engineering, VBIT Department of Electronics and Communication Engineering, VBIT 59 VIDYA SAGAR P
  • 60.
    Department of Electronicsand Communication Engineering, VBIT Department of Electronics and Communication Engineering, VBIT 60 VIDYA SAGAR P
  • 61.
    Department of Electronicsand Communication Engineering, VBIT Department of Electronics and Communication Engineering, VBIT 61 VIDYA SAGAR P
  • 62.
    Department of Electronicsand Communication Engineering, VBIT Department of Electronics and Communication Engineering, VBIT 62 VIDYA SAGAR P
  • 63.
    Department of Electronicsand Communication Engineering, VBIT Department of Electronics and Communication Engineering, VBIT 63 VIDYA SAGAR P
  • 64.
    Department of Electronicsand Communication Engineering, VBIT Department of Electronics and Communication Engineering, VBIT 64 VIDYA SAGAR P
  • 65.
    Department of Electronicsand Communication Engineering, VBIT Lambda based Design Rules: Design rules include width rules and spacing rules. Mead and Conway developed a set of simplified scalable λ -based design rules, which are valid for a range of fabrication technologies. In these rules, the minimum feature size of a technology is characterized as 2 λ .  All width and spacing rules are specified in terms of the parameter λ . 65 VIDYA SAGAR P
  • 66.
    Department of Electronicsand Communication Engineering, VBIT Design rules for the diffusion layers and metal layers Figure shows the design rule n diffusion, p diffusion, poly, metal1 and metal 2. The n and p diffusion lines is having a minimum width of 2λ and a minimum spacing of 3λ. Similarly it shows for other layers. 66 VIDYA SAGAR P
  • 67.
    Department of Electronicsand Communication Engineering, VBIT Design rules for transistors and gate over hang distance Figure shows the design rule for the transistor, and it also shows that the poly should extend for a minimum of 2λ beyond the diffusion boundaries.(gate over hang distance) 67 VIDYA SAGAR P
  • 68.
    Department of Electronicsand Communication Engineering, VBIT Via VIA is used to connect higher level metals from metal1 connection. Figure shows the design rules for contact cuts and Vias. The design rule for contact is minimum 2λx2λ and same is applicable for a Via. 68 VIDYA SAGAR P
  • 69.
    Department of Electronicsand Communication Engineering, VBIT Buried contact and Butting contact Buried contact is made down each layer to be joined Butting contact The layers are butted together in such a way the two contact cuts become contiguous 69 VIDYA SAGAR P
  • 70.
    Department of Electronicsand Communication Engineering, VBIT CMOS LAMBDA BASED DESIGN RULES: Figure shows the rules to be followed in CMOS well processes to accommodate both n and p transistors 70 VIDYA SAGAR P
  • 71.
    Department of Electronicsand Communication Engineering, VBIT Department of Electronics and Communication Engineering, VBIT CMOS Inverter Layout A A’ n p-substrate Field Oxide p+ n+ In Out GND VDD (a) Layout (b) Cross-Section along A-A’ A A’ 71 VIDYA SAGAR P
  • 72.
    Department of Electronicsand Communication Engineering, VBIT SCHEMATIC AND LAYOUT OF BASIC GATES a) CMOS INVERTER NOT GATE Schematic Stick diagram Layout 72 VIDYA SAGAR P
  • 73.
    Department of Electronicsand Communication Engineering, VBIT The CMOS NOT Gate X X X X Vp Gnd x Gnd n-well Vp x x x Contact Cut 73 VIDYA SAGAR P
  • 74.
    Department of Electronicsand Communication Engineering, VBIT Department of Electronics and Communication Engineering, VBIT Alternate Layout of NOT Gate Gnd Vp x x X x Vp Gnd X x X X 74 VIDYA SAGAR P
  • 75.
    Department of Electronicsand Communication Engineering, VBIT b) NAND GATE Schematic Stick diagram Layout 75 VIDYA SAGAR P
  • 76.
    Department of Electronicsand Communication Engineering, VBIT NAND2 Layout Gnd Vp b a. a b X Vp Gnd X X X X a b b a. 76 VIDYA SAGAR P
  • 77.
    Department of Electronicsand Communication Engineering, VBIT 77 VIDYA SAGAR P
  • 78.
    Department of Electronicsand Communication Engineering, VBIT NOR2 Layout Gnd Vp b a a b X Vp Gnd X X X X a b b a  78 VIDYA SAGAR P
  • 79.
    Department of Electronicsand Communication Engineering, VBIT TRANSMISSION GATE Symbol schematic stick diagram layout 79 VIDYA SAGAR P
  • 80.
    Department of Electronicsand Communication Engineering, VBIT Example: Inverter 80 VIDYA SAGAR P
  • 81.
    Department of Electronicsand Communication Engineering, VBIT Department of Electronics and Communication Engineering, VBIT Inverter, contd.. Layout using Electric 81 VIDYA SAGAR P
  • 82.
    Department of Electronicsand Communication Engineering, VBIT Example: NAND3 •Horizontal N-diffusion and p-diffusion strips •Vertical polysilicon gates •Metal1 VDD rail at top •Metal1 GND rail at bottom •32 by 40 82 VIDYA SAGAR P
  • 83.
    Department of Electronicsand Communication Engineering, VBIT Department of Electronics and Communication Engineering, VBIT NAND3 (using Electric), contd. 83 VIDYA SAGAR P
  • 84.
    Department of Electronicsand Communication Engineering, VBIT Department of Electronics and Communication Engineering, VBIT 84 VIDYA SAGAR P
  • 85.
    Department of Electronicsand Communication Engineering, VBIT Department of Electronics and Communication Engineering, VBIT Scaling • VLSI technology is constantly evolving towards smaller line widths • Reduced feature size generally leads to – better / faster performance – More gate / chip • More accurate description of modern technology is ULSI (ultra large scale integration 85 VIDYA SAGAR P
  • 86.
    Department of Electronicsand Communication Engineering, VBIT Department of Electronics and Communication Engineering, VBIT Scaling Factors • In our discussions we will consider 2 scaling factors, α and β • 1/ β is the scaling factor for VDD and oxide thickness D • 1/ α is scaling factor for all other linear dimensions • We will assume electric field is kept constant 86 VIDYA SAGAR P
  • 87.
    Department of Electronicsand Communication Engineering, VBIT Department of Electronics and Communication Engineering, VBIT Scaling Factors for Device Parameters Simple derivations showing the effects of scaling are derived in Pucknell and Eshraghian pages 125 - 129 It is important that you understand how the following parameters are effected by scaling.  Gate Area  Gate Capacitance per unit area  Gate Capacitance  Charge in Channel  Channel Resistance  Transistor Delay  Maximum Operating Frequency  Transistor Current  Switching Energy  Power Dissipation Per Gate (Static and Dynamic)  Power Dissipation Per Unit Area  Power - Speed Product 87 VIDYA SAGAR P
  • 88.
    Department of Electronicsand Communication Engineering, VBIT Department of Electronics and Communication Engineering, VBIT MOSFET Scaling ❑ Constant Field Scaling ❑ Constant Voltage Scaling ❑ Lateral Scaling ❑SCALING - refers to ordered reduction in dimensions of the MOSFET and other VLSI features ❑Reduce Size of VLSI chips. ❑Change operational characteristics of MOSFETs and parasitic. ❑Physical limits restrict degree of scaling that can be achieved. 88 VIDYA SAGAR P
  • 89.
    Department of Electronicsand Communication Engineering, VBIT Department of Electronics and Communication Engineering, VBIT Constant Field Scaling ❑ The electric field E is kept constant, and the scaled device is obtained by applying a dimensionless scale- factor α (such that E is unchanged): ❑ all dimensions, including those vertical to the surface (1/α) ❑ device voltages (1/α) ❑ the concentration densities (α). 89 VIDYA SAGAR P
  • 90.
    Department of Electronicsand Communication Engineering, VBIT Department of Electronics and Communication Engineering, VBIT Constant Voltage Scaling ❑ Vdd is kept constant. ❑ All dimensions, including those vertical to the surface are scaled. ❑ Concentration densities are scaled. 90 VIDYA SAGAR P
  • 91.
    Department of Electronicsand Communication Engineering, VBIT Department of Electronics and Communication Engineering, VBIT Lateral Scaling ❑ Only the gate length is scaled L = 1/α (gate-shrink). ❑ Year Feature Size(μm) 1980 5.0 1983 3.5 1985 2.5 1987 1.75 1989 1.25 1991 1.0 1993 0.8 1995 0.6 91 VIDYA SAGAR P
  • 92.
    Department of Electronicsand Communication Engineering, VBIT Department of Electronics and Communication Engineering, VBIT PARAMETER SCALING MODEL Constant Constant Lateral Field Voltage Length (L) 1/α 1/α 1/α Width (W) 1/α 1/α 1 Supply Voltage (V) 1/α 1 1 Gate Oxide thickness (tox) 1/α 1/α 1 Junction depth (Xj) 1/α 1/α 1 Current (I) 1/α α α Power Dissipation (P) 1/α2 α α Electric Field 1 α 1 Load Capacitance (C) 1/α 1/α 1/α Gate Delay (T) 1/α 1/α2 1/α2 92 VIDYA SAGAR P
  • 93.
    Department of Electronicsand Communication Engineering, VBIT Department of Electronics and Communication Engineering, VBIT Scaling of Interconnects • Resistance of track R ~ L / wt • R (scaled) ~ (L / α) / ( (w/ α )* (t /α)) • R(scaled) = αR • therefore resistance increases with scaling t w L A B 93 VIDYA SAGAR P
  • 94.
    Department of Electronicsand Communication Engineering, VBIT Department of Electronics and Communication Engineering, VBIT Scaling - Time Constant • Time constant of track connected to gate, • T = R * Cg • T(scaled) = α R * (β / α2) *Cg = (β / α) *R*Cg • Let β = α, therefore T is unscaled! • Therefore delays in tracks don’t reduce with scaling • Therefore as tracks get proportionately larger, effect gets worse • Cross talk between connections gets worse because of reduced spacing 94 VIDYA SAGAR P
  • 95.
    Department of Electronicsand Communication Engineering, VBIT Department of Electronics and Communication Engineering, VBIT Scaling of MOS and circuit parameter 95 VIDYA SAGAR P
  • 96.
    Department of Electronicsand Communication Engineering, VBIT 96 VIDYA SAGAR P