Slide shared is work of renowned Prof. Susanta Sen from Institute of Radio Physics and Electronics, University of Calcutta.
This was presented in NIT Patna by him on the occasion of Foundation day.
Slides contain great approach to VLSI technology from very basics and is really very helpful.
Introduction to CMOS VLSI Design:
This Presentations is design in way to provide basic summary of CMOS Vlsi design
This Presentation is Made at Eutectics.blogspot.in
the following is the structure of presentation :
2: Outline
3: Introduction
4: MOS capacitor
5: Terminal Voltage
6: nMOS Cutoff
7: nMOS Linear
8: nMOS Saturation
9: I-V Characteristics
10 : Channel Charge
11: Carrier velocity
12: nMOS Linear I-V
13: nMOS Saturation
14: nMOS I-V Summary
15: Example
16: pMOS I-V
17: Capacitance
18: Gate Capacitance
19: Diffusion Capacitane
20: Pass Transistor
21: Pass transistor ckts
22: Effective Resistance
23: RC Delay Model
24: RC values
25: Inverter Delay Estimate
Introduction to CMOS VLSI Design:
This Presentations is design in way to provide basic summary of CMOS Vlsi design
This Presentation is Made at Eutectics.blogspot.in
the following is the structure of presentation :
2: Outline
3: Introduction
4: MOS capacitor
5: Terminal Voltage
6: nMOS Cutoff
7: nMOS Linear
8: nMOS Saturation
9: I-V Characteristics
10 : Channel Charge
11: Carrier velocity
12: nMOS Linear I-V
13: nMOS Saturation
14: nMOS I-V Summary
15: Example
16: pMOS I-V
17: Capacitance
18: Gate Capacitance
19: Diffusion Capacitane
20: Pass Transistor
21: Pass transistor ckts
22: Effective Resistance
23: RC Delay Model
24: RC values
25: Inverter Delay Estimate
Dee 6113 CMOS IC DESIGN (Chapter 3 ~ CMOS inverter)MielWitwicky
Question 4
a) Draw a schematic diagram of an inverter.
b) Voltage Transfer Characteristics (VTC) is a plot of output voltage as a function of the input voltage. Draw and label the VTC of a CMOS inverter.
c) The inverter is really the nucleus of all digital design. Once its operation and properties are clearly understood, designing more intricate structures such as NAND gates, address, multipliers, and microprocessors is greatly simplified. Therefore, interpret the properties of static CMOS inverter circuit.
I have prepared it to create an understanding of delay modeling in VLSI.
Regards,
Vishal Sharma
Doctoral Research Scholar,
IIT Indore
vishalfzd@gmail.com
Dee 6113 CMOS IC DESIGN (Chapter 3 ~ CMOS inverter)MielWitwicky
Question 4
a) Draw a schematic diagram of an inverter.
b) Voltage Transfer Characteristics (VTC) is a plot of output voltage as a function of the input voltage. Draw and label the VTC of a CMOS inverter.
c) The inverter is really the nucleus of all digital design. Once its operation and properties are clearly understood, designing more intricate structures such as NAND gates, address, multipliers, and microprocessors is greatly simplified. Therefore, interpret the properties of static CMOS inverter circuit.
I have prepared it to create an understanding of delay modeling in VLSI.
Regards,
Vishal Sharma
Doctoral Research Scholar,
IIT Indore
vishalfzd@gmail.com
Gas Turbine Theory - Principle of Operation and ConstructionSahyog Shishodia
This presentation tells all about basic principle behind Gas Turbine, their working, operation and construction. How they came into existence and where are they used.
A gas turbine, also called a combustion turbine, is a type of internal combustion engine. It has an upstream rotating compressor coupled toa downstream turbine, and a combustion chamber in-between. Energy is added to the gas stream in the combustor, where fuel is mixed with air and ignited. In the high-pressure environment of the combustor, combustion of the fuel increases the temperature. The products of the combustion are forced into the turbine section
Visit https://www.topicsforseminar.com to Download
The presentation covers, Field Effect Transistor: Construction and Characteristic of JFETs, dc biasing of CS, ac analysis of CS amplifier, MOSFET (Depletion and Enhancement)Type, Transfer Characteristic
Final project report on grocery store management system..pdfKamal Acharya
In today’s fast-changing business environment, it’s extremely important to be able to respond to client needs in the most effective and timely manner. If your customers wish to see your business online and have instant access to your products or services.
Online Grocery Store is an e-commerce website, which retails various grocery products. This project allows viewing various products available enables registered users to purchase desired products instantly using Paytm, UPI payment processor (Instant Pay) and also can place order by using Cash on Delivery (Pay Later) option. This project provides an easy access to Administrators and Managers to view orders placed using Pay Later and Instant Pay options.
In order to develop an e-commerce website, a number of Technologies must be studied and understood. These include multi-tiered architecture, server and client-side scripting techniques, implementation technologies, programming language (such as PHP, HTML, CSS, JavaScript) and MySQL relational databases. This is a project with the objective to develop a basic website where a consumer is provided with a shopping cart website and also to know about the technologies used to develop such a website.
This document will discuss each of the underlying technologies to create and implement an e- commerce website.
6th International Conference on Machine Learning & Applications (CMLA 2024)ClaraZara1
6th International Conference on Machine Learning & Applications (CMLA 2024) will provide an excellent international forum for sharing knowledge and results in theory, methodology and applications of on Machine Learning & Applications.
NUMERICAL SIMULATIONS OF HEAT AND MASS TRANSFER IN CONDENSING HEAT EXCHANGERS...ssuser7dcef0
Power plants release a large amount of water vapor into the
atmosphere through the stack. The flue gas can be a potential
source for obtaining much needed cooling water for a power
plant. If a power plant could recover and reuse a portion of this
moisture, it could reduce its total cooling water intake
requirement. One of the most practical way to recover water
from flue gas is to use a condensing heat exchanger. The power
plant could also recover latent heat due to condensation as well
as sensible heat due to lowering the flue gas exit temperature.
Additionally, harmful acids released from the stack can be
reduced in a condensing heat exchanger by acid condensation. reduced in a condensing heat exchanger by acid condensation.
Condensation of vapors in flue gas is a complicated
phenomenon since heat and mass transfer of water vapor and
various acids simultaneously occur in the presence of noncondensable
gases such as nitrogen and oxygen. Design of a
condenser depends on the knowledge and understanding of the
heat and mass transfer processes. A computer program for
numerical simulations of water (H2O) and sulfuric acid (H2SO4)
condensation in a flue gas condensing heat exchanger was
developed using MATLAB. Governing equations based on
mass and energy balances for the system were derived to
predict variables such as flue gas exit temperature, cooling
water outlet temperature, mole fraction and condensation rates
of water and sulfuric acid vapors. The equations were solved
using an iterative solution technique with calculations of heat
and mass transfer coefficients and physical properties.
We have compiled the most important slides from each speaker's presentation. This year’s compilation, available for free, captures the key insights and contributions shared during the DfMAy 2024 conference.
Using recycled concrete aggregates (RCA) for pavements is crucial to achieving sustainability. Implementing RCA for new pavement can minimize carbon footprint, conserve natural resources, reduce harmful emissions, and lower life cycle costs. Compared to natural aggregate (NA), RCA pavement has fewer comprehensive studies and sustainability assessments.
The Internet of Things (IoT) is a revolutionary concept that connects everyday objects and devices to the internet, enabling them to communicate, collect, and exchange data. Imagine a world where your refrigerator notifies you when you’re running low on groceries, or streetlights adjust their brightness based on traffic patterns – that’s the power of IoT. In essence, IoT transforms ordinary objects into smart, interconnected devices, creating a network of endless possibilities.
Here is a blog on the role of electrical and electronics engineers in IOT. Let's dig in!!!!
For more such content visit: https://nttftrg.com/
The Role of Electrical and Electronics Engineers in IOT Technology.pdf
Trends in cmos digital design
1. Jan. 28, 2015 NIT-Patna: Foundation Day 2015 1
CMOS Digital Circuit Design
How to Make Both Ends Meet?
Susanta Sen
Institute of Radio Physics and Electronics
University of Calcutta
2. Jan. 28, 2015 NIT-Patna: Foundation Day 2015 2
Review of
MOS Transistor
3. Jan. 28, 2015 NIT-Patna: Foundation Day 2015 3
The MOS Transistor
4. Jan. 28, 2015 NIT-Patna: Foundation Day 2015 4
MOS Transistor
Zero Bias
5. Jan. 28, 2015 NIT-Patna: Foundation Day 2015 5
MOS Transistor (contd.)
VDS
ID
Channel Pinches off → Current Saturates
VG
Saturation Current increases with VG
Vt
Threshold Voltage Vt → Device Turns ON
MOS can be used as SWITCH
6. Jan. 28, 2015 NIT-Patna: Foundation Day 2015 6
MOS as SWITCH
Designing Logic Circuits
Logic ‘0’ = 0V : Logic ‘1’ = VDD
n-MOS : VG ≤ Vt → OFF : VG = VDD → ON
p-MOS: Negative VGS required
Connect Source to VDD
Gate Voltage → Negative w.r.t. Channel
VG ≥ VDD– |Vt| → OFF : VG = 0 → ON
S
VDD
VG0 to VDD D
G
7. Jan. 28, 2015 NIT-Patna: Foundation Day 2015 7
n-MOS SWITCH
Transferring Logic ‘1’ (VDD):
VDD
Vin = VDD Vt
VDD
Vo
t
Transistor
OFF
Source
Impedance
High
Weak ‘1’
Transistor
ON
Source
Impedance
Low
Strong ‘0’VDD
Vin = 0 V
Vo
t
VDD
Transferring Logic ‘0’ (0 V):
8. Jan. 28, 2015 NIT-Patna: Foundation Day 2015 8
p – MOS Switch
Transferring Logic ‘1’ (VDD):
VDD
Vo
t
0V
VDD Strong ‘1’
Transferring Logic ‘0’ (0 V):
0V
0 V
t
Vo
VDD
Vt
Weak ‘0’
9. Jan. 28, 2015 NIT-Patna: Foundation Day 2015 9
CMOS Logic
• Use n-MOS to produce Logic ‘0’ → Pull DOWN
• Use p-MOS to produce Logic ‘1’ → Pull UP
The CMOS Inverter
Equivalent
Circuit
Logic ‘1’
Output
Logic ‘0’
Output
10. Jan. 28, 2015 NIT-Patna: Foundation Day 2015 10
Switching Theory
Revisited
MOS Circuit Design
Digital Logic
11. Jan. 28, 2015 NIT-Patna: Foundation Day 2015 11
Review of Switching Theory
C
A B
F = C iff (A and B)
Switches in Series
A
B
C F = C iff (A or B)
Switches in Parallel
12. Jan. 28, 2015 NIT-Patna: Foundation Day 2015 12
Using n-MOS Switch
Constraint : C = ‘0’
A B
Series Connection
C = ‘0’ F = ‘0’ when (A . B) is TRUE
⇒ A nand B
A
B
C = ‘0’ F = ‘0’ when (A or B) is TRUE
⇒ A nor B
Parallel Connection
13. Jan. 28, 2015 NIT-Patna: Foundation Day 2015 13
Using p-MOS Switch
Constraint : C = ‘1’
A B
C = ‘1’ F = ‘1’ when ( A . B) is TRUE
⇒ A + B
Series Connection
C = ‘1’
A
B
F = ‘1’ when ( A + B) is TRUE
⇒ A . B
Parallel Connection
14. Jan. 28, 2015 NIT-Patna: Foundation Day 2015 14
CMOS Logic Design
• Pull UP Network
– Build using p-MOS
– Turns ON when Function is TRUE
• Pull DOWN Network
– Build using n-MOS
– Turns ON when Function is FALSE
• Operationally Complement
• Topologically Dual
15. Jan. 28, 2015 NIT-Patna: Foundation Day 2015 15
CMOS Logic (contd.)
A
A
B
BA
A
B
B
F
F
NAND GateNOR Gate
16. Jan. 28, 2015 NIT-Patna: Foundation Day 2015 16
CMOS Design Example
Consider the Function
f = A . (B + C)
Design the
Pull Down
Network first
A
B C
PullUp
F
B
A
C
f = [A . (B + C)] is true
The Pull Down Network connects
‘f ’ to ground when
Connect Ground
17. Jan. 28, 2015 NIT-Patna: Foundation Day 2015 17
Assignments
1. F = A.B + C
2. F = (A + B).(C + D)
3. F = A + B.C
4. F = A + B.C
5. F = A.C + B.C
6. F = A ⊕ B
19. Jan. 28, 2015 NIT-Patna: Foundation Day 2015 19
V
DD
VO
Vi
(=VG)
MOS Amplifier
VDS
ID
V
DD
VG
Vi
VO
Load Line
RL
ID
VO = VDD – ID.RL
VDD
20. Jan. 28, 2015 NIT-Patna: Foundation Day 2015 20
Non Linear Load
VDSVDD
ID
VDD
VO
Vi
LOAD LINEVO= VDD – Vdiode
VO
Vi
VDD
21. Jan. 28, 2015 NIT-Patna: Foundation Day 2015 21
Non Linear Load (contd.)
Vi
VO
VB
VDD
VDD
VDS
ID
VDD
VO
Vi
22. Jan. 28, 2015 NIT-Patna: Foundation Day 2015 22
The CMOS InverterAmplifier or Inverter ?
Vi VO
VO
Vi
Gate Bias of PMOS changes with
Input Voltage
VDD
VDD
VDS
ID
VDD
23. Jan. 28, 2015 NIT-Patna: Foundation Day 2015 24
A Closer Look
In presence of Noise
VOn = f (Vi + vn)
= f (Vi) + vn(∂VO/∂Vi) + vn
2
(∂2
VO/∂Vi
2
)+…VO
Vi
noisy_output = noiseless_output +
noise x gain + higher order terms
VO= f (Vi) → Gain =
∂VO/∂Vi
ViHViL
VOL
VOH
Digital → Noise immunity Analog → High Gain
24. Jan. 28, 2015 NIT-Patna: Foundation Day 2015 25
Noise Margins
VO
Vi
ViHViL
VOL
VOH
Digital → Noise immunity
NML = VIL – VOL
NMH = VOH – VIH
VOH
ViH
1 {
VOL
ViL
0 {
Undefined
Region
25. Jan. 28, 2015 NIT-Patna: Foundation Day 2015 26
Vi VO
VO
Vi
VDD
VDD
VDS
ID
VDD
Tuning the Characteristics
• Make the n-MOS wider
• It conducts more current
ID = ½ µCox[VGS – Vt]2
(W/L)
•Best Noise Margin
•When Vi = Voat VDD/2
•Wp = 3.Wn
26. Jan. 28, 2015 NIT-Patna: Foundation Day 2015 27
When the Signal Changes!
The CMOS Inverter
Logic ‘1’
Output
VDD
Vo
t Logic ‘0’
Output
Vo
t
VDD
Energy dissipated in
Pull Up Network
Energy dissipated in
Pull Down Network
27. Jan. 28, 2015 NIT-Patna: Foundation Day 2015 30
A Second Look at Changing Signals!
The CMOS Inverter
Logic ‘1’
Output
VDD
Vo
t Logic ‘0’
Output
Vo
t
VDD
Takes Time to change → Propagation Delay
28. Jan. 28, 2015 NIT-Patna: Foundation Day 2015 31
Attention to Speed
• p-MOS slower than n-MOS
– Hole mobility < Electron mobility
– Pull-UP → Higher Resistance
– Rise time longer
• Make p-MOS wider
– Resistance α W/L Ratio
– Wp = n. Wn → n = √µn /µp ≅ 2
• Widen transistors connected in Series
– Increases Input Capacitance
• Avoid Series connection of p-MOS
– Prefer NAND over NOR
29. Jan. 28, 2015 NIT-Patna: Foundation Day 2015 32
∀µn / µp → 2.7
• p-MOS wider than n-MOS
– Wp/Wn = 3 → symmetric characteristics
• Best Noise Margin
• Increased Capacitive Load
– Reduced speed
• Wp/Wn = 2 → Best speed
• Design is a trade-off
– Speed & Robustness
CMOS Logic Design
30. Jan. 28, 2015 NIT-Patna: Foundation Day 2015 33
LH
SO
E
k
HH
LH
SO
2 fold degenerate valence band
E
kHH
• Light hole (LH) band moves upward
→ higher probability of occupancy
• Low effective mass → higher mobility
• Tunable mobility
Promise of Strained Si
31. Jan. 28, 2015 NIT-Patna: Foundation Day 2015 34
aSi=5.43A
aGe= 5.64 Å
Si
Substrate
Ge epitaxial layer
Tensile strain
%2.4
0
0
=
−
=
a
aa
ε
Si – Ge hetero-structures
aSi= 5.43 Å
Compressive strain
32. Jan. 28, 2015 NIT-Patna: Foundation Day 2015 35
• Si1-xGex has a bulk relaxed lattice
constant smaller than Ge.
• Strain decreases
Strain Engineering: Si1-xGex alloy
SiGe epitaxial layer
Si Substrate Tensile strain
Compressive strain
33. Jan. 28, 2015 NIT-Patna: Foundation Day 2015 36
Virtual substrate for strained-Si
• Strained layers grow up to a critical thickness
• Beyond Critical thickness → misfit dislocations appear
• As more layers grow → strain relaxes and defects reduce
Strain relaxed Si-Ge
Virtual Substrate
Tensile Strained Si epitaxial layer
34. HRTEM image of Strained Si
on Virtual Substrate
Strained-Si
SiGe (X % Ge) buffer cap,
0.9 µm
X % Ge
0.0%Ge
Step graded SiGe
buffer, 2.1 µm
Si buffer, 0.5 µm
n-Si (100) substrate
HRTEM
35. Jan. 28, 2015 NIT-Patna: Foundation Day 2015 38
Ref: S. Takagi et al., ISSCC (2003) p. 376
Mobility enhancement with strain
36. Jan. 28, 2015 NIT-Patna: Foundation Day 2015 39
Strained Si Layer Structure
• Strained-Si PMOS layer
structure
• Type-II Band Alignment
– before charge sharing
– after charge sharing at
Zero bias
– Biased to inversion
Si1-xGex
Relaxed
Strained-Si
SiO2
(a)
EC
EV
(b)
EC
EV(d)
EC
EV
(c)
Poly-Si
37. Jan. 28, 2015 NIT-Patna: Foundation Day 2015 40
The Device Capacitance Model
EC
EV
EC
EV
Si1-xGex
Relaxed
SiO2
(a)
Poly-Si
Strained-Si
C1
C2
C3
STI
Channel
Strained-Si
Si1-xGex
C4Source /
Drain
38. Jan. 28, 2015 NIT-Patna: Foundation Day 2015 41
Design Optimization
• NMOS → Min. size : WN = 3λ
• PMOS → WP varied from 3λ to 9λ
• Calculate
–Propagation delay
–Shift from symmetry |(VDD/2 – Logic threshold)|
• Repeat for different strains (%Ge in VS)
• Converge (for same WP)
–Min. propagation delay &
–Min. shift from symmetry
39. Jan. 28, 2015 NIT-Patna: Foundation Day 2015 42
Parameter Values
(250 nm technology)
Parameter Value
Dielectric Constant (Si1 x‑
Gex
) 11.9 + 4x
Grading Coefficient (m)
Bottom → 0.48
Side Wall → 0.32
µ Cox
(Bulk)
Electron → 150 X 10-6
AV-2
Hole → 30 X 10-6
AV-2
VDD
2.5 V
|VT
|
n-MOS → 0.43 V
p-MOS → 0.40 V
Channel Length Modulation
Parameter
n-MOS → 0.06 V-1
p-MOS → 0.10 V-1
40. Jan. 28, 2015 NIT-Patna: Foundation Day 2015 44
30% Ge
13.0
13.5
14.0
14.5
15.0
15.5
3 5 7 9
P-transistor width (lamda)
Propagationdelay
(nS)
0
50
100
150
200
250
300
350
400
Shiftfromsymmetry
(mV)
30% Ge composition
43. Min. shift from symmetry
Min. Propagation delay
Summary
40% Ge in VS is most optimum
Conclusion
4
5
6
7
8
0.25 0.35 0.45
Ge composition (x)
P-TransistorWidth
(lambda)
S. Sen, S. Chattopadhyay, B. Mukhopadhyay; CODEC-2012