Trends in cmos digital design

Jan. 28, 2015 NIT-Patna: Foundation Day 2015 1
CMOS Digital Circuit Design
How to Make Both Ends Meet?
Susanta Sen
Institute of Radio Physics and Electronics
University of Calcutta

Review of
MOS Transistor

The MOS Transistor

MOS Transistor
Zero Bias

MOS Transistor (contd.)
VDS
ID
Channel Pinches off → Current Saturates
VG
Saturation Current increases with VG
Vt
Threshold Voltage Vt → Device Turns ON
MOS can be used as SWITCH

MOS as SWITCH
Designing Logic Circuits
Logic ‘0’ = 0V : Logic ‘1’ = VDD
n-MOS : VG ≤ Vt → OFF : VG = VDD → ON
p-MOS: Negative VGS required
Connect Source to VDD
Gate Voltage → Negative w.r.t. Channel
VG ≥ VDD– |Vt| → OFF : VG = 0 → ON
S
VDD
VG0 to VDD D
G

n-MOS SWITCH
Transferring Logic ‘1’ (VDD):
VDD
Vin = VDD Vt
VDD
Vo
t
Transistor
OFF
Source
Impedance
High
Weak ‘1’
Transistor
ON
Source
Impedance
Low
Strong ‘0’VDD
Vin = 0 V
Vo
t
VDD
Transferring Logic ‘0’ (0 V):

p – MOS Switch
Transferring Logic ‘1’ (VDD):
VDD
Vo
t
0V
VDD Strong ‘1’
Transferring Logic ‘0’ (0 V):
0V
0 V
t
Vo
VDD
Vt
Weak ‘0’

CMOS Logic
• Use n-MOS to produce Logic ‘0’ → Pull DOWN
• Use p-MOS to produce Logic ‘1’ → Pull UP
The CMOS Inverter
Equivalent
Circuit
Logic ‘1’
Output
Logic ‘0’
Output

Switching Theory
Revisited
MOS Circuit Design
Digital Logic

Review of Switching Theory
C
A B
F = C iff (A and B)
Switches in Series
A
B
C F = C iff (A or B)
Switches in Parallel

Using n-MOS Switch
Constraint : C = ‘0’
A B
Series Connection
C = ‘0’ F = ‘0’ when (A . B) is TRUE
⇒ A nand B
A
B
C = ‘0’ F = ‘0’ when (A or B) is TRUE
⇒ A nor B
Parallel Connection

Using p-MOS Switch
Constraint : C = ‘1’
A B
C = ‘1’ F = ‘1’ when ( A . B) is TRUE
⇒ A + B
Series Connection
C = ‘1’
A
B
F = ‘1’ when ( A + B) is TRUE
⇒ A . B
Parallel Connection

CMOS Logic Design
• Pull UP Network
– Build using p-MOS
– Turns ON when Function is TRUE
• Pull DOWN Network
– Build using n-MOS
– Turns ON when Function is FALSE
• Operationally Complement
• Topologically Dual

CMOS Logic (contd.)
A
A
B
BA
A
B
B
F
F
NAND GateNOR Gate

CMOS Design Example
Consider the Function
f = A . (B + C)
Design the
Pull Down
Network first
A
B C
PullUp
F
B
A
C
f = [A . (B + C)] is true
The Pull Down Network connects
‘f ’ to ground when
Connect Ground

Assignments
1. F = A.B + C
2. F = (A + B).(C + D)
3. F = A + B.C
4. F = A + B.C
5. F = A.C + B.C
6. F = A ⊕ B

Steady State
Input-Output Characteristics

V
DD
VO
Vi
(=VG)
MOS Amplifier
VDS
ID
V
DD
VG
Vi
VO
Load Line
RL
ID
VO = VDD – ID.RL
VDD

Non Linear Load
VDSVDD
ID
VDD
VO
Vi
LOAD LINEVO= VDD – Vdiode
VO
Vi
VDD

Non Linear Load (contd.)
Vi
VO
VB
VDD
VDD
VDS
ID
VDD
VO
Vi

The CMOS InverterAmplifier or Inverter ?
Vi VO
VO
Vi
Gate Bias of PMOS changes with
Input Voltage
VDD
VDD
VDS
ID
VDD

A Closer Look
In presence of Noise
VOn = f (Vi + vn)
= f (Vi) + vn(∂VO/∂Vi) + vn
2
(∂2
VO/∂Vi
2
)+…VO
Vi
noisy_output = noiseless_output +
noise x gain + higher order terms
VO= f (Vi) → Gain =
∂VO/∂Vi
ViHViL
VOL
VOH
Digital → Noise immunity Analog → High Gain

Noise Margins
VO
Vi
ViHViL
VOL
VOH
Digital → Noise immunity
NML = VIL – VOL
NMH = VOH – VIH
VOH
ViH
1 {
VOL
ViL
0 {
Undefined
Region

Vi VO
VO
Vi
VDD
VDD
VDS
ID
VDD
Tuning the Characteristics
• Make the n-MOS wider
• It conducts more current
ID = ½ µCox[VGS – Vt]2
(W/L)
•Best Noise Margin
•When Vi = Voat VDD/2
•Wp = 3.Wn

When the Signal Changes!
The CMOS Inverter
Logic ‘1’
Output
VDD
Vo
t Logic ‘0’
Output
Vo
t
VDD
Energy dissipated in
Pull Up Network
Energy dissipated in
Pull Down Network

A Second Look at Changing Signals!
The CMOS Inverter
Logic ‘1’
Output
VDD
Vo
t Logic ‘0’
Output
Vo
t
VDD
Takes Time to change → Propagation Delay

Attention to Speed
• p-MOS slower than n-MOS
– Hole mobility < Electron mobility
– Pull-UP → Higher Resistance
– Rise time longer
• Make p-MOS wider
– Resistance α W/L Ratio
– Wp = n. Wn → n = √µn /µp ≅ 2
• Widen transistors connected in Series
– Increases Input Capacitance
• Avoid Series connection of p-MOS
– Prefer NAND over NOR

∀µn / µp → 2.7
• p-MOS wider than n-MOS
– Wp/Wn = 3 → symmetric characteristics
• Best Noise Margin
• Increased Capacitive Load
– Reduced speed
• Wp/Wn = 2 → Best speed
• Design is a trade-off
– Speed & Robustness
CMOS Logic Design

LH
SO
E
k
HH
LH
SO
2 fold degenerate valence band
E
kHH
• Light hole (LH) band moves upward
→ higher probability of occupancy
• Low effective mass → higher mobility
• Tunable mobility
Promise of Strained Si

aSi=5.43A
aGe= 5.64 Å
Si
Substrate
Ge epitaxial layer
Tensile strain
%2.4
0
0
=
−
=
a
aa
ε
Si – Ge hetero-structures
aSi= 5.43 Å
Compressive strain

• Si1-xGex has a bulk relaxed lattice
constant smaller than Ge.
• Strain decreases
Strain Engineering: Si1-xGex alloy
SiGe epitaxial layer
Si Substrate Tensile strain
Compressive strain

Virtual substrate for strained-Si
• Strained layers grow up to a critical thickness
• Beyond Critical thickness → misfit dislocations appear
• As more layers grow → strain relaxes and defects reduce
Strain relaxed Si-Ge
Virtual Substrate
Tensile Strained Si epitaxial layer

HRTEM image of Strained Si
on Virtual Substrate
Strained-Si
SiGe (X % Ge) buffer cap,
0.9 µm
X % Ge
0.0%Ge
Step graded SiGe
buffer, 2.1 µm
Si buffer, 0.5 µm
n-Si (100) substrate
HRTEM

Ref: S. Takagi et al., ISSCC (2003) p. 376
Mobility enhancement with strain

Strained Si Layer Structure
• Strained-Si PMOS layer
structure
• Type-II Band Alignment
– before charge sharing
– after charge sharing at
Zero bias
– Biased to inversion
Si1-xGex
Relaxed
Strained-Si
SiO2
(a)
EC
EV
(b)
EC
EV(d)
EC
EV
(c)
Poly-Si

The Device Capacitance Model
EC
EV
EC
EV
Si1-xGex
Relaxed
SiO2
(a)
Poly-Si
Strained-Si
C1
C2
C3
STI
Channel
Strained-Si
Si1-xGex
C4Source /
Drain

Design Optimization
• NMOS → Min. size : WN = 3λ
• PMOS → WP varied from 3λ to 9λ
• Calculate
–Propagation delay
–Shift from symmetry |(VDD/2 – Logic threshold)|
• Repeat for different strains (%Ge in VS)
• Converge (for same WP)
–Min. propagation delay &
–Min. shift from symmetry

Parameter Values
(250 nm technology)
Parameter Value
Dielectric Constant (Si1 x‑
Gex
) 11.9 + 4x
Grading Coefficient (m)
Bottom → 0.48
Side Wall → 0.32
µ Cox
(Bulk)
Electron → 150 X 10-6
AV-2
Hole → 30 X 10-6
AV-2
VDD
2.5 V
|VT
|
n-MOS → 0.43 V
p-MOS → 0.40 V
Channel Length Modulation
Parameter
n-MOS → 0.06 V-1
p-MOS → 0.10 V-1

30% Ge
13.0
13.5
14.0
14.5
15.0
15.5
3 5 7 9
P-transistor width (lamda)
Propagationdelay
(nS)
0
50
100
150
200
250
300
350
400
Shiftfromsymmetry
(mV)
30% Ge composition

35% Ge
12.0
12.2
12.4
12.6
12.8
13.0
13.2
13.4
13.6
13.8
14.0
3 5 7 9
Propagationdelay
(nS)
0
50
100
150
200
250
300
350
Shiftfromsymmetry
(mV)
35% Ge composition

40% Ge
10.8
11.0
11.2
11.4
11.6
11.8
12.0
12.2
12.4
3 5 7 9
Propagationdelay
(nS)
0
50
100
150
200
250
300
Shiftfromsymmetry
(mV)
40% Ge composition

Min. shift from symmetry
Min. Propagation delay
Summary
40% Ge in VS is most optimum
Conclusion
4
5
6
7
8
0.25 0.35 0.45
Ge composition (x)
P-TransistorWidth
(lambda)
S. Sen, S. Chattopadhyay, B. Mukhopadhyay; CODEC-2012

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