pull up to pull down ratio of nmos inverter driven by another nmos inverter and also another describing with pass transistor. Transistor sizing with example and some formulas

1. Presentation Outcomes
Determination of Pull-Up to Pull-Down Ratio
(Zp.u./Zp.d.) for an Nmos Inverter driven by another
Nmos Inverter.
Determination of Pull-Up to Pull-Down Ratio for an
Nmos Inverter driven through one or more pass
transistor.
Transistor Sizing

2. Determination of Pull-Up to Pull-Down Ratio
(Zp.u./Zp.d.) for an Nmos Inverter driven by
another Nmos Inverter.
 Consider the arrangement in figure 2.8 in which an inverter is driven
from the output of another similar inverter. Consider the depletion
mode transistor for which Vgs = 0 under all conditions, and further
assume that in order to cascade inverters without degradation of levels
we are aiming to meet the requirement
Vin = Vout = Vinv
Figure 2,8 Nmos inverter driven directly by another inverter

3.  For equal margins around the inverter threshold, we set Vinv = 0.5VDD. At this point
both transistors are in saturation and
Ids = K W (Vgs – Vt)2
L 2
 In the depletion mode:
Ids = K Wp.u. (– Vtd)2 since Vgs = 0
Lp.u. 2
 In the enhancement mode:
Ids = K Wp.u. (Vinv – Vtd)2 since Vgs = Vinv
Lp.u. 2
 Equating (since currents are the same) we have
K Wp.u. (Vinv – Vtd)2 = K Wp.u. (– Vtd)2
Lp.u. 2 Lp.u. 2

4.  Where Wp.d., Lp.d., Wp.u. and Lp.u. are the widths and lengths of the pull-down
and pull-up transistors respectively.
Now write
Zp.d. = Lp.d.
Wp.d.
Zp.u. = Lp.u.
Wp.u.
 we have
1 (Vinv – Vt)2 = 1 (-Vtd)2
Zp.d. Zp.u.
 whence
Vinv = Vt - Vtd
(Zp.u./Zp.d.)-2 equation (2.9)

5.  Now we can substitute typical values as follows:
Vt = 0.2VDD ; Vtd = -0.6VDD
Vinv = 0.5VDD (for equal margins)
 thus, from equation (2.9)
0.5 = 0.2 + 0.6
(Zp.u./Zp.d.)-2
 whence
(Zp.u./Zp.d.)-2 = 2
Squaring on both the sides we get:
Zp.u./Zp.d. = 4/1
 Thus, the L:W of (p.u.) Transistor must be in such proportion with respect
to another (p.d.) Transistor

6. Determination of Pull-Up to Pull-Down Ratio
(Zp.u./Zp.d.) for an Nmos Inverter driven through
one or more pass transistor

12. Transistor Sizing
 Transistor sizing is the operation of enlarging (or reducing) the width of
the channel of a transistor.
 It is an effective technique to improve the delay of a CMOS circuit.
 When the width of the channel is increased, the current drive capability of
the transistor increases which reduces the signal rise/fall times at the gate
output.
 The active area, i.e., the area occupied by active devices (e.g., transistors)
increases with increased transistor sizes, and the layout area may increase
as the complexity of the circuit increases and thus to overcome this
transistor sizing is done.

13. Transistor Sizing
R ∞
𝐿
𝐴
R = 𝜌
𝐿
𝐴
R =
𝜌
𝑥𝑑
∗
𝐿
𝑊
R ∞
𝐿
𝑊
I ∞
𝑊
𝐿
(Since, R ∞ 1/I )
R ∞
1
(𝑤/𝐿)

14. Some Formulas
R
(
𝐿
𝑊
)eq
Series n (
𝐿
𝑊
)eq
Parallel
1
𝑛
(
𝐿
𝑊
)eq
I
(
𝑊
𝐿
)eq
1
𝑛
(
𝑊
𝐿
)eq
n (
𝑊
𝐿
)eq

15. Example:
Find
𝑊
𝐿
peq and
𝑊
𝐿
𝑛eq where,
𝑊
𝐿
p = 2 and
𝑊
𝐿
n = 1
Pmos Section
𝑊
𝐿
peq =
𝑊
𝐿
AB
=
𝑊
𝐿
A +
𝑊
𝐿
B
= 2 + 2
= 4

16. Example:
Find
𝑊
𝐿
peq and
𝑊
𝐿
𝑛eq where,
𝑊
𝐿
p = 2 and
𝑊
𝐿
n = 1
Nmos Section
𝑊
𝐿
Neq =1/(
𝑊
𝐿
AB)
= 1/ ( (
1
𝑊
𝐿
A
) + (
1
𝑊
𝐿
B
))
= 1/ (½+ ½)
= ½

17. Final Sizing
𝑊
𝐿
peq = 2
𝑊
𝐿
Neq = ½

18. Summary
 Explained basic nmos inverter with its characteristics
 Explained determination of Pull-Up to Pull-Down Ratio
(Zp.u./Zp.d.) for an Nmos Inverter driven by another Nmos
Inverter.
 Explained determination of Pull-Up to Pull-Down Ratio
for an Nmos Inverter driven through one or more pass
transistor.
 Explained what is transistor sizing with some examples

19. Thank You