The document proposes designs for ternary logic gates based on single power supply voltage for CMOS technology. It describes the design of a simple ternary inverter (STI), negative ternary inverter (NTI), and positive ternary inverter (PTI) using only enhancement-type MOSFETs. Transistor widths and lengths are optimized to achieve the desired voltage transfer characteristics. Basic ternary logic gates including a ternary NAND (TNAND) and ternary NOR (TNOR) are also designed using a similar single-transistor approach. The proposed gate designs aim to reduce transistor count and power consumption compared to prior ternary logic designs.
Router 1X3 – RTL Design and VerificationIJERD Editor
Routing is the process of moving a packet of data from source to destination and enables messages
to pass from one computer to another and eventually reach the target machine. A router is a networking device
that forwards data packets between computer networks. It is connected to two or more data lines from different
networks (as opposed to a network switch, which connects data lines from one single network). This paper,
mainly emphasizes upon the study of router device, it‟s top level architecture, and how various sub-modules of
router i.e. Register, FIFO, FSM and Synchronizer are synthesized, and simulated and finally connected to its top
module.
vlsi projects using verilog code 2014-2015E2MATRIX
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Router 1X3 – RTL Design and VerificationIJERD Editor
Routing is the process of moving a packet of data from source to destination and enables messages
to pass from one computer to another and eventually reach the target machine. A router is a networking device
that forwards data packets between computer networks. It is connected to two or more data lines from different
networks (as opposed to a network switch, which connects data lines from one single network). This paper,
mainly emphasizes upon the study of router device, it‟s top level architecture, and how various sub-modules of
router i.e. Register, FIFO, FSM and Synchronizer are synthesized, and simulated and finally connected to its top
module.
vlsi projects using verilog code 2014-2015E2MATRIX
E2MATRIX Research Lab
Are you scratching your head to write your M Tech thesis?
Don’t know where to start and where to find the relevant matter on the topic?
We Provide Complete Thesis Help For M.Tech / Phd Studnets.
E2MATRIX deals with Thesis guidance and research work for M.Tech, PhD Students.
If you are looking for professional thesis guidance then of course you are at the right place. We have a best team of Technical Developers and professionals who specialize in developing and delivering best and authenticated work with an assurance of on time delivery.
Contact : +91 9041262727, 9779363902.
Email : support@e2matrix.com
Web : www.e2matrix.com
This book guides the beginner to start up with Embedded C programming using MP LAB . This Book covers all interfacing examples with pic micro controller and guides beginners to develop projects on PIC micro controller
This presentation has given a brief introduction and working of CMOS Logic Structures which includes MOS logic, CMOS logic, CMOS logic structure, CMOS complementary logic, pass transistor logic, bi CMOS logic, pseudo –nMOS logic, CMOS domino logic, Cascode Voltage Switch Logic(CVSL), clocked CMOS logic(c²mos), dynamic CMOS logic
Low Power VLSI design architecture for EDA (Electronic Design Automation) and Modern Power Estimation, Reduction and Fixing technologies including clock gating and power gating
I have prepared it to create an understanding of delay modeling in VLSI.
Regards,
Vishal Sharma
Doctoral Research Scholar,
IIT Indore
vishalfzd@gmail.com
This presentation discusses the basics of Pass Transistor Logic, its advantages, limitation and finally implementation of Boolean functions/Combinational Logic circuits using Pass Transistor Logic.
Routing in Integrated circuits is an important task which requires extreme care while placing the modules and circuits and connecting them with each other.
FPGA are a special form of Programmable logic devices(PLDs) with higher densities as compared to custom ICs and capable of implementing functionality in a short period of time using computer aided design (CAD) software....by mathewsubin3388@gmail.com
This book guides the beginner to start up with Embedded C programming using MP LAB . This Book covers all interfacing examples with pic micro controller and guides beginners to develop projects on PIC micro controller
This presentation has given a brief introduction and working of CMOS Logic Structures which includes MOS logic, CMOS logic, CMOS logic structure, CMOS complementary logic, pass transistor logic, bi CMOS logic, pseudo –nMOS logic, CMOS domino logic, Cascode Voltage Switch Logic(CVSL), clocked CMOS logic(c²mos), dynamic CMOS logic
Low Power VLSI design architecture for EDA (Electronic Design Automation) and Modern Power Estimation, Reduction and Fixing technologies including clock gating and power gating
I have prepared it to create an understanding of delay modeling in VLSI.
Regards,
Vishal Sharma
Doctoral Research Scholar,
IIT Indore
vishalfzd@gmail.com
This presentation discusses the basics of Pass Transistor Logic, its advantages, limitation and finally implementation of Boolean functions/Combinational Logic circuits using Pass Transistor Logic.
Routing in Integrated circuits is an important task which requires extreme care while placing the modules and circuits and connecting them with each other.
FPGA are a special form of Programmable logic devices(PLDs) with higher densities as compared to custom ICs and capable of implementing functionality in a short period of time using computer aided design (CAD) software....by mathewsubin3388@gmail.com
Flash-based audio and video communicationKundan Singh
Modern multimedia communication systems have roots in several different technologies: transporting video over phone lines, using multicast on Internet2's Mbone, adding video session to VoIP or instant messaging, or adding interactive mode in existing streaming systems. Adobe's Flash Player has emerged as the most popular web platform for video content and used by almost all web users. More recently, several companies have attempted Flash-based interactive video communication. The high level abstractions offered by Flash Player and Flex framework significantly eases the development of video applications.
This talk will present the differences in video communication technologies, how it is being deployed in practice using the Flash platform, shedding some light on many confusions about what works and what does not, and how can Flash video work with standards such as SIP and HTML 5. This developer focused presentation will walk you through what it takes to build a Flash-based video communication system using example code.
Doclick Solutions offering IEEE projects for final year students in the below domain IN OUR R&D DIVISION,
Networking
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Data Mining
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Image Processing
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Wireless Networks
Hadoop Big Data
Mobile Computing, Etc...
We Provide Projects on Following Topics:
IEEE Projects 2014,2015,2016.
Application Projects (PHP, JAVA/J2EE, ANDROID)
HAM 1032 Combining the Power of IBM API Management and IBM Integration BusKaren Broughton-Mabbitt
Presented at InterConnect 2016 by Carsten Bornert and Ulas Cubuk. This session will discuss the power of combining IBM API Management and IBM Integration Bus together to expose core backend systems in a controlled, managed and secured manner. It will also explore common use cases where these technologies are used together to provide a compelling solution.
A new algorithm for data compression technique using vlsiTejeswar Tej
HOW COMPRESSION IS POSSIBLE?????????
NOW A DAYS LOT OF ALGORITHMS ARE READY TO COMPRESS DATA BUT POWER IS THE MAJOR CRITERIA OF ALL.BUT MY PROJECT IS TO OVERCOME IT I..E THE NEW ALGORITHM BY
K-RLE
Design of Quaternary Logical Circuit Using Voltage and Current Mode LogicVLSICS Design
In VLSI technology, designers main concentration were on area required and on performance of the device. In VLSI design power consumption is one of the major concerns due to continuous increase in chip density and decline in size of CMOS circuits and frequency at which circuits are operating. By considering these parameter logical circuits are designed using quaternary voltage mode logic and quaternary current mode logic. Power consumption required for quaternary voltage mode logic is 51.78 % less as compared to binary . Area in terms of number of transistor required for quaternary voltage mode logic is 3 times more as compared to binary. As quaternary voltage mode circuit required large area as compared to quaternary current mode circuit but power consumption required in quaternary voltage mode circuit is less than that required in quaternary current mode circuit.
A Low Power High Bandwidth Four Quadrant Analog Multiplier in 32 NM CNFET Tec...VLSICS Design
Carbon Nanotube Field Effect Transistor (CNFET) is a promising new technology that overcomes several limitations of traditional silicon integrated circuit technology. In recent years, the potential of CNFET for analog circuit applications has been explored. This paper proposes a novel four quadrant analog multiplier design using CNFETs. The simulation based on 32nm CNFET technology shows that the proposed multiplier has very low harmonic distortion (<0.45%), large input range (±400mV), large bandwidth (~50GHz) and low power consumption (~247µW), while operating at a supply voltage of ±0.9V.
Design and Analysis of Power and Variability Aware Digital Summing CircuitIDES Editor
Due to aggressive scaling and process imperfection
in sub-45 nm technology node Vt (threshold voltage) shift is
more pronounced causing large variations in circuit response.
Therefore, this paper presents the analyses of various popular
1-bit digital summing circuits in light of PVT (process, voltage
and temperature) variations to verify their functionality and
robustness. The investigation is carried with ±3ó process
parameters and ±10% VDD (supply voltage) variation by applying
Gaussian distribution and Monte Carlo analysis at 22 nm
technology node on HSPICE environment. Design guidelines
are derived to select the most suitable topology for the design
features required. Transmission Gate (TG)-based digital
summing circuit is found to be the most robust against PVT
variations. Hence, a TG-based digital summing circuit is
implemented using carbon nanotube field effect transistor
(CNFET). This implementation offers tighter spread in
propagation delay (3×), power dissipation (1.14×) and EDP
(energy delay product) (1.1×) at nominal voltage of VDD = 0.95V
compared to MOSFET-based (TG – topology) digital summing
circuit implying its robustness against PVT variations.
Distortion Analysis of Differential AmplifierIOSR Journals
Abstract: The linearity of the CMOS is of major concern in the design of many analog circuits. In this paper the nonlinearity behavior of CMOS analog integrated circuits is investigated.The basic building block of analog integrated circuits such as differential amplifier with current mirror load have been chosen for harmonic distortion analysis.A mechanism to analyze the distortion of CMOS circuits in deep submicron technology that can be easily used to detect the distortion is built.The MOSFET model used for simulation is TSMC BSIM3 SPICE model from 0.13-μm CMOS process technology. HSPICE circuit simulator tool is used for distortion analysis of CMOS circuits. The MOS model used in this paper includes short-channel effects and gate-source capacitance, gate-drain capacitance, output resistance of MOS transistor. Analytical results are compared with simulation results and the influences of circuit parameters on circuit linearity are discussed.
Keywords: Analog Integrated Circuits, CMOSanalog integrated circuits, harmonic distortion, HSPICE, Short-channel effects, small signal analysis, transient analysis.
Codec Scheme for Power Optimization in VLSI InterconnectsIJEEE
This paper presents a codec scheme for optimizing power in VLSI Interconnects. It is based on the traditional bus encoding method which is considered to be one of the most effective ways of power and delay reduction. The work done aims at optimizing power by designing the scheme using Full-Custom design approach. The model has been designed and implemented using Cadence Virtuoso Analog Design Suite in 0.18µm CMOS technology. Power has been computed for different possible combinations of input data. Delay has been reckoned for the maximum power consuming input combination. Layout editor has been used to generate the physical description of the circuit. The 4 bit input data combination consuming maximum dynamic power of 6.44µW and propagation delay of 722.7ps is “1000” with previously transmitted 4 bit data being “0111”. A significant power reduction of 38.89% has been observed by designing the scheme using Full-Custom approach as compared to the conventional Semi-Custom approach of design.
Design of ultra low power 8 channel analog multiplexer using dynamic threshol...VLSICS Design
The design of an ultra low voltage, low power high
speed 8 channel Analog multiplexer in 180nm CMOS
technology is presented. A modified transmission ga
te using a dynamic threshold voltage MOSFET
(DTMOS
)
is employed in the design. The design is optimized
with respect to critical requirements like short
switching time, low power dissipation, good lineari
ty and high dynamic range with an operating voltage
of
0.4V. The ON and OFF resistances achieved are 32 oh
ms and 10Mohms respectively with a switching
speed of 10MHz. The power dissipation obtained is a
round 2.65uW for a dynamic range of 1uV to 0.4V.
A NEW APPROACH TO DESIGN LOW POWER CMOS FLASH A/D CONVERTERVLSICS Design
In the present paper, a 4-bit flash analog to digital converter for low power SoC application is presented. CMOS inverter has been used as a comparator and by adjusting the ratio of channel width and length, the switching threshold of the CMOS inverter is varied to detect the input analog signal. The simulation results show that this proposed 4-bit flash ADC consumes about 12.4 mW at 200M sample/s with 3.3V supply voltage in TSMC 0.35 µm process. Compared with the traditional flash ADC, this proposed method can reduce about 78% in power consumption.
A LOW POWER, LOW PHASE NOISE CMOS LC OSCILLATORIJEEE
In this paper a Double Cross Coupled Inductor capacitor based Voltage Control Oscillator (LC-VCO) is designed. In the proposed circuit the phase noise, tuning range with respect to control voltage, output power and the power dissipation of the circuit is analysed. Phase noise of approximate -96 dBc/Hz at frequency of 1MHz, frequency tuning range of 4.8 to 8.3 GHz (corresponding to 53.0% tuning range) obtained by varying the control voltage from 0 to 2.0 V, Output power of circuit -8.92 dBm at 50 Ohm resistance terminal and the power consumption of Circuit is 3.8 mW. This VCO are designed for 5.5 GHz. The circuit is designed on the UMC 180nm CMOS technology and all the simulation results are obtained using cadence SPECTRE Simulator.
A Simulation Based Analysis of Lowering Dynamic Power in a CMOS Inverteridescitation
With the increase in demand of high fidelity
portable devices, there is more and more emphasis laying
down on the development of low power and high performance
systems. In the next generation processors, the low power
design has to be incorporated into fundamental computation
units, such as adder. CMOS circuit design plays a crucial role
in designing of these computation units (like adder and
multiplier) so if there is any optimal way to reduce the power
dissipation in CMOS circuits then it will directly lower down
the power dissipation of other circuits and logic gates as well.
In this paper we have studied and analyzed different
techniques to reduce the dynamic power of CMOS circuit
with the help of performing simulation on some significant
factors (i.e device characteristics) of respective circuitry
designs by using Cadence-Virtuoso tool.
International Journal of Engineering Research and Development (IJERD)IJERD Editor
International Journal of Engineering Research and Development is an international premier peer reviewed open access engineering and technology journal promoting the discovery, innovation, advancement and dissemination of basic and transitional knowledge in engineering, technology and related disciplines.
CNFET BASED BASIC GATES AND A NOVEL FULLADDER CELLVLSICS Design
In this paper two novel high performance designs for AND and OR basic gates and a novel Full-Adder Cell are presented. These designs are based on carbon nanotube technology. In order to compare the proposed designs with previous ones both MOSFET based and CNFET based circuits are selected. By the way the proposed designs have better performance in comparison with previous designs in terms of speed, power consumption and power-delay product (PDP).
An improved design of CMOS dynamic latch comparator with dual input dual output with a simple
design of three stages is represented. The basic disadvantages of latch type comparators are overcome by
producing an edge triggered comparison. The circuit is designed for a resolution of 300nV and the power
consumption is reduced to 450uW. It is designed for 1.8V DC supply voltage and 1 MHz clock frequency for
PVT variations. The simulation of the comparator is done in Cadence® Virtuoso Analog Design Environment
using 180nm technology. The error quotient is reduced less than 5% by adding a buffer stage. The delay is
brought down to 5nS. The active area appreciably is reduced. Layout of the proposed comparator has been
simulated in Cadence® Virtuoso Layout XL Design Environment. DRC and LVS have been verified.
Design and performance analysis of low phase noise LC-voltage controlled osci...TELKOMNIKA JOURNAL
Voltage controlled oscillator (VCO) offers the radio frequency (RF) system designer a freedom to select the required frequency. Today’s wireless communication system imposes a very stringent requirement in terms of phase noise generated in VCO. This study presents an inductive source degeneration technique to improve the phase noise performance of the inductance-capacitance (LC)-VCO. Double cross-coupled topology has been chosen for the proposed VCO. The post layout simulations with the parasitic resistance, inductance, capacitance (RLC) extracted view is carried out with united microelectronics corporations (UMC) 0.18 µm process by spectre simulator of cadence tools. The proposed VCO provides a phase noise
of -124.3 dBc/Hz @ 1 MHz. The tuning range obtained is 19.87% with a centre frequency of 2.46 GHz which makes it suitable for industrial, scientific, and medical (ISM) band applications. It consumes a power of 2.10 mW. Also, a good figure of merit of -189 is achieved. The total layout area occupied is 477×545 µm2.
High Performance and Low power VLSI CMOS Circuit Designs using ONOFIC Approach IJERA Editor
Leakage power dissipation a major concern for scaling down portable devices. Improving high performance with reduced power consumption and chip area are the main constraint for designing VLSI CMOS circuits. In this paper, high performance and low power ONOFIC approach for VLSI CMOS circuits have been implemented. Mostly the concentrated part in deep sub micron regime is the power dissipation. Many techniques have been proposed for reducing leakage current in deep sub micron but with some limitations they are not suitable for actual requirements. Here we discussed two techniques named LECTOR & ONOFIC. The proposed On/Off Logic (ONOFIC) serves the needs for deep sub micron with its reduced power dissipation and increased performance in VLSI circuits. Thus the proposed ONOFIC approach results have been compared with the LECTOR technique and observed that the proposed technique improves the performance and reduce the power dissipation.
Optimization of Digitally Controlled Oscillator with Low Poweriosrjce
IOSR journal of VLSI and Signal Processing (IOSRJVSP) is a double blind peer reviewed International Journal that publishes articles which contribute new results in all areas of VLSI Design & Signal Processing. The goal of this journal is to bring together researchers and practitioners from academia and industry to focus on advanced VLSI Design & Signal Processing concepts and establishing new collaborations in these areas.
Design and realization of microelectronic systems using VLSI/ULSI technologies require close collaboration among scientists and engineers in the fields of systems architecture, logic and circuit design, chips and wafer fabrication, packaging, testing and systems applications. Generation of specifications, design and verification must be performed at all abstraction levels, including the system, register-transfer, logic, circuit, transistor and process levels
ANALYSIS OF CMOS AND MTCMOS CIRCUITS USING 250 NANO METER TECHNOLOGYcscpconf
The low-power consumption with less delay time has become an important issue in the recent
trends of VLSI. In these days, the low power systems with high speed are highly preferable
everywhere. Designers need to understand how low-power techniques affect performance
attributes, and have to choose a set of techniques that are consistent with these attributes .The
main objective of this paper is to describe, how to achieve low power consumption with
approximately same delay time in a single circuit. In this paper, we make circuits with CMOS
and MTCMOS techniques and check out its power and delay characteristics. The circuits
designed using MTCMOS technique gives least power consumption.
All the pre-layout simulations have been performed at 250nm technology on tanner EDA tool.
Analysis of CMOS and MTCMOS Circuits Using 250 Nano Meter Technology csandit
The low-power consumption with less delay time has become an important issue in the recent
trends of VLSI. In these days, the low power systems with high speed are highly preferable
everywhere. Designers need to understand how low-power techniques affect performance
attributes, and have to choose a set of techniques that are consistent with these attributes .The
main objective of this paper is to describe, how to achieve low power consumption with
approximately same delay time in a single circuit. In this paper, we make circuits with CMOS
and MTCMOS techniques and check out its power and delay characteristics. The circuits
designed using MTCMOS technique gives least power consumption.
All the pre-layout simulations have been performed at 250nm technology on tanner EDA tool.
Similar to M.TECH IEEE.Technical seminar paper for Vlsi design and embedded systems. (20)
In the rapidly evolving landscape of technologies, XML continues to play a vital role in structuring, storing, and transporting data across diverse systems. The recent advancements in artificial intelligence (AI) present new methodologies for enhancing XML development workflows, introducing efficiency, automation, and intelligent capabilities. This presentation will outline the scope and perspective of utilizing AI in XML development. The potential benefits and the possible pitfalls will be highlighted, providing a balanced view of the subject.
We will explore the capabilities of AI in understanding XML markup languages and autonomously creating structured XML content. Additionally, we will examine the capacity of AI to enrich plain text with appropriate XML markup. Practical examples and methodological guidelines will be provided to elucidate how AI can be effectively prompted to interpret and generate accurate XML markup.
Further emphasis will be placed on the role of AI in developing XSLT, or schemas such as XSD and Schematron. We will address the techniques and strategies adopted to create prompts for generating code, explaining code, or refactoring the code, and the results achieved.
The discussion will extend to how AI can be used to transform XML content. In particular, the focus will be on the use of AI XPath extension functions in XSLT, Schematron, Schematron Quick Fixes, or for XML content refactoring.
The presentation aims to deliver a comprehensive overview of AI usage in XML development, providing attendees with the necessary knowledge to make informed decisions. Whether you’re at the early stages of adopting AI or considering integrating it in advanced XML development, this presentation will cover all levels of expertise.
By highlighting the potential advantages and challenges of integrating AI with XML development tools and languages, the presentation seeks to inspire thoughtful conversation around the future of XML development. We’ll not only delve into the technical aspects of AI-powered XML development but also discuss practical implications and possible future directions.
How to Get CNIC Information System with Paksim Ga.pptxdanishmna97
Pakdata Cf is a groundbreaking system designed to streamline and facilitate access to CNIC information. This innovative platform leverages advanced technology to provide users with efficient and secure access to their CNIC details.
zkStudyClub - Reef: Fast Succinct Non-Interactive Zero-Knowledge Regex ProofsAlex Pruden
This paper presents Reef, a system for generating publicly verifiable succinct non-interactive zero-knowledge proofs that a committed document matches or does not match a regular expression. We describe applications such as proving the strength of passwords, the provenance of email despite redactions, the validity of oblivious DNS queries, and the existence of mutations in DNA. Reef supports the Perl Compatible Regular Expression syntax, including wildcards, alternation, ranges, capture groups, Kleene star, negations, and lookarounds. Reef introduces a new type of automata, Skipping Alternating Finite Automata (SAFA), that skips irrelevant parts of a document when producing proofs without undermining soundness, and instantiates SAFA with a lookup argument. Our experimental evaluation confirms that Reef can generate proofs for documents with 32M characters; the proofs are small and cheap to verify (under a second).
Paper: https://eprint.iacr.org/2023/1886
UiPath Test Automation using UiPath Test Suite series, part 6DianaGray10
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Throughout the session, participants will discover how this synergy empowers testers to automate repetitive tasks, enhance testing accuracy, and expedite the software testing life cycle. Topics covered include the seamless integration process, practical use cases, and the benefits of harnessing AI-driven automation for UiPath testing initiatives. By attending this webinar, testers, and automation professionals can gain valuable insights into harnessing the power of AI to optimize their test automation workflows within the UiPath ecosystem, ultimately driving efficiency and quality in software development processes.
What will you get from this session?
1. Insights into integrating generative AI.
2. Understanding how this integration enhances test automation within the UiPath platform
3. Practical demonstrations
4. Exploration of real-world use cases illustrating the benefits of AI-driven test automation for UiPath
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Observability Concepts EVERY Developer Should Know -- DeveloperWeek Europe.pdfPaige Cruz
Monitoring and observability aren’t traditionally found in software curriculums and many of us cobble this knowledge together from whatever vendor or ecosystem we were first introduced to and whatever is a part of your current company’s observability stack.
While the dev and ops silo continues to crumble….many organizations still relegate monitoring & observability as the purview of ops, infra and SRE teams. This is a mistake - achieving a highly observable system requires collaboration up and down the stack.
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GraphSummit Singapore | The Future of Agility: Supercharging Digital Transfor...Neo4j
Leonard Jayamohan, Partner & Generative AI Lead, Deloitte
This keynote will reveal how Deloitte leverages Neo4j’s graph power for groundbreaking digital twin solutions, achieving a staggering 100x performance boost. Discover the essential role knowledge graphs play in successful generative AI implementations. Plus, get an exclusive look at an innovative Neo4j + Generative AI solution Deloitte is developing in-house.
LF Energy Webinar: Electrical Grid Modelling and Simulation Through PowSyBl -...DanBrown980551
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During the webinar, you will discover the PowSyBl ecosystem as well as handle and study an electrical network through an interactive Python notebook.
PowSyBl is an open source project hosted by LF Energy, which offers a comprehensive set of features for electrical grid modelling and simulation. Among other advanced features, PowSyBl provides:
- A fully editable and extendable library for grid component modelling;
- Visualization tools to display your network;
- Grid simulation tools, such as power flows, security analyses (with or without remedial actions) and sensitivity analyses;
The framework is mostly written in Java, with a Python binding so that Python developers can access PowSyBl functionalities as well.
What you will learn during the webinar:
- For beginners: discover PowSyBl's functionalities through a quick general presentation and the notebook, without needing any expert coding skills;
- For advanced developers: master the skills to efficiently apply PowSyBl functionalities to your real-world scenarios.
Generative AI Deep Dive: Advancing from Proof of Concept to ProductionAggregage
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M.TECH IEEE.Technical seminar paper for Vlsi design and embedded systems.
1. Design of CMOS Ternary Logic Family based on
Single Supply Voltage
V. T. Gaikwad P. R. Deshmukh
Department of Information Technology, Amravati (M.S.), India
Sipna COET, Amravati (M.S.), India,
vtgaikwad@rediffmail.com
Abstract— Since inception, CMOS logic is considered for
implementation of only binary logic. As the circuit complexity is
increasing, the interconnection in binary occupies large area on a
VLSI chip and thus, degrading the performance of binary. Hence
the non binary higher radix logic which is called as multi valued
logic (MVL) is considered as solution to this issue. A ternary logic
or a three-valued logic is considered as the best radix of several
MVL systems. In this paper, the designs of ternary logic circuits
are proposed based on single power supply voltage. The proposed
ternary logic gates are useful in designing the ternary logic
circuits. The proposed designs are based on the use of only
enhancement type MOSFETS so that it can be implemented with
recent CMOS technology.
The design of a set of inverters and basic ternary logic gates
is proposed. The transistor count in the basic ternary gates is
being reduced thereby improving component density. The
proposed GATES are designed & simulated with the help of
Microwind EDA tool & can be implemented at its layout side
using VLSI CMOS technology.
Keywords – CMOS technology, Radix, Enhancement
MOSFET, Multi Valued Logic, Ternary Logic, VLSI.
I. INTRODUCTION
Because of the advanced MOS technology & an easily
implemented binary algebra, the circuit complexity of binary
logic has been successfully pushed to the VLSI/ULSI level.
However, there exists some problem in present-day binary
systems that of interconnection, both on chip and off chips. On
chip, the interconnection problem is in the wire routing. As the
scale of integration continues to increase, the silicon area for
wire routing becomes increasingly greater than that for the
active logic elements, owing to the vast information exchanges
between each active block in the system. Therefore the speed
of a circuit decreases, due to the accompanied larger
capacitance with the longer interconnection lines. In the other
respect, the interconnections between chips face the pin
number limit. As well as the pin counts increasing at an
incredible rate as the chip becomes larger, the system
performance is also sacrificed due to frequent off-chip
connections. All the above difficulties can be reduced if the
multi valued logic is used for interconnections as it contents
more information per interconnection as compared to binary
interconnections. Therefore the multi valued logic is now
being considered for designing of VLSI/ULSI digital systems
due to its advantages over binary logic [1] [2] [3]. The multi
valued implementation will not only allow for transmitting
more information but it effectively reduces the chip area also.
The other advantage of using the MVL for interconnection is
that the number of pin outs and interconnections can be
reduced [4].
The multi valued logic memories are implemented
commercially. Considering the cost and radix relation
theoretically, the ternary logic circuits are more economical
than binary logic circuits [5-6].
But the complexity in design is a main draw back in
multiple valued logic circuits as compared to the binary logic
circuits. There has been development in the MVL circuit
implementation with the growth of device technology.
Several authors [6-15] have proposed the realization of
ternary CMOS circuits. In most of these designs, the power
supply voltages higher than the MOSFETs threshold voltages
are used which leads to the high power consumption. The
Carbon Nanotube FET (CNTFET) based multi valued circuits
have been reported by some authors [16-17] where they have
specified the issue related to metallic CNTs.
II. DESIGN AND SIMULATION OF TERNARY
LOGIC GATES
In design of digital systems, the inverter, NOR gate, and
NAND gates are considered to be the basic building blocks.
We propose the implementations of ternary inverter, NOR
gate, and NAND gate. The prime objective in our work is to
minimize the power consumption and propagation delay times
thereby reducing the number of transistors, by eliminating the
use of resistors. In the proposed designs the smaller single
supply voltage and the MOSFETs with smaller threshold
voltage are used. Three logic levels are represented by states 0,
1, 2 with potential (0v), (0.5v), and + Vcc (+1v) respectively.
III. DESIGN OF TERNARY INVERTER
The ternary inverter is a complement function; which in
the binary notation is known as an inverter. It is also called as
the MVL-NOT function. Depending on the inversion logic,
ternary inverters are of tree types namely, STI (Simple
Ternary Inverter), NTI (Negative Ternary Inverter) and PTI
(Positive Ternary Inverter). The logic functions of these
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2. inverter are shown in Tab. 1. The rule of ternary inversion for
these three types of basic ternary operations are defined by in
equation (1)
𝑋𝑐 = �
𝐶 , 𝑖𝑓 𝑥 = 1
𝐶 − 𝑋 , 𝑖𝑓 𝑥 ≠ 1
(1)
Where the value of 𝐶 in above equation is 2 for a PTI, 1 for a
STI and 0 for a NTI.
A MVL-NOT function is an elementary function in
MVL. High accuracy is necessary for voltage mode multi-
valued signal as the voltage levels for each logic level are
equal division of VDD.
Table I gives the truth table for these inverters
TABLE I. TRUTH TABLE OF TERNARY INVERTERS.
X NTI PTI STI
0 2 2 2
1 0 2 1
2 0 0 0
The logic symbols of these three inverters are given in Fig. 1.
(a)
(b)
(c)
Fig.1 Ternary Inverter symbols (a) STI. (b) NTI (c) PTI
A. Commutation Point of Inverters
The commutation voltage Vc is prime aspect in proper
design of ternary inverters which works as a switching
element. The commutation point is deciding the threshold of
switching activity of the inverter. The sizing of NMOS &
PMOS devices has a strong influence on the commutation
point Vc. The commutation voltage of an inverter can be given
as,
𝑽𝒄 =
𝑲.𝑽 𝑻𝑵 + 𝑽 𝑫𝑫− 𝑽 𝑷𝑷
𝟏+𝑲
(2)
Where
K = �
µn
Wn
Ln
µp Wp
Lp
𝝁 𝒏 - mobility of electron (600 V.cm-2
)
𝝁 𝒑 - mobility of holes (270 V. cm-2
)
𝑾𝒏 - n-channel MOS width ( in µm)
𝑳𝒏 - n- channel MOS lencth ( in μm)
𝑾𝒑 - p channel MOS width ( in µm)
Lp - p channel MOS length ( in µm)
𝑽 𝑫𝑫 - supply voltage (1.0V)
𝑽 𝑻𝑵 - Threshold voltage of n-channel device.
VTP - threshold voltage of p-channel device
For the proposed designs of STI, NTI & PTI, the appropriate
values of W/L based on equation (2) are used.
The commutation points of the inverters can observe on the
respective transfer characteristics.
B. Design of STI, NTI & PTI
MOS implementation of STI is described in [13, 14]. In
traditional design of simple ternary inverter (STI), positive
ternary inverter (PTI), negative ternary inverter (NTI) use a
pass transistors/CMOS transmission gate at its output is done
by using dual supply voltage.
Alternative new implementation of these three inverters is
shown in Fig. 2. The designs using single supply voltage &
without using the transmission gate or pass transistors leads to
a significant reduction in the power dissipation as well as in
propagation delays.
Fig 2. Schematic of CMOS STI, NTI & PTI.
Transistor T1 is enhancement PMOS & transistor T2 are
enhancement NMOS. The schematic for STI, NTI & PTI is
same but with the variation in width and length parameter of
each. Fig. 3 shows design layout of a Simple Ternary Inverter
(STI) implemented using a PMOS transistor & NMOS
transistor with Logic 2 at VDD, Logic 0 at GND (0 V) & logic
1 is a middle voltage between VDD & GND. The resistance of
channels can be change by changing the length-to-width ratio
of the PMOS and NMOS transistors. Thus, the length-to-width
ratio can be effectively used to change the resistance of
transistors as per the design requirement [8] [9].
3. Fig.3. Layout of Standard Ternary Inverter (STI)
The set of ternary inverters and logic gates like TNAND
(Ternary NAND) and TNOR (Ternary NOR) can be used to
realize the complex ternary functions
The circuit operation of this STI is simulated and
analyzed using Microwind design and simulation tool. Fig. 7
shows the output Voltage Vs Time characteristics and Fig. 8
shows the transfer characteristics of STI. Table II gives the
logic level voltages for inputs and outputs of ternary inverters.
TABLE II. STI LOGIC LEVEL VOLTAGE
Logic
Value
Voltage Level
I/p (V)
Voltage Level
O/p (V)
0 0 1.0
1 0.5 0.51
2 1.0 0
The power dissipation and the transition time of output
voltage signal are observed to be very small as specified in
result section.
IV. DESIGN OF TERNARY NAND GATE
A TNAND function gives the inversion of the minimum
value of the input signal where input signal belongs to 0, 1 and 2
or -1, 0 & +1 in balance ternary [1]. The NAND output can be
defined as,
Y= INV [ Min (I1,I2,I3…...In) ] (3)
The truth table of the function is given in Table III.
The CMOS design of proposed TNAND based on single supply
voltage is shown in Fig. 4. The results of the design are simulated
using Microwind. The transient characteristic of TNAND is
shown Fig 10 for Voltage Vs Time by applying different input
logic levels.
Fig.4. Proposed NAND with Standard Ternary logic
TABLE III: TERNARY NAND TRUTH TABLE.
V. DESIGN OF TERNARY NOR GATE
A TNOR o/p function gives the inversion of the
maximum value of the input signal [1]. Thus the NOR output can
be defined as,
Y= INV [ Max (I1,I2,I3…...In) ] (4)
TABLE IV TERNARY NOR TRUTH TABLE
Input A Input B
O/P
TNOR
0 0 2
0 1 1
0 2 0
1 0 1
1 1 1
1 2 0
2 0 0
2 1 0
2 2 0
Ternary NOR gate con be implemented with the same analogy
as that of TNAND.
Input A Input B
O/P
TNAND
0 0 2
0 1 2
0 2 2
1 0 2
1 1 1
1 2 1
2 0 2
2 1 1
2 2 0
4. VI. DESIGN OF TAND & TOR GATES
The basic elements of ternary logic family are STI,
TNAND & TNOR. By using these gates we can further
implement TAND, TOR. The implementation is shown with
logic symbol in Fig. 6. The logic gates like TEXOR and
TXNOR can also be implemented using this basic gate.
In multi valued logic, AND is basically a MIN function
and OR is a MAX function[1], which are specified in equation
(5) and in equation (6) respectively.
TAND Output Y= MIN [I1,I2,I3…...In] (5)
TOR Output Y= MAX [I1,I2,I3…...In] (6)
TAND gate and TOR gates can be implemented by inverting
the outputs of TNAND & TNOR respectively by using the
STI.
a) TAND & TOR from TNAND & TNOR
b) Symbol of TAND & TOR gate
Fig. 6. Logic symbol for TAND & TOR
In the design of TAND & TOR, the STI, proposed in this
work is used for the inversion at the output of TNAND &
TNOR. As the STI is designed without using transmission
gate/ pass transistor, it effectively reduces the component
count in the design of TAND & TOR gates. Operation of these
designs is verified & analyzed. Fig 11 shows the verification
of output of TAND for different logic levels at the input.
VII. RESULTS & DISCUSSIONS
A. Simulation & verification of outputs
The proposed ternary logic gates are design & their
performance is simulated for 45 nm technology using Microwind
EDA tool. Fig.7 shows the transient characteristic and Fig. 8
shows the transfer characteristic of proposed STI.
The outputs for NTI and PTI are observed as per the truth
tables and are shown with their transient characteristics in Fig. 9
and in Fig. 10 respectively.
The truth tables of ternary NAND & ternary AND are verified by
applying all logic level combinations at the inputs. The
corresponding input and output characteristics are shown in Fig
11 for ternary NAND gate and in Fig 12 for ternary AND gate.
Fig 7.Transient characteristic for STI
Fig 8. Transfer characeristic of STI
Fig.9. Transient characteristic of NTI
Fig.10. Transient characteristic of PTI
5. Fig.11. Transient Characteristic of TNAND.
Fig.12. Output Voltage Vs Time Characteristic of TAND.
B. Power Dissipation
The power dissipation P depends on three main factors
capacitance C, the supply voltage VDD and the clock frequency
f. For a CMOS inverter, equation (7) below, shows a linear
dependence of the power dissipation on these three factors.
P=
1
2
C V2
DD f (7)
Where
C - output load capacitance (Farad)
VDD - supply voltage (V)
f - clock frequency (HZ)
The average power dissipation of these ternary gates
are calculated for the maximum output voltage swing. The
designs are proposed with the minimum transistor count
thereby reducing the overall power dissipation and reducing
the transition times.
Table V shows the average power dissipation over
500 ns time scale associated with the respective logic gate.
TABLE V. POWER DISSIPATION
Gate Power Dissipation
STI 0.065 µW
TNAND 0.191 mW
TAND 0.213 mW
Some of the results for power dissipation are compared with
the available results of previous designs & summarized in
following table VI.
TABLE VI: COMPARISON OF POWER DISSIPATION OF STI
Ref [6] Ref [14] Ref [12]
Proposed
Work
2.56
mw
0.7 µw 1.9 µw 0.065 µw
C. Rise time & Fall time
The rise time & fall time is mainly contributing to the
propagation delay of the logic gate. The proposed designs are
simulated to obtain rise time and fall time for various
switching transitions. The rise times and fall times of STI are
given in table VII
TABLE VII. RISE TIME & FALL TIME OF STI
O/p Transition
Rise Time/Fall
Time (ps)
1- 2 0.9
2 -1 1.1
1- 0 0.9
0 - 1 1.2
2 - 0 1.6
As the inverter is considered to be the basic switching
element in any design, the transition time of STI is considered
to be reference is observed to be very small.
CONCLUSION
Most of the traditional designs are based on ternary
logic, which requires dual power supply. Similarly for the
design of inverter as a basic switching element, the
transmission gates/ transistors are used to pull the output at
specific required voltage level. In the proposed designs, these
output transmission gates/pull up transistors is eliminated from
the inverters, thereby reducing the component count.
Similarly use of single power supply to implement the ternary
logic gates has lead to significant reductions in the overall
power dissipation and improving the transition time. The
proposed logic gates are useful further to design the low power
ternary circuits.
Considering the various advantages of the multi
valued logic, the appropriate design of the MVL logic gates is
important so that it will lead to the further development and its
applications in this area.
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